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Commit 423861ac authored by Rabeeh Khoury's avatar Rabeeh Khoury
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Update release to may-29 release and misc changes 

1. Poweroff the HoneyComb board by asserting SUS_S5# signal
2. Add USB3.0 DWC3 workaround by disabling parkmode
3. Keep flexspi divisor as default which is ~17MHz. This enables using
the carrier board SPI that is limited in speed due to the analogue mux
connected to it.
4. Remove uefi build and update LSDK20.04 to may-29 update. UEFI is
temporarily hosted at https://github.com/SolidRun/lx2160a_uefi until
fully upstreamed.
5. Add 4x25Gbps MC config
Signed-off-by: default avatarRabeeh Khoury <rabeeh@solid-run.com>
parent 67b73cd2
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patches/atf/0003-lx2160acex7-assert-SUS_S5-GPIO-to-poweroff-the-COM.patch 0 → 100644
View file @ 423861ac
From c9828291218cd363f099ea90f09cc66cf13f86ba Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Thu, 3 Sep 2020 14:08:44 +0300
Subject: [PATCH 3/3] lx2160acex7: assert SUS_S5# GPIO to poweroff the COM
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
plat/nxp/soc-lx2160/aarch64/lx2160.S | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/plat/nxp/soc-lx2160/aarch64/lx2160.S b/plat/nxp/soc-lx2160/aarch64/lx2160.S
index 7b2b67b..83f5889 100644
--- a/plat/nxp/soc-lx2160/aarch64/lx2160.S
+++ b/plat/nxp/soc-lx2160/aarch64/lx2160.S
@@ -668,6 +668,10 @@ _soc_sys_off:
* spurious timeout reset request
* workaround: MASK RESET REQ RPTOE
*/
+ mov x3, #NXP_GPIO3_ADDR
+ mov w1, #0x01000000
+ str w1, [x3]
+
ldr x0, =NXP_RESET_ADDR
ldr w1, =RSTRQMR_RPTOE_MASK
str w1, [x0, #RST_RSTRQMR1_OFFSET]
--
2.17.1
patches/linux-LSDK-20.04/7ba6b09fda5e0cb741ee56f3264665e0edc64822.patch 0 → 100644
View file @ 423861ac
commit 7ba6b09fda5e0cb741ee56f3264665e0edc64822
Author: Neil Armstrong <narmstrong@baylibre.com>
Date: Fri Feb 21 10:15:31 2020 +0100
usb: dwc3: core: add support for disabling SS instances in park mode
In certain circumstances, the XHCI SuperSpeed instance in park mode
can fail to recover, thus on Amlogic G12A/G12B/SM1 SoCs when there is high
load on the single XHCI SuperSpeed instance, the controller can crash like:
xhci-hcd xhci-hcd.0.auto: xHCI host not responding to stop endpoint command.
xhci-hcd xhci-hcd.0.auto: Host halt failed, -110
xhci-hcd xhci-hcd.0.auto: xHCI host controller not responding, assume dead
xhci-hcd xhci-hcd.0.auto: xHCI host not responding to stop endpoint command.
hub 2-1.1:1.0: hub_ext_port_status failed (err = -22)
xhci-hcd xhci-hcd.0.auto: HC died; cleaning up
usb 2-1.1-port1: cannot reset (err = -22)
Setting the PARKMODE_DISABLE_SS bit in the DWC3_USB3_GUCTL1 mitigates
the issue. The bit is described as :
"When this bit is set to '1' all SS bus instances in park mode are disabled"
Synopsys explains:
The GUCTL1.PARKMODE_DISABLE_SS is only available in
dwc_usb3 controller running in host mode.
This should not be set for other IPs.
This can be disabled by default based on IP, but I recommend to have a
property to enable this feature for devices that need this.
CC: Dongjin Kim <tobetter@gmail.com>
Cc: Jianxin Pan <jianxin.pan@amlogic.com>
Cc: Thinh Nguyen <thinhn@synopsys.com>
Cc: Jun Li <lijun.kernel@gmail.com>
Reported-by: Tim <elatllat@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Felipe Balbi <balbi@kernel.org>
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 1d85c42b9c67..43bd5b1ea9e2 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1029,6 +1029,9 @@ static int dwc3_core_init(struct dwc3 *dwc)
if (dwc->dis_tx_ipgap_linecheck_quirk)
reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
+ if (dwc->parkmode_disable_ss_quirk)
+ reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
+
dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
}
@@ -1342,6 +1345,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
"snps,dis-del-phy-power-chg-quirk");
dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
"snps,dis-tx-ipgap-linecheck-quirk");
+ dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
+ "snps,parkmode-disable-ss-quirk");
dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
"snps,tx_de_emphasis_quirk");
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 77c4a9abe365..3ecc69c5b150 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -249,6 +249,7 @@
#define DWC3_GUCTL_HSTINAUTORETRY BIT(14)
/* Global User Control 1 Register */
+#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
@@ -1024,6 +1025,8 @@ struct dwc3_scratchpad_array {
* change quirk.
* @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
* check during HS transmit.
+ * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
+ * instances in park mode.
* @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
* @tx_de_emphasis: Tx de-emphasis value
* 0 - -6dB de-emphasis
@@ -1215,6 +1218,7 @@ struct dwc3 {
unsigned dis_u2_freeclk_exists_quirk:1;
unsigned dis_del_phy_power_chg_quirk:1;
unsigned dis_tx_ipgap_linecheck_quirk:1;
+ unsigned parkmode_disable_ss_quirk:1;
unsigned tx_de_emphasis_quirk:1;
unsigned tx_de_emphasis:2;
patches/mc-utils/0002-Add-CEX7-4x25Gbps-support.patch 0 → 100644
View file @ 423861ac
From 7446630daae30107311f30c22855d6b678dbba67 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Thu, 24 Sep 2020 16:48:52 +0300
Subject: [PATCH] Add CEX7 4x25Gbps support
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
config/lx2160a/CEX7/dpc-quad-25g.dts | 91 ++++
config/lx2160a/CEX7/dpl-eth.quad-25g.19.dts | 516 ++++++++++++++++++++
2 files changed, 607 insertions(+)
create mode 100644 config/lx2160a/CEX7/dpc-quad-25g.dts
create mode 100644 config/lx2160a/CEX7/dpl-eth.quad-25g.19.dts
diff --git a/config/lx2160a/CEX7/dpc-quad-25g.dts b/config/lx2160a/CEX7/dpc-quad-25g.dts
new file mode 100644
index 0000000..3aeb1d2
--- /dev/null
+++ b/config/lx2160a/CEX7/dpc-quad-25g.dts
@@ -0,0 +1,91 @@
+/*
+* Copyright 2018 NXP
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* * Neither the name of the above-listed copyright holders nor the
+* names of any contributors may be used to endorse or promote products
+* derived from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+* This DPC showcases one Linux configuration for lx2160a boards.
+*/
+
+/dts-v1/;
+
+/ {
+
+ resources {
+
+ icid_pools {
+
+ icid_pool@1 {
+ num = <0x64>;
+ base_icid = <0x0>;
+ };
+ };
+ };
+
+ mc_general {
+
+ log {
+ mode = "LOG_MODE_ON";
+ level = "LOG_LEVEL_WARNING";
+ };
+
+ console {
+ mode = "CONSOLE_MODE_OFF";
+ uart_id = <0x4>;
+ level = "LOG_LEVEL_WARNING";
+ };
+ };
+
+ controllers {
+
+ qbman {
+ /* Transform this number of 8-WQ channels into four times
+ * as many 2-WQ channels. This allows the creation of a
+ * larger number of DPCONs.
+ */
+ wq_ch_conversion = <32>;
+ };
+ };
+
+ board_info {
+ ports {
+ mac@3 {
+ link_type = "MAC_LINK_TYPE_FIXED";
+ };
+ mac@4 {
+ link_type = "MAC_LINK_TYPE_FIXED";
+ };
+ mac@5 {
+ link_type = "MAC_LINK_TYPE_FIXED";
+ };
+ mac@6 {
+ link_type = "MAC_LINK_TYPE_FIXED";
+ };
+ mac@17 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ };
+ };
+};
diff --git a/config/lx2160a/CEX7/dpl-eth.quad-25g.19.dts b/config/lx2160a/CEX7/dpl-eth.quad-25g.19.dts
new file mode 100644
index 0000000..e62a85e
--- /dev/null
+++ b/config/lx2160a/CEX7/dpl-eth.quad-25g.19.dts
@@ -0,0 +1,516 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/ {
+ dpl-version = <0xa>;
+ /*****************************************************************
+ * Containers
+ *****************************************************************/
+ containers {
+ dprc@1 {
+ parent = "none";
+ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED";
+ objects {
+ /* ------------ DPNIs --------------*/
+ obj_set@dpni {
+ type = "dpni";
+ ids = <0x0>;
+ };
+
+
+ /* ------------ DPMACs --------------*/
+ obj_set@dpmac {
+ type = "dpmac";
+ ids = <0x3 0x4 0x5 0x6 0x11>;
+ };
+
+
+ /* ------------ DPBPs --------------*/
+ obj_set@dpbp {
+ type = "dpbp";
+ ids = <0x0 0x1>;
+ };
+
+ /* ------------ DPIOs --------------*/
+ obj_set@dpio {
+ type = "dpio";
+ ids = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf>;
+ };
+
+ /* ------------ DPMCPs --------------*/
+ obj_set@dpmcp {
+ type = "dpmcp";
+ ids = <0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23>;
+ };
+
+ /* ------------ DPCON --------------*/
+ obj_set@dpcon {
+ type = "dpcon";
+ ids = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f>;
+ };
+
+ /* ------------ DPSECI --------------*/
+ obj@700 {
+ obj_name = "dpseci@0";
+ };
+
+ /* ------------ DPRTC --------------*/
+ obj@800 {
+ obj_name="dprtc@0";
+ };
+ };
+ };
+ };
+
+ /*****************************************************************
+ * Objects
+ *****************************************************************/
+ objects {
+
+ /* ------------ DPNI --------------*/
+ dpni@0 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@1 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@2 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@3 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@4 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@5 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@6 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@7 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@8 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpmac@2 {
+ };
+
+ dpmac@3 {
+ };
+
+ dpmac@4 {
+ };
+
+ dpmac@5 {
+ };
+
+ dpmac@6 {
+ };
+ dpmac@7 {
+ };
+ dpmac@8 {
+ };
+ dpmac@9 {
+ };
+ dpmac@10 {
+ };
+
+ dpmac@17 {
+ };
+
+ dpmac@18 {
+ };
+
+ /* ------------ DPBP --------------*/
+ dpbp@0 {
+ };
+
+ dpbp@1 {
+ };
+
+
+ /* ------------ DPIO --------------*/
+ dpio@0 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@1 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@2 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@3 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@4 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@5 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@6 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@7 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@8 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@9 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@10 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@11 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@12 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@13 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@14 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@15 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ /* ------------ DPMCP --------------*/
+ dpmcp@1 {
+ };
+
+ dpmcp@2 {
+ };
+
+ dpmcp@3 {
+ };
+
+ dpmcp@4 {
+ };
+
+ dpmcp@5 {
+ };
+
+ dpmcp@6 {
+ };
+
+ dpmcp@7 {
+ };
+
+ dpmcp@8 {
+ };
+
+ dpmcp@9 {
+ };
+
+ dpmcp@10 {
+ };
+
+ dpmcp@11 {
+ };
+
+ dpmcp@12 {
+ };
+
+ dpmcp@13 {
+ };
+
+ dpmcp@14 {
+ };
+
+ dpmcp@15 {
+ };
+
+ dpmcp@16 {
+ };
+
+ dpmcp@17 {
+ };
+
+ dpmcp@18 {
+ };
+
+ dpmcp@19 {
+ };
+
+ dpmcp@20 {
+ };
+
+ dpmcp@21 {
+ };
+
+ dpmcp@22 {
+ };
+
+ dpmcp@23 {
+ };
+
+ dpmcp@24 {
+ };
+
+ dpmcp@25 {
+ };
+
+ dpmcp@26 {
+ };
+
+ dpmcp@27 {
+ };
+
+ dpmcp@28 {
+ };
+
+ dpmcp@29 {
+ };
+
+ dpmcp@30 {
+ };
+
+ dpmcp@31 {
+ };
+
+ dpmcp@32 {
+ };
+
+ dpmcp@33 {
+ };
+
+ dpmcp@34 {
+ };
+
+ dpmcp@35 {
+ };
+
+ /* ------------ DPCON --------------*/
+ dpcon@0 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@1 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@2 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@3 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@4 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@5 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@6 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@7 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@8 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@9 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@10 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@11 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@12 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@13 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@14 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@15 {
+ num_priorities = <0x2>;
+ };
+ dpcon@16 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@17 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@18 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@19 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@20 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@21 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@22 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@23 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@24 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@25 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@26 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@27 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@28 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@29 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@30 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@31 {
+ num_priorities = <0x2>;
+ };
+
+ /* ------------ DPSECI --------------*/
+ dpseci@0 {
+ priorities = <0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01>;
+ options = "DPSECI_OPT_HAS_CG";
+ };
+
+ /* ------------ DPRTC --------------*/
+ dprtc@0 {
+ compatible="fsl,dprtc";
+ };
+ };
+
+ /*****************************************************************
+ * Connections
+ *****************************************************************/
+ connections {
+ connection@1 {
+ endpoint1 = "dpni@0";
+ endpoint2 = "dpmac@17";
+ };
+ };
+};
+
--
2.17.1
patches/rcw-LSDK-20.04/0010-lx2160acex7-remove-flexspi-divisor-optimization.patch 0 → 100644
View file @ 423861ac
From 4f1f779e2d0757ab1d328761c06dc09b9c6a3544 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Tue, 1 Sep 2020 12:39:31 +0300
Subject: [PATCH 10/10] lx2160acex7: remove flexspi divisor optimization
Keep the flexspi divisor as default; which is 17MHz when the fabric at
700MHz.
The HoneyComb / ClearFog CX carrier boards holds an SPI flash that it's
MUX is limited to 20MHz.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160acex7/configs/lx2160a_1900_600_2600.rcwi | 3 ---
lx2160acex7/configs/lx2160a_2000_700_2400.rcwi | 3 ---
lx2160acex7/configs/lx2160a_2000_700_2600.rcwi | 3 ---
lx2160acex7/configs/lx2160a_2000_700_2900.rcwi | 3 ---
lx2160acex7/configs/lx2160a_2000_700_3200.rcwi | 3 ---
lx2160acex7/configs/lx2160a_2400_700_3200.rcwi | 3 ---
lx2160acex7/configs/lx2160a_2500_700_3200.rcwi | 3 ---
lx2160acex7/configs/lx2160a_2600_700_3200.rcwi | 3 ---
lx2160acex7/configs/lx2160a_defaults.rcwi | 10 ++++++++--
lx2160acex7/configs/lx2160a_xspiboot.rcwi | 3 ---
10 files changed, 8 insertions(+), 29 deletions(-)
diff --git a/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi b/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi
index 8b61021..a3b7b29 100644
--- a/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi
+++ b/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi
@@ -7,6 +7,3 @@ SYS_PLL_RAT=12
MEM_PLL_RAT=26
MEM2_PLL_RAT=26
-
-/* Modify FlexSPI Clock Divisor value */
-/* #include <../lx2160asi/flexspi_divisor_24.rcw>*/
diff --git a/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi
index 6b0b150..4cb3abf 100644
--- a/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi
+++ b/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi
@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
MEM_PLL_RAT=24
MEM2_PLL_RAT=24
-
-/* Modify FlexSPI Clock Divisor value */
-/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/
diff --git a/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi
index 21dce67..a5c436c 100644
--- a/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi
+++ b/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi
@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
MEM_PLL_RAT=26
MEM2_PLL_RAT=26
-
-/* Modify FlexSPI Clock Divisor value */
-/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/
diff --git a/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi
index e6a8e30..d1db3fb 100644
--- a/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi
+++ b/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi
@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
MEM_PLL_RAT=29
MEM2_PLL_RAT=29
-
-/* Modify FlexSPI Clock Divisor value */
-/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/
diff --git a/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi
index 27ee377..22fcadf 100644
--- a/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi
+++ b/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi
@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
MEM_PLL_RAT=32
MEM2_PLL_RAT=32
-
-/* Modify FlexSPI Clock Divisor value */
-#include <../lx2160asi/flexspi_divisor_28.rcw>
diff --git a/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi
index fc0fd6c..8f74ff0 100644
--- a/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi
+++ b/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi
@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
MEM_PLL_RAT=32
MEM2_PLL_RAT=32
-
-/* Modify FlexSPI Clock Divisor value */
-#include <../lx2160asi/flexspi_divisor_28.rcw>
diff --git a/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi
index 62d9069..2dc1460 100644
--- a/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi
+++ b/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi
@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
MEM_PLL_RAT=32
MEM2_PLL_RAT=32
-
-/* Modify FlexSPI Clock Divisor value */
-#include <../lx2160asi/flexspi_divisor_28.rcw>
diff --git a/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi
index e244917..d9fd795 100644
--- a/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi
+++ b/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi
@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
MEM_PLL_RAT=32
MEM2_PLL_RAT=32
-
-/* Modify FlexSPI Clock Divisor value */
-#include <../lx2160asi/flexspi_divisor_28.rcw>
diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
index 7997d49..359e86c 100644
--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
+++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
@@ -45,5 +45,11 @@ write 0x2320000,0x20000000
/* common PBI commands */
#include <../lx2160asi/common.rcw>
-/* Modify FlexSPI Clock Divisor value - for now keep it fixed value but using loadc/jumpc/jump it can be calculated on the fly */
-#include <../lx2160asi/flexspi_divisor_28.rcw>
+/*
+ * Do not modify the FlexSPI clock divisor value when using HoneyComb / ClearFog CX
+ * as carrier boards. The reason is that the analog mux used on the carrier board
+ * can't accomodate more than 20MHz SPI frequency. So keep the value default 0x14
+ * which indicates divide by 80. In 700MHz fabric clock this is around 17MHz SPI
+ * clock.
+ */
+/*#include <../lx2160asi/flexspi_divisor_28.rcw>*/
diff --git a/lx2160acex7/configs/lx2160a_xspiboot.rcwi b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
index fa092c9..21782ec 100644
--- a/lx2160acex7/configs/lx2160a_xspiboot.rcwi
+++ b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
@@ -6,6 +6,3 @@
/* common PBI commands */
#include <../lx2160asi/common.rcw>
-
-/* Modify FlexSPI Clock Divisor value */
-#include <../lx2160asi/flexspi_divisor_28.rcw>
--
2.17.1
runme.sh
View file @ 423861ac
#!/bin/bash
set -e
# BOOT_LOADER=u-boot,uefi
# DDR_SPEED=2400,2600,2900,3200
# SERDES=8_5_2, 13_5_2, 20_5_2
###############################################################################
# General configurations
###############################################################################
#RELEASE=lx2160a-early-access-bsp0.7 # Supports both rev1 and rev2
#RELEASE=LSDK-19.09 # LSDK-19.09 supports rev1 only
BUILDROOT_VERSION=2020.02.1
#UEFI_RELEASE=DEBUG
#BOOT_LOADER=uefi
#DDR_SPEED=3200
#SERDES=8_5_2 # 8x10g
#SERDES=13_5_2 # dual 100g
......@@ -21,10 +13,10 @@ BUILDROOT_VERSION=2020.02.1
# Misc
###############################################################################
RELEASE=${RELEASE:-LSDK-20.04}
BOOT_LOADER=${BOOT_LOADER:-u-boot}
DDR_SPEED=${DDR_SPEED:-3200}
SERDES=${SERDES:-8_5_2}
UEFI_RELEASE=${UEFI_RELEASE:-RELEASE}
SHALLOW=${SHALLOW:false}
mkdir -p build images
ROOTDIR=`pwd`
......@@ -45,6 +37,10 @@ case "${SERDES}" in
DPC=dpc-dual-100g.dtb
DPL=dpl-eth.dual-100g.19.dtb
;;
17_*)
DPC=dpc-quad-25g.dtb
DPL=dpl-eth.quad-25g.19.dtb
;;
20_*)
DPC=dpc-dual-40g.dtb
DPL=dpl-eth.dual-40g.19.dtb
......@@ -81,8 +77,6 @@ if [[ ! -d $ROOTDIR/build/toolchain ]]; then
cd $ROOTDIR/build/toolchain
wget https://releases.linaro.org/components/toolchain/binaries/7.4-2019.02/aarch64-linux-gnu/gcc-linaro-7.4.1-2019.02-x86_64_aarch64-linux-gnu.tar.xz
tar -xvf gcc-linaro-7.4.1-2019.02-x86_64_aarch64-linux-gnu.tar.xz
wget https://releases.linaro.org/components/toolchain/binaries/4.9-2016.02/aarch64-linux-gnu/gcc-linaro-4.9-2016.02-x86_64_aarch64-linux-gnu.tar.xz
tar -xvf gcc-linaro-4.9-2016.02-x86_64_aarch64-linux-gnu.tar.xz
fi
echo "Building boot loader"
......@@ -96,21 +90,28 @@ for i in $QORIQ_COMPONENTS; do
if [[ ! -d $ROOTDIR/build/$i ]]; then
echo "Cloing https://source.codeaurora.org/external/qoriq/qoriq-components/$i release $RELEASE"
cd $ROOTDIR/build
git clone https://source.codeaurora.org/external/qoriq/qoriq-components/$i
cd $i
if [ "x$i" == "xlinux" ] && [ "x$RELEASE" == "xLSDK-19.06" ]; then
git checkout -b LSDK-19.06-V4.19 refs/tags/LSDK-19.06-V4.19
elif [ "x$i" == "xlinux" ] && [ "x$RELEASE" == "xLSDK-19.09" ]; then
git checkout -b LSDK-19.09-V4.19
elif [ "x$i" == "xlinux" ] && [ "x$RELEASE" == "xLSDK-20.04" ]; then
git checkout -b LSDK-20.04-V5.4 refs/tags/LSDK-20.04-V5.4
elif [ "x$i" == "xdpdk" ] && [ "x$RELEASE" == "xLSDK-20.04" ]; then
git checkout -b LSDK-19.09
elif [ "x$i" == "xrestool" ] && [ "x$RELEASE" == "xLSDK-19.06" ]; then
git checkout -b LSDK-19.09-update-291119
CHECKOUT=$RELEASE
if [ "x$i" == "xu-boot" ] && [ "x$RELEASE" == "xLSDK-20.04" ]; then
CHECKOUT=LSDK-20.04-update-290520
fi
if [ "x$i" == "xlinux" ] && [ "x$RELEASE" == "xLSDK-20.04" ]; then
CHECKOUT=LSDK-20.04-V5.4-update-290520
fi
if [ "x$i" == "xatf" ] && [ "x$RELEASE" == "xLSDK-20.04" ]; then
CHECKOUT=LSDK-20.04-update-290520
fi
if [ "x$i" == "xrcw" ] && [ "x$RELEASE" == "xLSDK-20.04" ]; then
CHECKOUT=LSDK-20.04-update-290520
fi
if [ "x$i" == "xdpdk" ] && [ "x$RELEASE" == "xLSDK-20.04" ]; then
CHECKOUT=LSDK-19.09
fi
if [ "x$SHALLOW" == "xtrue" ]; then
git clone --depth=1 https://source.codeaurora.org/external/qoriq/qoriq-components/$i -b $CHECKOUT
else
git checkout -b $RELEASE refs/tags/$RELEASE
git clone https://source.codeaurora.org/external/qoriq/qoriq-components/$i -b $CHECKOUT
fi
cd $i
if [ "x$i" == "xatf" ]; then
cd $ROOTDIR/build/atf/tools/fiptool
git clone https://github.com/NXP/ddr-phy-binary.git
......@@ -131,6 +132,13 @@ for i in $QORIQ_COMPONENTS; do
if [[ -d $ROOTDIR/patches/$i-$RELEASE/ ]]; then
git am $ROOTDIR/patches/$i-$RELEASE/*.patch
fi
if [[ $RELEASE == *"-update"* ]]; then
# Check extract the LSDK name up to the '-update-...'
SUB_RELEASE=`echo $RELEASE | cut -f-2 -d'-'`
if [[ -d $ROOTDIR/patches/$i-$RELEASE/ ]]; then
git am $ROOTDIR/patches/$i-$RELEASE/*.patch
fi
fi
fi
done
......@@ -440,11 +448,6 @@ dd if=$ROOTDIR/build/mc-utils/config/lx2160a/CEX7/${DPL} of=images/${IMG} bs=512
# DPAA2 DPC at 0x7000
dd if=$ROOTDIR/build/mc-utils/config/lx2160a/CEX7/${DPC} of=images/${IMG} bs=512 seek=28672 conv=notrunc
# Device tree (UEFI) at 0x7800
if [ "x${BOOT_LOADER}" == "xuefi" ]; then
dd if=$ROOTDIR/build/uefi/Build/LX2160aCex7Pkg/${UEFI_RELEASE}_GCC49/AARCH64/Platform/NXP/LX2160aCex7Pkg/DeviceTree/DeviceTree/OUTPUT/fsl-lx2160a-cex7.dtb of=images/${IMG} bs=512 seek=30720 conv=notrunc
dd if=$ROOTDIR/build/uefi/Build/LX2160aCex7Pkg/${UEFI_RELEASE}_GCC49/FV/LX2160ACEX7NV_EFI.fd of=images/${IMG} bs=512 seek=10240 conv=notrunc
fi
# Kernel at 0x8000
dd if=$ROOTDIR/build/linux/kernel-lx2160acex7.itb of=images/${IMG} bs=512 seek=32768 conv=notrunc
......
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