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Commit 6fa3d382 authored by Josua Mayer's avatar Josua Mayer Committed by Rabeeh Khoury
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enable runtime switching of dpmac interface speeds from 1 to 10Gbps 

Signed-off-by: default avatarJosua Mayer <josua@solid-run.com>
parent 93536f42
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configs/linux/lx2k_additions.config
View file @ 6fa3d382
......@@ -43,3 +43,6 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_USER_API_RNG=y
CONFIG_CRYPTO_USER_API_AEAD=y
CONFIG_SFP=y
CONFIG_PHY_FSL_SERDES_28G=y
CONFIG_MARVELL_PHY=y
CONFIG_NAMESPACES=y
patches/linux-LSDK-21.08/0006-net-phy-add-phy_interface_t-bitmap-support.patch 0 → 100644
View file @ 6fa3d382
From 2a75420f57b18b252aa43cd95029baed55a0e7f4 Mon Sep 17 00:00:00 2001
From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
Date: Tue, 26 Oct 2021 11:06:01 +0100
Subject: [PATCH 06/13] net: phy: add phy_interface_t bitmap support
Add support for a bitmap for phy interface modes, which includes:
- a macro to declare the interface bitmap
- an inline helper to zero the interface bitmap
- an inline helper to detect an empty interface bitmap
- inline helpers to do a bitwise AND and OR operations on two interface
bitmaps
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
include/linux/phy.h | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 8559a829a822..cb54401cdfb4 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -148,6 +148,40 @@ typedef enum {
PHY_INTERFACE_MODE_MAX,
} phy_interface_t;
+/* PHY interface mode bitmap handling */
+#define DECLARE_PHY_INTERFACE_MASK(name) \
+ DECLARE_BITMAP(name, PHY_INTERFACE_MODE_MAX)
+
+static inline void phy_interface_zero(unsigned long *intf)
+{
+ bitmap_zero(intf, PHY_INTERFACE_MODE_MAX);
+}
+
+static inline bool phy_interface_empty(const unsigned long *intf)
+{
+ return bitmap_empty(intf, PHY_INTERFACE_MODE_MAX);
+}
+
+static inline void phy_interface_and(unsigned long *dst, const unsigned long *a,
+ const unsigned long *b)
+{
+ bitmap_and(dst, a, b, PHY_INTERFACE_MODE_MAX);
+}
+
+static inline void phy_interface_or(unsigned long *dst, const unsigned long *a,
+ const unsigned long *b)
+{
+ bitmap_or(dst, a, b, PHY_INTERFACE_MODE_MAX);
+}
+
+static inline void phy_interface_set_rgmii(unsigned long *intf)
+{
+ __set_bit(PHY_INTERFACE_MODE_RGMII, intf);
+ __set_bit(PHY_INTERFACE_MODE_RGMII_ID, intf);
+ __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, intf);
+ __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, intf);
+}
+
/*
* phy_supported_speeds - return all speeds currently supported by a PHY device
*/
--
2.34.1
patches/linux-LSDK-21.08/0007-dpaa2-eth-unregister-the-netdev-before-disconnecting.patch 0 → 100644
View file @ 6fa3d382
From 2ffca903d11b80fc624a09f3556a68b4f1cfd173 Mon Sep 17 00:00:00 2001
From: Robert-Ionut Alexa <robert-ionut.alexa@nxp.com>
Date: Thu, 1 Jul 2021 14:49:08 +0300
Subject: [PATCH 07/13] dpaa2-eth: unregister the netdev before disconnecting
from the PHY
The netdev should be unregistered before we are disconnecting from the MAC/PHY
so that the dev_close callback is called and the PHY and the phylink workqueues
are actually stopped before we are disconnecting and destroying the phylink instance.
Fixes: 719479230893 ("dpaa2-eth: add MAC/PHY support through phylink")
Signed-off-by: Robert-Ionut Alexa <robert-ionut.alexa@nxp.com>
---
drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c
index 816256eaeac7..756041df9d08 100644
--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c
+++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c
@@ -4535,9 +4535,8 @@ static int dpaa2_eth_remove(struct fsl_mc_device *ls_dev)
#ifdef CONFIG_DEBUG_FS
dpaa2_dbg_remove(priv);
#endif
- dpaa2_eth_disconnect_mac(priv);
-
unregister_netdev(net_dev);
+ dpaa2_eth_disconnect_mac(priv);
dpaa2_eth_dl_port_del(priv);
dpaa2_eth_dl_traps_unregister(priv);
--
2.34.1
patches/linux-LSDK-21.08/0008-arm64-dts-lx2160a-describe-the-SerDes-block-1.patch 0 → 100644
View file @ 6fa3d382
From b09da32305a0a5e416cf1bbcb370b6bd6ebffbac Mon Sep 17 00:00:00 2001
From: Ioana Ciornei <ioana.ciornei@nxp.com>
Date: Wed, 3 Nov 2021 17:47:31 +0200
Subject: [PATCH 08/13] arm64: dts: lx2160a: describe the SerDes block #1
Describe the SerDes block #1 using the generic phys infrastructure. This
way, the ethernet nodes can each reference their serdes lanes
individually using the 'phys' dts property.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
.../freescale/fsl-lx2160a-clearfog-itx.dtsi | 4 ++
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 41 +++++++++++++++++++
2 files changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
index 17f8e733972a..14a6334adff2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
@@ -63,21 +63,25 @@ sfp3: sfp-3 {
&dpmac7 {
sfp = <&sfp0>;
managed = "in-band-status";
+ phys = <&serdes1_lane_d>;
};
&dpmac8 {
sfp = <&sfp1>;
managed = "in-band-status";
+ phys = <&serdes1_lane_c>;
};
&dpmac9 {
sfp = <&sfp2>;
managed = "in-band-status";
+ phys = <&serdes1_lane_b>;
};
&dpmac10 {
sfp = <&sfp3>;
managed = "in-band-status";
+ phys = <&serdes1_lane_a>;
};
&emdio2 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index cff0699d7992..c493b889c2a8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -613,6 +613,47 @@ soc {
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
+ serdes_1: serdes_phy@1ea0000 {
+ compatible = "fsl,serdes-28g";
+ reg = <0x00 0x1ea0000 0x0 0x1e30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+
+ serdes1_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+ serdes1_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+ serdes1_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+ serdes1_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+ serdes1_lane_e: phy@4 {
+ reg = <4>;
+ #phy-cells = <0>;
+ };
+ serdes1_lane_f: phy@5 {
+ reg = <5>;
+ #phy-cells = <0>;
+ };
+ serdes1_lane_g: phy@6 {
+ reg = <6>;
+ #phy-cells = <0>;
+ };
+ serdes1_lane_h: phy@7 {
+ reg = <7>;
+ #phy-cells = <0>;
+ };
+ };
+
crypto: crypto@8000000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
fsl,sec-era = <10>;
--
2.34.1
patches/linux-LSDK-21.08/0009-phy-add-support-for-the-Layerscape-SerDes-28G.patch 0 → 100644
View file @ 6fa3d382
From 2d18ee5b33795fe6cb1ca6b734b68739100dde9c Mon Sep 17 00:00:00 2001
From: Ioana Ciornei <ioana.ciornei@nxp.com>
Date: Wed, 10 Nov 2021 17:05:52 +0200
Subject: [PATCH 09/13] phy: add support for the Layerscape SerDes 28G
This patch adds minimal support for the SerDes 28G block found on the
LX2160A SoC. At the moment, only SGMII/1000Base-X and 10GBaseR are
supported.
At probe time, the platform driver will read the current
configuration of both PLLs found on a SerDes block and will determine
what protocols are supported using that PLL.
For example, if a PLL is configured to generate a clock net (frate) of
5GHz the only protocols sustained by that PLL are SGMII/1000Base-X
(using a quarter of the full clock rate) and QSGMII using the full clock
net frequency on the lane.
On the .set_mode() callback, the PHY driver will first check if the
requested operating mode (protocol) is even supported by the current PLL
configuration and will error out if not.
Then, the lane is reconfigured to run on the requested protocol.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
drivers/phy/freescale/Kconfig | 8 +
drivers/phy/freescale/Makefile | 1 +
drivers/phy/freescale/phy-fsl-serdes-28g.c | 521 +++++++++++++++++++++
3 files changed, 530 insertions(+)
create mode 100644 drivers/phy/freescale/phy-fsl-serdes-28g.c
diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
index 29b05925e1c5..b46c28672dc2 100644
--- a/drivers/phy/freescale/Kconfig
+++ b/drivers/phy/freescale/Kconfig
@@ -39,3 +39,11 @@ config PHY_FSL_IMX_PCIE
help
Enable this to add support for the PCIE PHY as found on i.MX
family of SOCs.
+
+config PHY_FSL_SERDES_28G
+ tristate "Freescale Layerscape SerDes PHY support"
+ depends on OF
+ select GENERIC_PHY
+ help
+ Enable this to add support for the SerDes 28G PHY as found on NXP's
+ Layerscape platform such as LX2160A.
diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
index 0675f155c47d..380809d3f34c 100644
--- a/drivers/phy/freescale/Makefile
+++ b/drivers/phy/freescale/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
obj-$(CONFIG_PHY_SAMSUNG_HDMI_PHY) += phy-fsl-samsung-hdmi.o
obj-$(CONFIG_PHY_FSL_IMX_PCIE) += phy-fsl-imx8-pcie.o
+obj-$(CONFIG_PHY_FSL_SERDES_28G) += phy-fsl-serdes-28g.o
diff --git a/drivers/phy/freescale/phy-fsl-serdes-28g.c b/drivers/phy/freescale/phy-fsl-serdes-28g.c
new file mode 100644
index 000000000000..841edf6c0477
--- /dev/null
+++ b/drivers/phy/freescale/phy-fsl-serdes-28g.c
@@ -0,0 +1,521 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (c) 2021 NXP. */
+
+#include <linux/module.h>
+#include <linux/phy.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+
+#define SERDES28G_NUM_LANE 8
+#define SERDES28G_NUM_PLL 2
+
+/* General registers per SerDes block */
+#define SERDES28G_PCC8 0x10a0
+#define SERDES28G_PCC8_SGMII 0x1
+#define SERDES28G_PCC8_SGMII_DIS 0x0
+
+#define SERDES28G_PCCC 0x10b0
+#define SERDES28G_PCCC_10GBASER 0x9
+#define SERDES28G_PCCC_USXGMII 0x1
+#define SERDES28G_PCCC_SXGMII_DIS 0x0
+
+/* Per PLL registers */
+#define SERDES28G_PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0)
+#define SERDES28G_PLLnRSTCTL_DIS(rstctl) (((rstctl) & BIT(24)) >> 24)
+#define SERDES28G_PLLnRSTCTL_LOCK(rstctl) (((rstctl) & BIT(23)) >> 23)
+
+#define SERDES28G_PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4)
+#define SERDES28G_PLLnCR0_REFCLK_SEL(cr0) (((cr0) & GENMASK(20,16)))
+#define SERDES28G_PLLnCR0_REFCLK_SEL_100MHZ 0x0
+#define SERDES28G_PLLnCR0_REFCLK_SEL_125MHZ 0x10000
+#define SERDES28G_PLLnCR0_REFCLK_SEL_156MHZ 0x20000
+#define SERDES28G_PLLnCR0_REFCLK_SEL_150MHZ 0x30000
+#define SERDES28G_PLLnCR0_REFCLK_SEL_161MHZ 0x40000
+
+#define SERDES28G_PLLnCR1(pll) (0x400 + (pll) * 0x100 + 0x8)
+#define SERDES28G_PLLnCR1_FRATE_SEL(cr1) (((cr1) & GENMASK(28,24)))
+#define SERDES28G_PLLnCR1_FRATE_5G_10GVCO 0x0
+#define SERDES28G_PLLnCR1_FRATE_5G_25GVCO 0x10000000
+#define SERDES28G_PLLnCR1_FRATE_10G_20GVCO 0x6000000
+
+/* Per SerDes lane registers */
+/* Lane a General Control Register */
+#define SERDES28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0)
+#define SERDES28G_LNaGCR0_PROTO_SEL_MSK GENMASK(7,3)
+#define SERDES28G_LNaGCR0_PROTO_SEL_SGMII 0x8
+#define SERDES28G_LNaGCR0_PROTO_SEL_XFI 0x50
+#define SERDES28G_LNaGCR0_IF_WIDTH_MSK GENMASK(2,0)
+#define SERDES28G_LNaGCR0_IF_WIDTH_10_BIT 0x0
+#define SERDES28G_LNaGCR0_IF_WIDTH_20_BIT 0x2
+
+/* Lane a Tx Reset Control Register */
+#define SERDES28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20)
+#define SERDES28G_LNaTRSTCTL_HLT_REQ BIT(27)
+#define SERDES28G_LNaTRSTCTL_RST_DONE BIT(30)
+#define SERDES28G_LNaTRSTCTL_RST_REQ BIT(31)
+
+/* Lane a Tx General Control Register */
+#define SERDES28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24)
+#define SERDES28G_LNaTGCR0_USE_PLLF 0x0
+#define SERDES28G_LNaTGCR0_USE_PLLS BIT(28)
+#define SERDES28G_LNaTGCR0_USE_PLL_MSK BIT(28)
+#define SERDES28G_LNaTGCR0_N_RATE_FULL 0x0
+#define SERDES28G_LNaTGCR0_N_RATE_HALF 0x1000000
+#define SERDES28G_LNaTGCR0_N_RATE_QUARTER 0x2000000
+#define SERDES28G_LNaTGCR0_N_RATE_MSK GENMASK(26,24)
+
+/* Lane a Rx Reset Control Register */
+#define SERDES28G_LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40)
+#define SERDES28G_LNaRRSTCTL_HLT_REQ BIT(27)
+#define SERDES28G_LNaRRSTCTL_RST_DONE BIT(30)
+#define SERDES28G_LNaRRSTCTL_RST_REQ BIT(31)
+
+/* Lane a Rx General Control Register */
+#define SERDES28G_LNaRGCR0(lane) (0x800 + (lane) * 0x100 + 0x44)
+#define SERDES28G_LNaRGCR0_USE_PLLF 0x0
+#define SERDES28G_LNaRGCR0_USE_PLLS BIT(28)
+#define SERDES28G_LNaRGCR0_USE_PLL_MSK BIT(28)
+#define SERDES28G_LNaRGCR0_N_RATE_MSK GENMASK(26,24)
+#define SERDES28G_LNaRGCR0_N_RATE_FULL 0x0
+#define SERDES28G_LNaRGCR0_N_RATE_HALF 0x1000000
+#define SERDES28G_LNaRGCR0_N_RATE_QUARTER 0x2000000
+#define SERDES28G_LNaRGCR0_N_RATE_MSK GENMASK(26,24)
+
+#define SERDES28G_SGMIIaCR1(lane) (0x1804 + (lane) * 0x10)
+#define SERDES28G_SGMIIaCR1_SGPCS_EN BIT(11)
+#define SERDES28G_SGMIIaCR1_SGPCS_DIS 0x0
+#define SERDES28G_SGMIIaCR1_SGPCS_MSK BIT(11)
+
+struct serdes28g_pll {
+ struct serdes28g_priv *priv;
+ u32 rstctl, cr0, cr1;
+ int id;
+ DECLARE_PHY_INTERFACE_MASK(supported);
+};
+
+struct serdes28g_priv {
+ void __iomem *base;
+ struct device *dev;
+ struct serdes28g_pll pll[SERDES28G_NUM_PLL];
+};
+
+struct serdes28g_lane {
+ struct serdes28g_priv *priv;
+ bool powered_up;
+ unsigned id;
+};
+
+static void serdes28g_rmw(struct serdes28g_priv *priv, unsigned long off,
+ u32 val, u32 mask)
+{
+ void __iomem *reg = priv->base + off;
+ u32 orig, tmp;
+
+ orig = ioread32(reg);
+ tmp = orig & ~mask;
+ tmp |= val;
+ iowrite32(tmp, reg);
+}
+
+#define serdes28g_lane_rmw(lane, reg, val, mask) \
+ serdes28g_rmw((lane)->priv, SERDES28G_##reg(lane->id), SERDES28G_##reg##_##val, SERDES28G_##reg##_##mask)
+
+#define serdes28g_lane_read(lane, reg) \
+ ioread32((lane)->priv->base + SERDES28G_##reg((lane)->id))
+#define serdes28g_pll_read(pll, reg) \
+ ioread32((pll)->priv->base + SERDES28G_##reg((pll)->id))
+
+static bool serdes28g_supports_interface(struct serdes28g_priv *priv, int intf)
+{
+ int i;
+
+ for (i = 0; i < SERDES28G_NUM_PLL; i++)
+ if (test_bit(intf, priv->pll[i].supported))
+ return true;
+
+ return false;
+}
+
+static struct serdes28g_pll *serdes28g_pll_get(struct serdes28g_priv *priv,
+ phy_interface_t intf)
+{
+ struct serdes28g_pll *pll;
+ int i;
+
+ for (i = 0; i < SERDES28G_NUM_PLL; i++) {
+ pll = &priv->pll[i];
+ if (test_bit(intf, pll->supported))
+ return pll;
+ }
+
+ return NULL;
+}
+
+static void serdes28g_lane_set_nrate(struct serdes28g_lane *lane,
+ struct serdes28g_pll *pll,
+ phy_interface_t intf)
+{
+ switch (SERDES28G_PLLnCR1_FRATE_SEL(pll->cr1)) {
+ case SERDES28G_PLLnCR1_FRATE_5G_10GVCO:
+ case SERDES28G_PLLnCR1_FRATE_5G_25GVCO:
+ switch (intf) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ serdes28g_lane_rmw(lane, LNaTGCR0, N_RATE_QUARTER, N_RATE_MSK);
+ serdes28g_lane_rmw(lane, LNaRGCR0, N_RATE_QUARTER, N_RATE_MSK);
+ break;
+ default:
+ break;
+ }
+ break;
+ case SERDES28G_PLLnCR1_FRATE_10G_20GVCO:
+ switch (intf) {
+ case PHY_INTERFACE_MODE_10GBASER:
+ case PHY_INTERFACE_MODE_USXGMII:
+ serdes28g_lane_rmw(lane, LNaTGCR0, N_RATE_FULL, N_RATE_MSK);
+ serdes28g_lane_rmw(lane, LNaRGCR0, N_RATE_FULL, N_RATE_MSK);
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+static void serdes28g_lane_set_pll(struct serdes28g_lane *lane,
+ struct serdes28g_pll *pll)
+{
+ if (pll->id == 0) {
+ serdes28g_lane_rmw(lane, LNaTGCR0, USE_PLLF, USE_PLL_MSK);
+ serdes28g_lane_rmw(lane, LNaRGCR0, USE_PLLF, USE_PLL_MSK);
+ } else {
+ serdes28g_lane_rmw(lane, LNaTGCR0, USE_PLLS, USE_PLL_MSK);
+ serdes28g_lane_rmw(lane, LNaRGCR0, USE_PLLS, USE_PLL_MSK);
+ }
+}
+
+static int serdes28g_lane_set_sgmii(struct serdes28g_lane *lane)
+{
+ struct serdes28g_priv *priv = lane->priv;
+ struct serdes28g_pll *pll;
+ u32 lane_mask, lane_offset;
+
+ lane_offset = (4 * (SERDES28G_NUM_LANE - lane->id - 1));
+ lane_mask = GENMASK(3,0) << lane_offset;
+
+ /* Disable the SXGMII lane */
+ serdes28g_rmw(priv, SERDES28G_PCCC,
+ SERDES28G_PCCC_SXGMII_DIS << lane_offset, lane_mask);
+
+ /* This lane runs in SGMII mode */
+ serdes28g_rmw(priv, SERDES28G_PCC8,
+ SERDES28G_PCC8_SGMII << lane_offset, lane_mask);
+
+ /* Setup the protocol select and SerDes parallel interface width */
+ serdes28g_lane_rmw(lane, LNaGCR0, PROTO_SEL_SGMII, PROTO_SEL_MSK);
+ serdes28g_lane_rmw(lane, LNaGCR0, IF_WIDTH_10_BIT, IF_WIDTH_MSK);
+
+ /* Switch to the PLL that works with this interface type */
+ pll = serdes28g_pll_get(priv, PHY_INTERFACE_MODE_SGMII);
+ serdes28g_lane_set_pll(lane, pll);
+
+ /* Choose the portion of clock net to be used on this lane */
+ serdes28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_SGMII);
+
+ /* Enable the SGMII PCS */
+ serdes28g_lane_rmw(lane, SGMIIaCR1, SGPCS_EN, SGPCS_MSK);
+
+ return 0;
+}
+
+static int serdes28g_lane_set_10gbaser(struct serdes28g_lane *lane)
+{
+ struct serdes28g_priv *priv = lane->priv;
+ u32 lane_mask, lane_offset;
+ struct serdes28g_pll *pll;
+
+ lane_offset = (4 * (SERDES28G_NUM_LANE - lane->id - 1));
+ lane_mask = GENMASK(3,0) << lane_offset;
+
+ /* Stop the lane from running in SGMII/1000Base-x/1000Base-KX mode */
+ serdes28g_rmw(priv, SERDES28G_PCC8,
+ SERDES28G_PCC8_SGMII_DIS << lane_offset, lane_mask);
+
+ /* Enable the SXGMII lane */
+ serdes28g_rmw(priv, SERDES28G_PCCC,
+ SERDES28G_PCCC_10GBASER << lane_offset, lane_mask);
+
+ /* Setup the protocol select and SerDes parallel interface width */
+ serdes28g_lane_rmw(lane, LNaGCR0, PROTO_SEL_XFI, PROTO_SEL_MSK);
+ serdes28g_lane_rmw(lane, LNaGCR0, IF_WIDTH_20_BIT, IF_WIDTH_MSK);
+
+ /* Switch to the PLL that works with this interface type */
+ pll = serdes28g_pll_get(priv, PHY_INTERFACE_MODE_10GBASER);
+ serdes28g_lane_set_pll(lane, pll);
+
+ /* Choose the portion of clock net to be used on this lane */
+ serdes28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_10GBASER);
+
+ /* Disable the SGMII PCS */
+ serdes28g_lane_rmw(lane, SGMIIaCR1, SGPCS_DIS, SGPCS_MSK);
+
+ return 0;
+}
+
+static int serdes28g_set_mode(struct phy *phy, enum phy_mode mode, int submode)
+{
+ struct serdes28g_lane *lane = phy_get_drvdata(phy);
+ struct serdes28g_priv *priv = lane->priv;
+ int err;
+
+ if (mode != PHY_MODE_ETHERNET)
+ return -EOPNOTSUPP;
+
+ if (!serdes28g_supports_interface(priv, submode))
+ return -EOPNOTSUPP;
+
+ switch (submode) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ err = serdes28g_lane_set_sgmii(lane);
+ break;
+ case PHY_INTERFACE_MODE_10GBASER:
+ err = serdes28g_lane_set_10gbaser(lane);
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+
+ return err;
+}
+
+static int serdes28g_power_off(struct phy *phy)
+{
+ struct serdes28g_lane *lane = phy_get_drvdata(phy);
+ u32 trstctl, rrstctl;
+
+ if (!lane->powered_up)
+ return 0;
+
+ /* Issue a halt request */
+ serdes28g_lane_rmw(lane, LNaTRSTCTL, HLT_REQ, HLT_REQ);
+ serdes28g_lane_rmw(lane, LNaRRSTCTL, HLT_REQ, HLT_REQ);
+
+ /* Wait until the halting process is complete */
+ do {
+ trstctl = serdes28g_lane_read(lane, LNaTRSTCTL);
+ rrstctl = serdes28g_lane_read(lane, LNaRRSTCTL);
+ } while ((trstctl & SERDES28G_LNaTRSTCTL_HLT_REQ) ||
+ (rrstctl & SERDES28G_LNaRRSTCTL_HLT_REQ));
+
+ lane->powered_up = false;
+
+ return 0;
+}
+
+static int serdes28g_power_on(struct phy *phy)
+{
+ struct serdes28g_lane *lane = phy_get_drvdata(phy);
+ u32 trstctl, rrstctl;
+
+ if (lane->powered_up)
+ return 0;
+
+ /* Issue a reset request on the lane */
+ serdes28g_lane_rmw(lane, LNaTRSTCTL, RST_REQ, RST_REQ);
+ serdes28g_lane_rmw(lane, LNaRRSTCTL, RST_REQ, RST_REQ);
+
+ /* Wait until the reset sequence is completed */
+ do {
+ trstctl = serdes28g_lane_read(lane, LNaTRSTCTL);
+ rrstctl = serdes28g_lane_read(lane, LNaRRSTCTL);
+ } while (!(trstctl & SERDES28G_LNaTRSTCTL_RST_DONE) ||
+ !(rrstctl & SERDES28G_LNaRRSTCTL_RST_DONE));
+
+ lane->powered_up = true;
+
+ return 0;
+}
+
+static const struct phy_ops serdes28g_ops = {
+ .power_on = serdes28g_power_on,
+ .power_off = serdes28g_power_off,
+ .set_mode = serdes28g_set_mode,
+ .owner = THIS_MODULE,
+};
+
+static void serdes26_pll_dump(struct serdes28g_pll *pll)
+{
+ struct serdes28g_priv *priv = pll->priv;
+ bool dis, lock;
+ u32 refclk, frate;
+ int intf;
+
+ dis = SERDES28G_PLLnRSTCTL_DIS(pll->rstctl) != 0 ? true : false;
+ lock = SERDES28G_PLLnRSTCTL_LOCK(pll->rstctl) != 0 ? true : false;
+ refclk = SERDES28G_PLLnCR0_REFCLK_SEL(pll->cr0);
+ frate = (SERDES28G_PLLnCR1_FRATE_SEL(pll->cr1));
+
+ dev_err(priv->dev, "PLL%c: %sabled, %slocked\n",
+ pll->id == 0 ? 'F' : 'S',
+ dis ? "dis" : "en",
+ lock ? "" : "un");
+
+ switch (refclk) {
+ case SERDES28G_PLLnCR0_REFCLK_SEL_100MHZ:
+ dev_err(priv->dev, "\tReference clock: 100MHz\n");
+ break;
+ case SERDES28G_PLLnCR0_REFCLK_SEL_125MHZ:
+ dev_err(priv->dev, "\tReference clock: 125MHz\n");
+ break;
+ case SERDES28G_PLLnCR0_REFCLK_SEL_156MHZ:
+ dev_err(priv->dev, "\tReference clock: 156.25MHz\n");
+ break;
+ case SERDES28G_PLLnCR0_REFCLK_SEL_150MHZ:
+ dev_err(priv->dev, "\tReference clock: 150MHz\n");
+ break;
+ case SERDES28G_PLLnCR0_REFCLK_SEL_161MHZ:
+ dev_err(priv->dev, "\tReference clock: 161.1328125MHz\n");
+ break;
+ default:
+ break;
+ }
+
+ switch (frate) {
+ case SERDES28G_PLLnCR1_FRATE_5G_10GVCO:
+ case SERDES28G_PLLnCR1_FRATE_5G_25GVCO:
+ dev_err(priv->dev, "\tclock net: 5GHz\n");
+ break;
+ case SERDES28G_PLLnCR1_FRATE_10G_20GVCO:
+ dev_err(priv->dev, "\tclock net: 10.3125GHz\n");
+ break;
+ default:
+ /* 6GHz, 12.890625GHz, 8GHz */
+ break;
+ }
+
+ dev_err(priv->dev, "\tSupported interfaces:\n");
+ for (intf = 0; intf < PHY_INTERFACE_MODE_MAX; intf++) {
+ if (test_bit(intf, pll->supported))
+ dev_err(priv->dev, "\t\t%s\n", phy_modes(intf));
+ }
+}
+
+static void serdes28g_pll_read_configuration(struct serdes28g_priv *priv)
+{
+ struct serdes28g_pll *pll;
+ int i;
+
+ for (i = 0; i < SERDES28G_NUM_PLL; i++) {
+ pll = &priv->pll[i];
+ pll->priv = priv;
+ pll->id = i;
+
+ pll->rstctl = serdes28g_pll_read(pll, PLLnRSTCTL);
+ pll->cr0 = serdes28g_pll_read(pll, PLLnCR0);
+ pll->cr1 = serdes28g_pll_read(pll, PLLnCR1);
+
+ switch (SERDES28G_PLLnCR1_FRATE_SEL(pll->cr1)) {
+ case SERDES28G_PLLnCR1_FRATE_5G_10GVCO:
+ case SERDES28G_PLLnCR1_FRATE_5G_25GVCO:
+ /* 5GHz clock net */
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX, pll->supported);
+ __set_bit(PHY_INTERFACE_MODE_SGMII, pll->supported);
+ __set_bit(PHY_INTERFACE_MODE_QSGMII, pll->supported);
+ break;
+ case SERDES28G_PLLnCR1_FRATE_10G_20GVCO:
+ /* 10.3125GHz clock net */
+ __set_bit(PHY_INTERFACE_MODE_10GBASER, pll->supported);
+ __set_bit(PHY_INTERFACE_MODE_USXGMII, pll->supported);
+ break;
+ default:
+ /* 6GHz, 12.890625GHz, 8GHz */
+ break;
+ }
+
+ serdes26_pll_dump(pll);
+ }
+}
+
+static int serdes28g_probe(struct platform_device *pdev)
+{
+ struct phy_provider *provider;
+ struct serdes28g_priv *priv;
+ struct device_node *child;
+ int err;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+ priv->dev = &pdev->dev;
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ serdes28g_pll_read_configuration(priv);
+
+ for_each_available_child_of_node(pdev->dev.of_node, child) {
+ struct serdes28g_lane *lane;
+ struct phy *phy;
+ u32 val;
+
+ err = of_property_read_u32(child, "reg", &val);
+ if (err < 0) {
+ dev_err(&pdev->dev, "missing 'reg' property (%d)\n", err);
+ continue;
+ }
+
+ if (val >= SERDES28G_NUM_LANE) {
+ dev_err(&pdev->dev, "invalid 'reg' property\n");
+ continue;
+ }
+
+ lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);
+ if (!lane) {
+ of_node_put(child);
+ return -ENOMEM;
+ }
+
+ phy = devm_phy_create(&pdev->dev, child, &serdes28g_ops);
+ if (IS_ERR(phy)) {
+ of_node_put(child);
+ return PTR_ERR(phy);
+ }
+
+ lane->priv = priv;
+ lane->id = val;
+ lane->powered_up = true;
+ phy_set_drvdata(phy, lane);
+
+ phy_power_on(phy);
+
+ dev_err(priv->dev, "created PHY for lane #%d\n", lane->id);
+ }
+
+ dev_set_drvdata(&pdev->dev, priv);
+ provider = devm_of_phy_provider_register(&pdev->dev,
+ of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(provider);
+}
+
+static const struct of_device_id serdes28g_of_match_table[] = {
+ { .compatible = "fsl,serdes-28g" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, serdes28g_of_match_table);
+
+static struct platform_driver serdes28g_driver = {
+ .probe = serdes28g_probe,
+ .driver = {
+ .name = "serdes-28g",
+ .of_match_table = serdes28g_of_match_table,
+ },
+};
+module_platform_driver(serdes28g_driver);
+
+MODULE_AUTHOR("Ioana Ciornei <ioana.ciornei@nxp.com>");
+MODULE_DESCRIPTION("SerDes 28G PHY driver for Layerscape SoCs");
--
2.34.1
patches/linux-LSDK-21.08/0010-dpaa2-eth-configure-the-SerDes-phy-on-a-protocol-cha.patch 0 → 100644
View file @ 6fa3d382
From 08d2275cb55bf41e48d6ee10309229965594f37f Mon Sep 17 00:00:00 2001
From: Ioana Ciornei <ioana.ciornei@nxp.com>
Date: Wed, 10 Nov 2021 17:06:45 +0200
Subject: [PATCH 10/13] dpaa2-eth: configure the SerDes phy on a protocol
change
This patch integrates the dpaa2-eth driver with the generic PHY
infrastructure in order to search, find and reconfigure the SerDes lanes
in case of a protocol change.
The phylink's .mac_prepare() and .mac_finish() callbacks are implemented
just so that the SerDes lane can be stopped and then powered back on in
case reconfiguration is necessary.
On the .mac_config() callback, the phy_set_mode_ext() API is called so
that the SerDes28G PHY driver can change the lane's configuration.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
.../net/ethernet/freescale/dpaa2/dpaa2-mac.c | 74 ++++++++++---------
.../net/ethernet/freescale/dpaa2/dpaa2-mac.h | 2 +
2 files changed, 42 insertions(+), 34 deletions(-)
diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
index a5c76ff33bed..b174b59ea45b 100644
--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
+++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
@@ -4,6 +4,7 @@
#include <linux/fsl/mc.h>
#include <linux/msi.h>
#include <linux/acpi.h>
+#include <linux/phy/phy.h>
#include <linux/property.h>
#include "dpaa2-eth.h"
@@ -106,46 +107,12 @@ static int dpaa2_mac_get_if_mode(struct fwnode_handle *dpmac_node,
return err;
}
-static bool dpaa2_mac_phy_mode_mismatch(struct dpaa2_mac *mac,
- phy_interface_t interface)
-{
- switch (interface) {
- /* We can switch between SGMII and 1000BASE-X at runtime with
- * pcs-lynx
- */
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_1000BASEX:
- if (mac->pcs &&
- (mac->if_mode == PHY_INTERFACE_MODE_SGMII ||
- mac->if_mode == PHY_INTERFACE_MODE_1000BASEX))
- return false;
- return interface != mac->if_mode;
-
- case PHY_INTERFACE_MODE_10GBASER:
- case PHY_INTERFACE_MODE_USXGMII:
- case PHY_INTERFACE_MODE_QSGMII:
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_ID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_TXID:
- return (interface != mac->if_mode);
- default:
- return true;
- }
-}
-
static void dpaa2_mac_validate(struct phylink_config *config,
unsigned long *supported,
struct phylink_link_state *state)
{
- struct dpaa2_mac *mac = phylink_to_dpaa2_mac(config);
__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
- if (state->interface != PHY_INTERFACE_MODE_NA &&
- dpaa2_mac_phy_mode_mismatch(mac, state->interface)) {
- goto empty_set;
- }
-
phylink_set_port_modes(mask);
phylink_set(mask, Autoneg);
phylink_set(mask, Pause);
@@ -210,6 +177,10 @@ static void dpaa2_mac_config(struct phylink_config *config, unsigned int mode,
if (err)
netdev_err(mac->net_dev, "%s: dpmac_set_link_state() = %d\n",
__func__, err);
+
+ err = phy_set_mode_ext(mac->serdes_phy, PHY_MODE_ETHERNET, state->interface);
+ if (err)
+ netdev_err(mac->net_dev, "phy_set_mode_ext() = %d\n", err);
}
static void dpaa2_mac_link_up(struct phylink_config *config,
@@ -263,11 +234,37 @@ static void dpaa2_mac_link_down(struct phylink_config *config,
netdev_err(mac->net_dev, "dpmac_set_link_state() = %d\n", err);
}
+static int dpaa2_mac_prepare(struct phylink_config *config, unsigned int mode,
+ phy_interface_t interface)
+{
+ struct dpaa2_mac *mac = phylink_to_dpaa2_mac(config);
+
+ dpaa2_mac_link_down(config, mode, interface);
+
+ if (mac->serdes_phy)
+ phy_power_off(mac->serdes_phy);
+
+ return 0;
+}
+
+static int dpaa2_mac_finish(struct phylink_config *config, unsigned int mode,
+ phy_interface_t interface)
+{
+ struct dpaa2_mac *mac = phylink_to_dpaa2_mac(config);
+
+ if (mac->serdes_phy)
+ phy_power_on(mac->serdes_phy);
+
+ return 0;
+}
+
static const struct phylink_mac_ops dpaa2_mac_phylink_ops = {
.validate = dpaa2_mac_validate,
.mac_config = dpaa2_mac_config,
.mac_link_up = dpaa2_mac_link_up,
.mac_link_down = dpaa2_mac_link_down,
+ .mac_prepare = dpaa2_mac_prepare,
+ .mac_finish = dpaa2_mac_finish,
};
static int dpaa2_pcs_create(struct dpaa2_mac *mac,
@@ -321,6 +318,7 @@ int dpaa2_mac_connect(struct dpaa2_mac *mac)
{
struct net_device *net_dev = mac->net_dev;
struct fwnode_handle *dpmac_node;
+ struct phy *serdes_phy = NULL;
struct phylink *phylink;
int err;
@@ -337,6 +335,14 @@ int dpaa2_mac_connect(struct dpaa2_mac *mac)
return -EINVAL;
mac->if_mode = err;
+ if (!phy_interface_mode_is_rgmii(mac->if_mode) &&
+ is_of_node(dpmac_node)) {
+ serdes_phy = of_phy_get(to_of_node(dpmac_node), NULL);
+ if (IS_ERR(serdes_phy))
+ return -EPROBE_DEFER;
+ }
+ mac->serdes_phy = serdes_phy;
+
/* The MAC does not have the capability to add RGMII delays so
* error out if the interface mode requests them and there is no PHY
* to act upon them
diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h
index b337f9da639b..a0fdb43185ea 100644
--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h
+++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h
@@ -26,6 +26,8 @@ struct dpaa2_mac {
enum dpmac_link_type if_link_type;
struct lynx_pcs *pcs;
struct fwnode_handle *fw_node;
+
+ struct phy *serdes_phy;
};
bool dpaa2_mac_is_type_fixed(struct fsl_mc_device *dpmac_dev,
--
2.34.1
patches/linux-LSDK-21.08/0011-dpaa2-eth-configure-the-MAC-XIF_MODE-register-on-pro.patch 0 → 100644
View file @ 6fa3d382
From 706968646b36732de79aae3354a858bf387edf57 Mon Sep 17 00:00:00 2001
From: Ioana Ciornei <ioana.ciornei@nxp.com>
Date: Wed, 10 Nov 2021 17:09:06 +0200
Subject: [PATCH 11/13] dpaa2-eth: configure the MAC XIF_MODE register on
protocol change
This patch ioremaps the MEMAC XIF_MODE register in order to change the
protocol (IFMODE field) from XLGMII (10G/25G mode) to GMII mode in case
of a major reconfiguration.
This is just a hack in the dpaa2-eth driver until we have support in the
MC firmware.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
.../net/ethernet/freescale/dpaa2/dpaa2-mac.c | 26 +++++++++++++++++++
.../net/ethernet/freescale/dpaa2/dpaa2-mac.h | 1 +
2 files changed, 27 insertions(+)
diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
index b174b59ea45b..6a5f754c8c61 100644
--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
+++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
@@ -165,6 +165,7 @@ static void dpaa2_mac_config(struct phylink_config *config, unsigned int mode,
{
struct dpaa2_mac *mac = phylink_to_dpaa2_mac(config);
struct dpmac_link_state *dpmac_state = &mac->state;
+ u32 if_mode, orig, tmp;
int err;
if (state->an_enabled)
@@ -178,6 +179,24 @@ static void dpaa2_mac_config(struct phylink_config *config, unsigned int mode,
netdev_err(mac->net_dev, "%s: dpmac_set_link_state() = %d\n",
__func__, err);
+ switch (state->interface) {
+ case PHY_INTERFACE_MODE_10GBASER:
+ case PHY_INTERFACE_MODE_USXGMII:
+ if_mode = 0x1;
+ break;
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ if_mode = 0x3;
+ break;
+ default:
+ break;
+ }
+
+ orig = ioread32(mac->if_mode_reg);
+ tmp = orig & ~0x3;
+ tmp |= if_mode;
+ iowrite32(tmp, mac->if_mode_reg);
+
err = phy_set_mode_ext(mac->serdes_phy, PHY_MODE_ETHERNET, state->interface);
if (err)
netdev_err(mac->net_dev, "phy_set_mode_ext() = %d\n", err);
@@ -412,6 +431,7 @@ int dpaa2_mac_open(struct dpaa2_mac *mac)
{
struct fsl_mc_device *dpmac_dev = mac->mc_dev;
struct net_device *net_dev = mac->net_dev;
+ unsigned long if_mode_addr;
int err;
err = dpmac_open(mac->mc_io, 0, dpmac_dev->obj_desc.id,
@@ -434,6 +454,12 @@ int dpaa2_mac_open(struct dpaa2_mac *mac)
mac->fw_node = dpaa2_mac_get_node(&mac->mc_dev->dev, mac->attr.id);
net_dev->dev.of_node = to_of_node(mac->fw_node);
+ if_mode_addr = 0x8c07080 + 0x4000 * (dpmac_dev->obj_desc.id - 1);
+ mac->if_mode_reg = ioremap(if_mode_addr, 4);
+ if (!mac->if_mode_reg) {
+ netdev_err(net_dev, "ioremap on if_mode failed\n");
+ }
+
return 0;
err_close_dpmac:
diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h
index a0fdb43185ea..5f1a500b503a 100644
--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h
+++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h
@@ -28,6 +28,7 @@ struct dpaa2_mac {
struct fwnode_handle *fw_node;
struct phy *serdes_phy;
+ void __iomem *if_mode_reg;
};
bool dpaa2_mac_is_type_fixed(struct fsl_mc_device *dpmac_dev,
--
2.34.1
patches/mc-utils/0006-lx2160acex7-upgrade-network-ports-from-fixed-link-to.patch 0 → 100644
View file @ 6fa3d382
From ae5d80dc0f1b92dface59c9e14f4627ca8e03cfc Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Thu, 31 Mar 2022 10:57:54 +0300
Subject: [PATCH 6/6] lx2160acex7: upgrade network ports from fixed link to phy
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
config/lx2160a/CEX7/dpc-8_x_usxgmii.dts | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/config/lx2160a/CEX7/dpc-8_x_usxgmii.dts b/config/lx2160a/CEX7/dpc-8_x_usxgmii.dts
index 44e22bb..7b0e576 100644
--- a/config/lx2160a/CEX7/dpc-8_x_usxgmii.dts
+++ b/config/lx2160a/CEX7/dpc-8_x_usxgmii.dts
@@ -72,28 +72,28 @@
board_info {
ports {
mac@3 {
- link_type = "MAC_LINK_TYPE_FIXED";
+ link_type = "MAC_LINK_TYPE_PHY";
};
mac@4 {
- link_type = "MAC_LINK_TYPE_FIXED";
+ link_type = "MAC_LINK_TYPE_PHY";
};
mac@5 {
- link_type = "MAC_LINK_TYPE_FIXED";
+ link_type = "MAC_LINK_TYPE_PHY";
};
mac@6 {
- link_type = "MAC_LINK_TYPE_FIXED";
+ link_type = "MAC_LINK_TYPE_PHY";
};
mac@7 {
- link_type = "MAC_LINK_TYPE_FIXED";
+ link_type = "MAC_LINK_TYPE_PHY";
};
mac@8 {
- link_type = "MAC_LINK_TYPE_FIXED";
+ link_type = "MAC_LINK_TYPE_PHY";
};
mac@9 {
- link_type = "MAC_LINK_TYPE_FIXED";
+ link_type = "MAC_LINK_TYPE_PHY";
};
mac@10 {
- link_type = "MAC_LINK_TYPE_FIXED";
+ link_type = "MAC_LINK_TYPE_PHY";
};
mac@17 {
link_type = "MAC_LINK_TYPE_PHY";
--
2.34.1
patches/rcw-LSDK-21.08/0017-lx2160acex7-mode-8-use-external-PLLs.patch 0 → 100644
View file @ 6fa3d382
From 89be982a78fd1767a7c9f36147df91969293387d Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Sun, 27 Mar 2022 13:37:03 +0300
Subject: [PATCH 17/18] lx2160acex7: mode 8: use external PLLs
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
lx2160acex7/configs/lx2160a_SD1_8.rcwi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lx2160acex7/configs/lx2160a_SD1_8.rcwi b/lx2160acex7/configs/lx2160a_SD1_8.rcwi
index abd6dfd..0dab1c4 100644
--- a/lx2160acex7/configs/lx2160a_SD1_8.rcwi
+++ b/lx2160acex7/configs/lx2160a_SD1_8.rcwi
@@ -1,4 +1,4 @@
SRDS_PRTCL_S1=8 /* should be 8 */
-SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */
+/*SRDS_INTRA_REF_CLK_S1 = 1*/ /* PLLF used for PLLS */
SRDS_PLL_REF_CLK_SEL_S1=2
-SRDS_PLL_PD_PLL1=1
+/*SRDS_PLL_PD_PLL1=1*/
--
2.34.1
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