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Commit 92bef239 authored by Josua Mayer's avatar Josua Mayer
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u-boot: add dedicated device-tree for lx2162-clearfog 

Implicitly fixes mac address assignment all interfaces.
parent 143b0ba3
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Showing with 482 additions and 6 deletions
patches/linux-LSDK-21.08/0061-net-dpaa2-add-support-for-retimer-phys.patch
View file @ 92bef239
From 4f57e6a9e4b8a9b1e440459ce574a1f4921e1473 Mon Sep 17 00:00:00 2001 From 2c6770fb3ff78aecb8b4ed04ff3a8e54bf0f3531 Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com> From: Josua Mayer <josua@solid-run.com>
Date: Sun, 16 Apr 2023 14:32:28 +0300 Date: Sun, 16 Apr 2023 14:32:28 +0300
Subject: [PATCH] net: dpaa2: add support for retimer phys Subject: [PATCH] net: dpaa2: add support for retimer phys
...@@ -19,12 +19,12 @@ one serdes and 2 retimer phys. ...@@ -19,12 +19,12 @@ one serdes and 2 retimer phys.
Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Josua Mayer <josua@solid-run.com>
--- ---
.../net/ethernet/freescale/dpaa2/dpaa2-mac.c | 63 +++++++++++++++---- .../net/ethernet/freescale/dpaa2/dpaa2-mac.c | 62 +++++++++++++++----
.../net/ethernet/freescale/dpaa2/dpaa2-mac.h | 1 + .../net/ethernet/freescale/dpaa2/dpaa2-mac.h | 1 +
2 files changed, 51 insertions(+), 13 deletions(-) 2 files changed, 50 insertions(+), 13 deletions(-)
diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
index 2302e9c11186..a4aad5431e82 100644 index 2302e9c11186..aadceeb0ca12 100644
--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c --- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
+++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c +++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
@@ -266,6 +266,7 @@ static void dpaa2_mac_config(struct phylink_config *config, unsigned int mode, @@ -266,6 +266,7 @@ static void dpaa2_mac_config(struct phylink_config *config, unsigned int mode,
...@@ -66,7 +66,7 @@ index 2302e9c11186..a4aad5431e82 100644 ...@@ -66,7 +66,7 @@ index 2302e9c11186..a4aad5431e82 100644
mac->if_link_type = mac->attr.link_type; mac->if_link_type = mac->attr.link_type;
@@ -436,19 +450,42 @@ int dpaa2_mac_connect(struct dpaa2_mac *mac) @@ -436,19 +450,41 @@ int dpaa2_mac_connect(struct dpaa2_mac *mac)
return -EINVAL; return -EINVAL;
mac->if_mode = err; mac->if_mode = err;
...@@ -93,7 +93,6 @@ index 2302e9c11186..a4aad5431e82 100644 ...@@ -93,7 +93,6 @@ index 2302e9c11186..a4aad5431e82 100644
+ if (err || !strcmp("serdes", phy_name)) { + if (err || !strcmp("serdes", phy_name)) {
+ if (!(mac->features & DPAA2_MAC_FEATURE_PROTOCOL_CHANGE) + if (!(mac->features & DPAA2_MAC_FEATURE_PROTOCOL_CHANGE)
+ || phy_interface_mode_is_rgmii(mac->if_mode)) { + || phy_interface_mode_is_rgmii(mac->if_mode)) {
+ printk("dpaa2_mac_connect: should maybe not enable serdes phy?\n");
+ continue; + continue;
+ } + }
+ +
......
patches/u-boot-LSDK-21.08/0043-lx2160acex7-add-device-tree-for-lx2162-clearfog.patch 0 → 100644
View file @ 92bef239
From 1b7e1dfd077c837d22b4c47fa9ff4908af117725 Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Sat, 27 May 2023 14:28:39 +0300
Subject: [PATCH] lx2160acex7: add device-tree for lx2162 clearfog
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/fsl-lx2162a-clearfog.dts | 375 +++++++++++++++++++++++
arch/arm/dts/fsl-lx2162a-som.dtsi | 4 -
board/solidrun/lx2160a/eth_lx2160acex7.c | 8 +
configs/lx2160acex7_tfa_defconfig | 2 +-
drivers/net/fsl-mc/mc.c | 7 +
6 files changed, 392 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/dts/fsl-lx2162a-clearfog.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b084ee0fa0..a3b8bea6d6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -428,6 +428,7 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-lx2160a-cex7.dtb \
fsl-lx2160a-cex7-8-x-x.dtb \
fsl-lx2160a-half-twins-8-9-x.dtb \
+ fsl-lx2162a-clearfog.dtb \
fsl-lx2162a-som.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
diff --git a/arch/arm/dts/fsl-lx2162a-clearfog.dts b/arch/arm/dts/fsl-lx2162a-clearfog.dts
new file mode 100644
index 0000000000..9764305a84
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2162a-clearfog.dts
@@ -0,0 +1,375 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree file for LX2162A Clearfog
+//
+// Copyright 2022 Josua Mayer <josua@solid-run.com>
+
+/dts-v1/;
+
+#include "fsl-lx2162a-som.dtsi"
+#include "dt-bindings/gpio/gpio.h"
+
+/* work-around for phy address 1 conflict on mdio bus */
+#define OCTOPHY_ADDR_OFFSET_LOWER 0x08
+#define OCTOPHY_ADDR_OFFSET_UPPER 0x08
+#define OCTOPHY_ADDR_LOWER(index) (OCTOPHY_ADDR_OFFSET_LOWER + index)
+#define OCTOPHY_ADDR_UPPER(index) (OCTOPHY_ADDR_OFFSET_UPPER + index)
+
+/ {
+ model = "SolidRun LX2162A Clearfog";
+ compatible = "solidrun,clearfog", "fsl,lx2160a";
+ aliases {
+ crypto = &crypto;
+ serial0 = &uart0;
+ };
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ sfp_at: sfp-at {
+ compatible = "sff,sfp";
+ i2c-bus = <&sfp_i2c0>;
+ mod-def0-gpio = <&gpio2 16 GPIO_ACTIVE_LOW>; /* EVT4_B */
+ maximum-power-milliwatt = <2000>;
+ };
+
+ sfp_ab: sfp-ab {
+ compatible = "sff,sfp";
+ i2c-bus = <&sfp_i2c1>;
+ mod-def0-gpio = <&gpio2 1 GPIO_ACTIVE_LOW>; /* PROC_IRQ1 */
+ maximum-power-milliwatt = <2000>;
+ };
+
+ sfp_bt: sfp-bt {
+ compatible = "sff,sfp";
+ i2c-bus = <&sfp_i2c2>;
+ mod-def0-gpio = <&gpio2 10 GPIO_ACTIVE_LOW>; /* PROC_IRQ10 */
+ maximum-power-milliwatt = <2000>;
+ };
+
+ sfp_bb: sfp-bb {
+ compatible = "sff,sfp";
+ i2c-bus = <&sfp_i2c3>;
+ mod-def0-gpio = <&gpio2 15 GPIO_ACTIVE_LOW>; /* EVT3_B */
+ maximum-power-milliwatt = <2000>;
+ };
+};
+
+&i2c2 {
+ i2c-switch@70 {
+ compatible = "nxp,pca9546";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ i2c-mux-idle-disconnect;
+
+ /* upper 10G connector */
+ sfp_i2c0: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ /* lower 10G connector */
+ sfp_i2c1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ /* upper 25G connector */
+ sfp_i2c2: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ /* lower 25G connector */
+ sfp_i2c3: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+
+ i2c-switch@71 {
+ compatible = "nxp,pca9546";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x71>;
+ i2c-mux-idle-disconnect;
+ mpcie1_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ mpcie0_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ pcieclk_i2c: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ pcieclk@6b {
+ compatible = "skyworks,si53154";
+ reg = <0x6b>;
+ };
+ };
+ };
+};
+
+/*
+ * Serdes 1 Clocks:
+ * - PLLF = 161.1328125MHz
+ * - PLLS = PLLF
+ */
+
+/*
+ * SD1 Protocol 2: 4x 1Gbps
+ * - Lane 0 (H): USXGMII / XFI WRIOP MAC3
+ * - Lane 1 (G): USXGMII / XFI WRIOP MAC4
+ * - Lane 2 (F): USXGMII / XFI WRIOP MAC5
+ * - Lane 3 (E): USXGMII / XFI WRIOP MAC6
+ * Requires either 100MHz or 125MHz reference clock
+ */
+
+/*
+ * SD1 Protocol 3: 4x 10Gbps
+ * - Lane 0 (H): USXGMII / XFI WRIOP MAC3
+ * - Lane 1 (G): USXGMII / XFI WRIOP MAC4
+ * - Lane 2 (F): USXGMII / XFI WRIOP MAC5
+ * - Lane 3 (E): USXGMII / XFI WRIOP MAC6
+ * Requires either 156.25MHz or 161.1328125MHz reference clock
+ */
+
+/*
+ * SD1 Protocol 17: 4x 25Gbps
+ * - Lane 0 (H): 25GE WRIOP MAC3
+ * - Lane 1 (G): 25GE WRIOP MAC4
+ * - Lane 2 (F): 25GE WRIOP MAC5
+ * - Lane 3 (E): 25GE WRIOP MAC6
+ * Requires 161.1328125MHz reference clock
+ */
+
+/*
+ * SD1 Protocol 18: 2x 10Gbps + 2x 25Gbps
+ * - Lane 0 (H): USXGMII / XFI WRIOP MAC3
+ * - Lane 1 (G): USXGMII / XFI WRIOP MAC4
+ * - Lane 2 (F): 25GE WRIOP MAC5
+ * - Lane 3 (E): 25GE WRIOP MAC6
+ * Requires 161.1328125MHz reference clock
+ */
+
+/* upper 10G connector */
+&dpmac3 {
+ status = "okay";
+ managed = "in-band-status";
+ sfp = <&sfp_at>;
+};
+
+/* lower 10G connector */
+&dpmac4 {
+ status = "okay";
+ managed = "in-band-status";
+ sfp = <&sfp_ab>;
+};
+
+&dpmac5 {
+ status = "okay";
+ managed = "in-band-status";
+ sfp = <&sfp_bt>;
+};
+
+&dpmac6 {
+ status = "okay";
+ managed = "in-band-status";
+ sfp = <&sfp_bb>;
+};
+
+/*
+ * Serdes 2 Clocks:
+ * - PLLF = 100MHz (Carrier CLK_SLOT1)
+ * - PLLS = 156.25MHz (SoM)
+ */
+
+/*
+ * SD2 Protocol 7: 4x 1Gbps + 2x PCIe Gen. 2 x1 + 2x 10Gbps
+ * - Lane 0 (A): PCIe.3
+ * - Lane 1 (B): SGMII WRIOP MAC12
+ * - Lane 2 (C): SGMII WRIOP MAC17
+ * - Lane 3 (D): SGMII WRIOP MAC18
+ * - Lane 4 (E): PCIe.4
+ * - Lane 5 (F): SGMII WRIOP MAC16
+ * - Lane 6 (G): USXGMII / XFI WRIOP MAC13
+ * - Lane 7 (H): USXGMII / XFI WRIOP MAC14
+ * Requires 100MHz and 156.25MHz reference clocks
+ */
+
+/*
+ * SD2 Protocol 9: 8x 1Gbps
+ * - Lane 0 (A): SGMII WRIOP MAC11
+ * - Lane 1 (B): SGMII WRIOP MAC12
+ * - Lane 2 (C): SGMII WRIOP MAC17
+ * - Lane 3 (D): SGMII WRIOP MAC18
+ * - Lane 4 (E): SGMII WRIOP MAC15
+ * - Lane 5 (F): SGMII WRIOP MAC16
+ * - Lane 6 (G): SGMII WRIOP MAC13
+ * - Lane 7 (H): SGMII WRIOP MAC14
+ * Requires 100MHz reference clock
+ */
+
+/*
+ * SD2 Protocol 11: 6x 1Gbps + 2x PCIe Gen. 3 x1
+ * - Lane 0 (A): PCIe.3
+ * - Lane 1 (B): SGMII WRIOP MAC12
+ * - Lane 2 (C): SGMII WRIOP MAC17
+ * - Lane 3 (D): SGMII WRIOP MAC18
+ * - Lane 4 (E): PCIe.4
+ * - Lane 5 (F): SGMII WRIOP MAC16
+ * - Lane 6 (G): SGMII WRIOP MAC13
+ * - Lane 7 (H): SGMII WRIOP MAC14
+ * Requires 100MHz reference clock
+ */
+
+&dpmac11 {
+ status = "okay";
+ phy-handle = <&ethernet_phy2>;
+ phy-mode = "rgmii";
+};
+
+&dpmac12 {
+ status = "okay";
+ phy-handle = <&ethernet_phy0>;
+ phy-mode = "rgmii";
+};
+
+&dpmac17 {
+ /* override connection to on-SoM phy */
+ /delete-property/ phy-handle;
+ /delete-property/ phy-connection-type;
+
+ status = "okay";
+ phy-handle = <&ethernet_phy4>;
+ phy-mode = "rgmii";
+};
+
+&dpmac18 {
+ status = "okay";
+ phy-handle = <&ethernet_phy6>;
+ phy-mode = "rgmii";
+};
+
+&dpmac15 {
+ status = "okay";
+ phy-handle = <&ethernet_phy3>;
+ phy-mode = "rgmii";
+};
+
+&dpmac16 {
+ status = "okay";
+ phy-handle = <&ethernet_phy1>;
+ phy-mode = "rgmii";
+};
+
+&dpmac13 {
+ status = "okay";
+ phy-handle = <&ethernet_phy5>;
+ phy-mode = "rgmii";
+};
+
+&dpmac14 {
+ status = "okay";
+ phy-handle = <&ethernet_phy7>;
+ phy-mode = "rgmii";
+};
+
+&emdio1 {
+ status = "okay";
+
+ /*
+ * SoM can have a phy at address 1 connected to SoC Ethernet Controller 1.
+ * It competes for WRIOP MAC17 with Serdes 2 Protocols 7,9,11 - and no connector is wired.
+ */
+ /delete-node/ ethernet-phy@1;
+
+ ethernet_phy0: mv88e3580-p0@0 {
+ reg = <OCTOPHY_ADDR_LOWER(0)>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ max-speed = <1000>;
+ };
+
+ ethernet_phy1: mv88e3580-p1@1 {
+ reg = <OCTOPHY_ADDR_LOWER(1)>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ max-speed = <1000>;
+ };
+
+ ethernet_phy2: mv88e3580-p2@2 {
+ reg = <OCTOPHY_ADDR_LOWER(2)>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ max-speed = <1000>;
+ };
+
+ ethernet_phy3: mv88e3580-p3@3 {
+ reg = <OCTOPHY_ADDR_LOWER(3)>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ max-speed = <1000>;
+ };
+
+ ethernet_phy4: mv88e3580-p4@4 {
+ reg = <OCTOPHY_ADDR_UPPER(4)>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ max-speed = <1000>;
+ };
+
+ ethernet_phy5: mv88e3580-p5@5 {
+ reg = <OCTOPHY_ADDR_UPPER(5)>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ max-speed = <2500>;
+ };
+
+ ethernet_phy6: mv88e3580-p6@6 {
+ reg = <OCTOPHY_ADDR_UPPER(6)>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ max-speed = <1000>;
+ };
+
+ ethernet_phy7: mv88e3580-p7@7 {
+ reg = <OCTOPHY_ADDR_UPPER(7)>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ max-speed = <2500>;
+ };
+};
+
+/* CON7 */
+&pcie4 {
+ status = "disabled";
+};
+
+/* CON8 */
+&pcie3 {
+ status = "disabled";
+};
+
+&sata0 {
+ status = "disabled";
+};
+
+&sata1 {
+ status = "disabled";
+};
+
+&sata2 {
+ status = "disabled";
+};
+
+&sata3 {
+ status = "disabled";
+};
+
+&usb0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-lx2162a-som.dtsi b/arch/arm/dts/fsl-lx2162a-som.dtsi
index f254421fae..7f18500682 100644
--- a/arch/arm/dts/fsl-lx2162a-som.dtsi
+++ b/arch/arm/dts/fsl-lx2162a-som.dtsi
@@ -28,10 +28,6 @@
&emdio1 {
status = "okay";
- cortina_phy: ethernet-phy@0 {
- reg = <0x0>;
- };
-
rgmii_phy1: ethernet-phy@1 {
/* AR8035 PHY - "compatible" property not strictly needed */
compatible = "ethernet-phy-id004d.d072";
diff --git a/board/solidrun/lx2160a/eth_lx2160acex7.c b/board/solidrun/lx2160a/eth_lx2160acex7.c
index 6c5e4cad6a..9bc43a5ed7 100644
--- a/board/solidrun/lx2160a/eth_lx2160acex7.c
+++ b/board/solidrun/lx2160a/eth_lx2160acex7.c
@@ -277,6 +277,14 @@ int board_fit_config_name_match(const char *name)
srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
if (get_svr() & 0x800) {
+ /* Notice - order of matching is similar to order of CONFIG_OF_LIST */
+ if (!strncmp(name, "fsl-lx2162a-clearfog", 28)) {
+ /* Once SW support for 18/7 is complete, 18/11 may be dropped */
+ if (srds_s1 == 18 && srds_s2 == 7 ||
+ srds_s1 == 18 && srds_s2 == 9 ||
+ srds_s1 == 18 && srds_s2 == 11)
+ return 0;
+ }
if (!strncmp(name, "fsl-lx2162a-som", 15)) {
return 0;
}
diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
index 3dd2272510..061934ae71 100644
--- a/configs/lx2160acex7_tfa_defconfig
+++ b/configs/lx2160acex7_tfa_defconfig
@@ -40,7 +40,7 @@ CONFIG_CMD_NVME=y
CONFIG_NVME=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="fsl-lx2160a-half-twins-8-9-x fsl-lx2160a-cex7-8-x-x fsl-lx2160a-cex7 fsl-lx2162a-som"
+CONFIG_OF_LIST="fsl-lx2160a-half-twins-8-9-x fsl-lx2160a-cex7-8-x-x fsl-lx2160a-cex7 fsl-lx2162a-clearfog fsl-lx2162a-som"
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 914ec001ec..2974d2c09b 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -432,6 +432,13 @@ static int mc_fixup_mac_addrs(void *blob, enum mc_fixup_type type)
phy_interface_strings[wriop_get_enet_if(i)]);
eth_dev = eth_get_dev_by_name(ethname);
+ if (eth_dev == NULL && wriop_get_enet_if(i) == PHY_INTERFACE_MODE_SGMII) {
+ /* maybe connected to copper PHY ... */
+ snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s", i,
+ phy_interface_strings[PHY_INTERFACE_MODE_RGMII]);
+
+ eth_dev = eth_get_dev_by_name(ethname);
+ }
if (eth_dev == NULL)
continue;
--
2.35.3
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