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Commit bd2d3fd7 authored by Josua Mayer's avatar Josua Mayer
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add partial support for LX2162A Clearfog 

LX2162A Clearfog support only covers 8x 1G rj45 + 2x 10G fixed-link sfp.
Signed-off-by: default avatarJosua Mayer <josua@solid-run.com>
parent 329a7255
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Showing with 2467 additions and 3 deletions
patches/linux-LSDK-21.08/0022-arm64-dts-lx2162a-som-add-EEPROMs.patch 0 → 100644
View file @ bd2d3fd7
From 1b36215d63699e054f72e0aa3f99812ab7132260 Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Thu, 8 Sep 2022 14:45:03 +0300
Subject: [PATCH] arm64: dts: lx2162a-som: add EEPROMs
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2162a-som.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-som.dtsi
index 9b90cef2df04..8e4d898971ca 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-som.dtsi
@@ -44,6 +44,11 @@ tps5622@69 {
compatible = "tps53679";
reg = <0x69>;
};
+
+ config_eeprom: eeprom@57 {
+ reg = <0x57>;
+ compatible = "st,m24c02", "atmel,24c02";
+ };
};
&i2c2 {
@@ -52,6 +57,11 @@ &i2c2 {
&i2c4 {
status = "okay";
+
+ variable_eeprom: eeprom@54 {
+ reg = <0x54>;
+ compatible = "st,m24m02", "atmel,24c2048";
+ };
};
&i2c5 {
--
2.37.3
patches/linux-LSDK-21.08/0023-arm64-dts-add-lx2162-clearfog.patch 0 → 100644
View file @ bd2d3fd7
From 79ac46f001064cbd954203d571841b49ded72856 Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Thu, 8 Sep 2022 15:17:03 +0300
Subject: [PATCH] arm64: dts: add lx2162 clearfog
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../dts/freescale/fsl-lx2162a-clearfog.dts | 471 ++++++++++++++++++
2 files changed, 472 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index bf51a3cfeda7..3896283a75cd 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -54,6 +54,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-clearfog-cx.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-half-twins.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-clearfog.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-solidnet.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
new file mode 100644
index 000000000000..b9fe7f017c3c
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
@@ -0,0 +1,471 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree file for LX2162A Clearfog
+//
+// Copyright 2022 Josua Mayer <josua@solid-run.com>
+
+/dts-v1/;
+
+#include "fsl-lx2162a-som.dtsi"
+
+/* work-around for phy address 1 conflict on mdio bus */
+#define OCTOPHY_ADDR_OFFSET_LOWER 0x08
+#define OCTOPHY_ADDR_OFFSET_UPPER 0x00
+#define OCTOPHY_ADDR_LOWER(index) (OCTOPHY_ADDR_OFFSET_LOWER + index)
+#define OCTOPHY_ADDR_UPPER(index) (OCTOPHY_ADDR_OFFSET_UPPER + index)
+
+/ {
+ model = "SolidRun LX2162A Clearfog";
+ compatible = "solidrun,clearfog", "fsl,lx2160a";
+ aliases {
+ crypto = &crypto;
+ serial0 = &uart0;
+ };
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ sfp0: sfp-0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&sfp_i2c0>;
+ maximum-power-milliwatt = <2000>;
+ };
+
+ sfp1: sfp-1 {
+ compatible = "sff,sfp";
+ i2c-bus = <&sfp_i2c1>;
+ maximum-power-milliwatt = <2000>;
+ };
+
+ sfp2: sfp-2 {
+ compatible = "sff,sfp";
+ i2c-bus = <&sfp_i2c2>;
+ maximum-power-milliwatt = <2000>;
+ };
+
+ sfp3: sfp-3 {
+ compatible = "sff,sfp";
+ i2c-bus = <&sfp_i2c3>;
+ maximum-power-milliwatt = <2000>;
+ };
+};
+
+&i2c2 {
+ retimer@30 {
+ compatible = "ti,ds250df410";
+ reg = <0x30>;
+ };
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9546";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ i2c-mux-idle-disconnect;
+
+ /* upper 10G connector */
+ sfp_i2c0: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ /* lower 10G connector */
+ sfp_i2c1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ /* upper 25G connector */
+ sfp_i2c2: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ /* lower 25G connector */
+ sfp_i2c3: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+
+ i2c-switch@71 {
+ compatible = "nxp,pca9546";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x71>;
+ i2c-mux-idle-disconnect;
+ mpcie1_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ mpcie0_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ pcieclk_i2c: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ pcieclk@6b {
+ compatible = "skyworks,si53154";
+ reg = <0x6b>;
+ };
+ };
+ };
+};
+
+/*
+ * Serdes 1 Clocks:
+ * - PLLF = 161.1328125MHz
+ * - PLLS = PLLF
+ */
+
+/*
+ * SD1 Protocol 2: 4x 1Gbps
+ * - Lane 0 (H): USXGMII / XFI WRIOP MAC3
+ * - Lane 1 (G): USXGMII / XFI WRIOP MAC4
+ * - Lane 2 (F): USXGMII / XFI WRIOP MAC5
+ * - Lane 3 (E): USXGMII / XFI WRIOP MAC6
+ * Requires either 100MHz or 125MHz reference clock
+ */
+
+/*
+ * SD1 Protocol 3: 4x 10Gbps
+ * - Lane 0 (H): USXGMII / XFI WRIOP MAC3
+ * - Lane 1 (G): USXGMII / XFI WRIOP MAC4
+ * - Lane 2 (F): USXGMII / XFI WRIOP MAC5
+ * - Lane 3 (E): USXGMII / XFI WRIOP MAC6
+ * Requires either 156.25MHz or 161.1328125MHz reference clock
+ */
+
+/*
+ * SD1 Protocol 17: 4x 25Gbps
+ * - Lane 0 (H): 25GE WRIOP MAC3
+ * - Lane 1 (G): 25GE WRIOP MAC4
+ * - Lane 2 (F): 25GE WRIOP MAC5
+ * - Lane 3 (E): 25GE WRIOP MAC6
+ * Requires 161.1328125MHz reference clock
+ */
+
+/*
+ * SD1 Protocol 18: 2x 10Gbps + 2x 25Gbps
+ * - Lane 0 (H): USXGMII / XFI WRIOP MAC3
+ * - Lane 1 (G): USXGMII / XFI WRIOP MAC4
+ * - Lane 2 (F): 25GE WRIOP MAC5
+ * - Lane 3 (E): 25GE WRIOP MAC6
+ * Requires 161.1328125MHz reference clock
+ */
+
+/* upper 10G connector */
+&dpmac3 {
+ status = "okay";
+ phys = <&serdes1_lane_h>;
+ phy-connection-type = "10gbase-r";
+ // sfp = <&sfp0>;
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ };
+};
+
+&pcs_mdio3 {
+ status = "okay";
+};
+
+/* lower 10G connector */
+&dpmac4 {
+ status = "okay";
+ phys = <&serdes1_lane_g>;
+ phy-connection-type = "10gbase-r";
+ // sfp = <&sfp1>;
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ };
+};
+
+&pcs_mdio4 {
+ status = "okay";
+};
+
+&dpmac5 {
+ status = "okay";
+ phys = <&serdes1_lane_f>;
+ phy-connection-type = "10gbase-r";
+ //phy-connection-type = "25g-aui";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ };
+};
+
+&pcs_mdio5 {
+ status = "okay";
+};
+
+&dpmac6 {
+ status = "okay";
+ phys = <&serdes1_lane_e>;
+ phy-connection-type = "10gbase-r";
+ //phy-connection-type = "25g-aui";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ };
+};
+
+&pcs_mdio6 {
+ status = "okay";
+};
+
+&serdes_1 {
+ status = "okay";
+};
+
+/*
+ * Serdes 2 Clocks:
+ * - PLLF = 100MHz (Carrier CLK_SLOT1)
+ * - PLLS = 156.25MHz (SoM)
+ */
+
+/*
+ * SD2 Protocol 7: 4x 1Gbps + 2x PCIe Gen. 2 x1 + 2x 10Gbps
+ * - Lane 0 (A): PCIe.3
+ * - Lane 1 (B): SGMII WRIOP MAC12
+ * - Lane 2 (C): SGMII WRIOP MAC17
+ * - Lane 3 (D): SGMII WRIOP MAC18
+ * - Lane 4 (E): PCIe.4
+ * - Lane 5 (F): SGMII WRIOP MAC16
+ * - Lane 6 (G): USXGMII / XFI WRIOP MAC13
+ * - Lane 7 (H): USXGMII / XFI WRIOP MAC14
+ * Requires 100MHz and 156.25MHz reference clocks
+ */
+
+/*
+ * SD2 Protocol 9: 8x 1Gbps
+ * - Lane 0 (A): SGMII WRIOP MAC11
+ * - Lane 1 (B): SGMII WRIOP MAC12
+ * - Lane 2 (C): SGMII WRIOP MAC17
+ * - Lane 3 (D): SGMII WRIOP MAC18
+ * - Lane 4 (E): SGMII WRIOP MAC15
+ * - Lane 5 (F): SGMII WRIOP MAC16
+ * - Lane 6 (G): SGMII WRIOP MAC13
+ * - Lane 7 (H): SGMII WRIOP MAC14
+ * Requires 100MHz reference clock
+ */
+
+/*
+ * SD2 Protocol 11: 6x 1Gbps + 2x PCIe Gen. 3 x1
+ * - Lane 0 (A): PCIe.3
+ * - Lane 1 (B): SGMII WRIOP MAC12
+ * - Lane 2 (C): SGMII WRIOP MAC17
+ * - Lane 3 (D): SGMII WRIOP MAC18
+ * - Lane 4 (E): PCIe.4
+ * - Lane 5 (F): SGMII WRIOP MAC16
+ * - Lane 6 (G): SGMII WRIOP MAC13
+ * - Lane 7 (H): SGMII WRIOP MAC14
+ * Requires 100MHz reference clock
+ */
+
+&dpmac11 {
+ status = "okay";
+ phys = <&serdes2_lane_a>;
+ phy-handle = <&ethernet_phy2>;
+ phy-connection-type = "rgmii-id";
+};
+
+&pcs_mdio11 {
+ status = "okay";
+};
+
+&dpmac12 {
+ status = "okay";
+ phys = <&serdes2_lane_b>;
+ phy-handle = <&ethernet_phy0>;
+ phy-connection-type = "rgmii-id";
+};
+
+&pcs_mdio12 {
+ status = "okay";
+};
+
+&dpmac17 {
+ /* override connection to on-SoM phy */
+ /delete-property/ phy-handle;
+ /delete-property/ phy-connection-type;
+
+ status = "okay";
+ phys = <&serdes2_lane_c>;
+ phy-handle = <&ethernet_phy4>;
+ phy-connection-type = "rgmii-id";
+};
+
+&pcs_mdio17 {
+ status = "okay";
+};
+
+&dpmac18 {
+ status = "okay";
+ phys = <&serdes2_lane_d>;
+ phy-handle = <&ethernet_phy6>;
+ phy-connection-type = "rgmii-id";
+};
+
+&pcs_mdio18 {
+ status = "okay";
+};
+
+&dpmac15 {
+ status = "okay";
+ phys = <&serdes2_lane_e>;
+ phy-handle = <&ethernet_phy3>;
+ phy-connection-type = "rgmii-id";
+};
+
+&pcs_mdio15 {
+ status = "okay";
+};
+
+&dpmac16 {
+ status = "okay";
+ phys = <&serdes2_lane_f>;
+ phy-handle = <&ethernet_phy1>;
+ phy-connection-type = "rgmii-id";
+};
+
+&pcs_mdio16 {
+ status = "okay";
+};
+
+&dpmac13 {
+ status = "okay";
+ phys = <&serdes2_lane_g>;
+ phy-handle = <&ethernet_phy5>;
+ phy-connection-type = "rgmii-id";
+};
+
+&pcs_mdio13 {
+ status = "okay";
+};
+
+&dpmac14 {
+ status = "okay";
+ phys = <&serdes2_lane_h>;
+ phy-handle = <&ethernet_phy7>;
+ phy-connection-type = "rgmii-id";
+};
+
+&pcs_mdio14 {
+ status = "okay";
+};
+
+&emdio1 {
+ status = "okay";
+
+ /*
+ * SoM can have a phy at address 1 connected to SoC Ethernet Controller 1.
+ * It competes for WRIOP MAC17 with Serdes 2 Protocols 7,9,11 - and no connector is wired.
+ */
+ /delete-node/ ethernet-phy@1;
+
+ ethernet_phy0: mv88e3580-p0@0 {
+ reg = <OCTOPHY_ADDR_LOWER(0)>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ rx-internal-delay-ps = <2000>;
+ tx-internal-delay-ps = <2000>;
+ };
+
+ ethernet_phy1: mv88e3580-p1@1 {
+ reg = <OCTOPHY_ADDR_LOWER(1)>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ rx-internal-delay-ps = <2000>;
+ tx-internal-delay-ps = <2000>;
+ };
+
+ ethernet_phy2: mv88e3580-p2@2 {
+ reg = <OCTOPHY_ADDR_LOWER(2)>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ rx-internal-delay-ps = <2000>;
+ tx-internal-delay-ps = <2000>;
+ };
+
+ ethernet_phy3: mv88e3580-p3@3 {
+ reg = <OCTOPHY_ADDR_LOWER(3)>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ rx-internal-delay-ps = <2000>;
+ tx-internal-delay-ps = <2000>;
+ };
+
+ ethernet_phy4: mv88e3580-p4@4 {
+ reg = <OCTOPHY_ADDR_UPPER(4)>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ rx-internal-delay-ps = <2000>;
+ tx-internal-delay-ps = <2000>;
+ };
+
+ ethernet_phy5: mv88e3580-p5@5 {
+ reg = <OCTOPHY_ADDR_UPPER(5)>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ rx-internal-delay-ps = <2000>;
+ tx-internal-delay-ps = <2000>;
+ };
+
+ ethernet_phy6: mv88e3580-p6@6 {
+ reg = <OCTOPHY_ADDR_UPPER(6)>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ rx-internal-delay-ps = <2000>;
+ tx-internal-delay-ps = <2000>;
+ };
+
+ ethernet_phy7: mv88e3580-p7@7 {
+ reg = <OCTOPHY_ADDR_UPPER(7)>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ rx-internal-delay-ps = <2000>;
+ tx-internal-delay-ps = <2000>;
+ };
+};
+
+/* CON7 */
+&pcie4 {
+ status = "disabled";
+};
+
+/* CON8 */
+&pcie3 {
+ status = "disabled";
+};
+
+&serdes_2 {
+ status = "okay";
+};
+
+&sata0 {
+ status = "disabled";
+};
+
+&sata1 {
+ status = "disabled";
+};
+
+&sata2 {
+ status = "disabled";
+};
+
+&sata3 {
+ status = "disabled";
+};
+
+&usb0 {
+ status = "okay";
+};
--
2.37.3
patches/mc-utils/0012-lx2162som-add-configurations-for-clearfog.patch 0 → 100644
View file @ bd2d3fd7
From bcd5bf8204ef95febea2b81fea72814087ec0c98 Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Thu, 8 Sep 2022 14:26:46 +0300
Subject: [PATCH] lx2162som: add configurations for clearfog
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
.gitignore | 1 +
.../LX2162-USOM/clearfog-s1_0-s2_0-dpc.dts | 68 ++++++++
.../LX2162-USOM/clearfog-s1_0-s2_0-dpl.dts | 123 ++++++++++++++
.../LX2162-USOM/clearfog-s1_0-s2_11-dpc.dts | 102 ++++++++++++
.../LX2162-USOM/clearfog-s1_0-s2_11-dpl.dts | 142 ++++++++++++++++
.../LX2162-USOM/clearfog-s1_0-s2_7-dpc.dts | 102 ++++++++++++
.../LX2162-USOM/clearfog-s1_0-s2_7-dpl.dts | 142 ++++++++++++++++
.../LX2162-USOM/clearfog-s1_0-s2_9-dpc.dts | 110 ++++++++++++
.../LX2162-USOM/clearfog-s1_0-s2_9-dpl.dts | 146 ++++++++++++++++
.../LX2162-USOM/clearfog-s1_3-s2_0-dpc.dts | 94 +++++++++++
.../LX2162-USOM/clearfog-s1_3-s2_0-dpl.dts | 138 +++++++++++++++
.../LX2162-USOM/clearfog-s1_3-s2_9-dpc.dts | 127 ++++++++++++++
.../LX2162-USOM/clearfog-s1_3-s2_9-dpl.dts | 157 ++++++++++++++++++
13 files changed, 1452 insertions(+)
create mode 100644 .gitignore
create mode 100644 config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_0-dpc.dts
create mode 100644 config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_0-dpl.dts
create mode 100644 config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_11-dpc.dts
create mode 100644 config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_11-dpl.dts
create mode 100644 config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_7-dpc.dts
create mode 100644 config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_7-dpl.dts
create mode 100644 config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_9-dpc.dts
create mode 100644 config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_9-dpl.dts
create mode 100644 config/lx2160a/LX2162-USOM/clearfog-s1_3-s2_0-dpc.dts
create mode 100644 config/lx2160a/LX2162-USOM/clearfog-s1_3-s2_0-dpl.dts
create mode 100644 config/lx2160a/LX2162-USOM/clearfog-s1_3-s2_9-dpc.dts
create mode 100644 config/lx2160a/LX2162-USOM/clearfog-s1_3-s2_9-dpl.dts
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..b60ed20
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1 @@
+*.dtb
diff --git a/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_0-dpc.dts b/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_0-dpc.dts
new file mode 100644
index 0000000..fcc3fee
--- /dev/null
+++ b/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_0-dpc.dts
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2020 NXP
+ * Copyright 2022 Josua Mayer <josua@solid-run.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/ {
+ resources {
+ icid_pools {
+ icid_pool@1 {
+ num = <0x64>;
+ base_icid = <0x0>;
+ };
+ };
+ };
+
+ mc_general {
+ log {
+ mode = "LOG_MODE_ON";
+ level = "LOG_LEVEL_WARNING";
+ };
+
+ console {
+ mode = "CONSOLE_MODE_OFF";
+ uart_id = <0x4>;
+ level = "LOG_LEVEL_WARNING";
+ };
+ };
+
+ controllers {
+ qbman {
+ /* Transform this number of 8-WQ channels into four times
+ * as many 2-WQ channels. This allows the creation of a
+ * larger number of DPCONs.
+ */
+ wq_ch_conversion = <64>;
+ };
+ };
+
+ board_info {
+ ports {
+ };
+ };
+};
diff --git a/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_0-dpl.dts b/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_0-dpl.dts
new file mode 100644
index 0000000..ff40d79
--- /dev/null
+++ b/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_0-dpl.dts
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2020 NXP
+ * Copyright 2022 Josua Mayer <josua@solid-run.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+/ {
+ dpl-version = <10>;
+
+ containers {
+ dprc@1 {
+ compatible = "fsl,dprc";
+ parent = "none";
+ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_OBJ_CREATE_ALLOWED", "DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED";
+
+ objects {
+ obj_set@dpmcp {
+ type = "dpmcp";
+ ids = <0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23>;
+ };
+ };
+ };
+ };
+
+ objects {
+ dpmcp@1 {
+ };
+ dpmcp@2 {
+ };
+ dpmcp@3 {
+ };
+ dpmcp@4 {
+ };
+ dpmcp@5 {
+ };
+ dpmcp@6 {
+ };
+ dpmcp@7 {
+ };
+ dpmcp@8 {
+ };
+ dpmcp@9 {
+ };
+ dpmcp@10 {
+ };
+ dpmcp@11 {
+ };
+ dpmcp@12 {
+ };
+ dpmcp@13 {
+ };
+ dpmcp@14 {
+ };
+ dpmcp@15 {
+ };
+ dpmcp@16 {
+ };
+ dpmcp@17 {
+ };
+ dpmcp@18 {
+ };
+ dpmcp@19 {
+ };
+ dpmcp@20 {
+ };
+ dpmcp@21 {
+ };
+ dpmcp@22 {
+ };
+ dpmcp@23 {
+ };
+ dpmcp@24 {
+ };
+ dpmcp@25 {
+ };
+ dpmcp@26 {
+ };
+ dpmcp@27 {
+ };
+ dpmcp@28 {
+ };
+ dpmcp@29 {
+ };
+ dpmcp@30 {
+ };
+ dpmcp@31 {
+ };
+ dpmcp@32 {
+ };
+ dpmcp@33 {
+ };
+ dpmcp@34 {
+ };
+ dpmcp@35 {
+ };
+ };
+
+ connections {
+ };
+};
diff --git a/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_11-dpc.dts b/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_11-dpc.dts
new file mode 100644
index 0000000..b199f64
--- /dev/null
+++ b/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_11-dpc.dts
@@ -0,0 +1,102 @@
+/*
+ * Copyright 2020 NXP
+ * Copyright 2022 Josua Mayer <josua@solid-run.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/ {
+ resources {
+ icid_pools {
+ icid_pool@1 {
+ num = <0x64>;
+ base_icid = <0x0>;
+ };
+ };
+ };
+
+ mc_general {
+ log {
+ mode = "LOG_MODE_ON";
+ level = "LOG_LEVEL_WARNING";
+ };
+
+ console {
+ mode = "CONSOLE_MODE_OFF";
+ uart_id = <0x4>;
+ level = "LOG_LEVEL_WARNING";
+ };
+ };
+
+ controllers {
+ qbman {
+ /* Transform this number of 8-WQ channels into four times
+ * as many 2-WQ channels. This allows the creation of a
+ * larger number of DPCONs.
+ */
+ wq_ch_conversion = <64>;
+ };
+ };
+
+ board_info {
+ recycle_ports {
+ recycle@1 {
+ max_rate = "1G";
+ };
+
+ recycle@2 {
+ max_rate = "1G";
+ };
+ };
+
+ ports {
+ /* Serdes 2 */
+ mac@12 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@13 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@14 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@16 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@17 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@18 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ };
+ };
+};
diff --git a/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_11-dpl.dts b/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_11-dpl.dts
new file mode 100644
index 0000000..766b04d
--- /dev/null
+++ b/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_11-dpl.dts
@@ -0,0 +1,142 @@
+/*
+ * Copyright 2020 NXP
+ * Copyright 2022 Josua Mayer <josua@solid-run.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+/ {
+ dpl-version = <10>;
+
+ containers {
+ dprc@1 {
+ compatible = "fsl,dprc";
+ parent = "none";
+ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_OBJ_CREATE_ALLOWED", "DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED";
+
+ objects {
+ obj_set@dpmac {
+ type = "dpmac";
+ ids = <0xc 0xd 0xe 0x10 0x11 0x12>;
+ };
+
+ obj_set@dpmcp {
+ type = "dpmcp";
+ ids = <0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23>;
+ };
+ };
+ };
+ };
+
+ objects {
+ /* Serdes 2 */
+ dpmac@12 {
+ };
+ dpmac@13 {
+ };
+ dpmac@14 {
+ };
+ dpmac@16 {
+ };
+ dpmac@17 {
+ };
+ dpmac@18 {
+ };
+
+ dpmcp@1 {
+ };
+ dpmcp@2 {
+ };
+ dpmcp@3 {
+ };
+ dpmcp@4 {
+ };
+ dpmcp@5 {
+ };
+ dpmcp@6 {
+ };
+ dpmcp@7 {
+ };
+ dpmcp@8 {
+ };
+ dpmcp@9 {
+ };
+ dpmcp@10 {
+ };
+ dpmcp@11 {
+ };
+ dpmcp@12 {
+ };
+ dpmcp@13 {
+ };
+ dpmcp@14 {
+ };
+ dpmcp@15 {
+ };
+ dpmcp@16 {
+ };
+ dpmcp@17 {
+ };
+ dpmcp@18 {
+ };
+ dpmcp@19 {
+ };
+ dpmcp@20 {
+ };
+ dpmcp@21 {
+ };
+ dpmcp@22 {
+ };
+ dpmcp@23 {
+ };
+ dpmcp@24 {
+ };
+ dpmcp@25 {
+ };
+ dpmcp@26 {
+ };
+ dpmcp@27 {
+ };
+ dpmcp@28 {
+ };
+ dpmcp@29 {
+ };
+ dpmcp@30 {
+ };
+ dpmcp@31 {
+ };
+ dpmcp@32 {
+ };
+ dpmcp@33 {
+ };
+ dpmcp@34 {
+ };
+ dpmcp@35 {
+ };
+ };
+
+ connections {
+ };
+};
diff --git a/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_7-dpc.dts b/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_7-dpc.dts
new file mode 100644
index 0000000..b199f64
--- /dev/null
+++ b/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_7-dpc.dts
@@ -0,0 +1,102 @@
+/*
+ * Copyright 2020 NXP
+ * Copyright 2022 Josua Mayer <josua@solid-run.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/ {
+ resources {
+ icid_pools {
+ icid_pool@1 {
+ num = <0x64>;
+ base_icid = <0x0>;
+ };
+ };
+ };
+
+ mc_general {
+ log {
+ mode = "LOG_MODE_ON";
+ level = "LOG_LEVEL_WARNING";
+ };
+
+ console {
+ mode = "CONSOLE_MODE_OFF";
+ uart_id = <0x4>;
+ level = "LOG_LEVEL_WARNING";
+ };
+ };
+
+ controllers {
+ qbman {
+ /* Transform this number of 8-WQ channels into four times
+ * as many 2-WQ channels. This allows the creation of a
+ * larger number of DPCONs.
+ */
+ wq_ch_conversion = <64>;
+ };
+ };
+
+ board_info {
+ recycle_ports {
+ recycle@1 {
+ max_rate = "1G";
+ };
+
+ recycle@2 {
+ max_rate = "1G";
+ };
+ };
+
+ ports {
+ /* Serdes 2 */
+ mac@12 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@13 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@14 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@16 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@17 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@18 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ };
+ };
+};
diff --git a/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_7-dpl.dts b/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_7-dpl.dts
new file mode 100644
index 0000000..766b04d
--- /dev/null
+++ b/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_7-dpl.dts
@@ -0,0 +1,142 @@
+/*
+ * Copyright 2020 NXP
+ * Copyright 2022 Josua Mayer <josua@solid-run.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+/ {
+ dpl-version = <10>;
+
+ containers {
+ dprc@1 {
+ compatible = "fsl,dprc";
+ parent = "none";
+ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_OBJ_CREATE_ALLOWED", "DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED";
+
+ objects {
+ obj_set@dpmac {
+ type = "dpmac";
+ ids = <0xc 0xd 0xe 0x10 0x11 0x12>;
+ };
+
+ obj_set@dpmcp {
+ type = "dpmcp";
+ ids = <0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23>;
+ };
+ };
+ };
+ };
+
+ objects {
+ /* Serdes 2 */
+ dpmac@12 {
+ };
+ dpmac@13 {
+ };
+ dpmac@14 {
+ };
+ dpmac@16 {
+ };
+ dpmac@17 {
+ };
+ dpmac@18 {
+ };
+
+ dpmcp@1 {
+ };
+ dpmcp@2 {
+ };
+ dpmcp@3 {
+ };
+ dpmcp@4 {
+ };
+ dpmcp@5 {
+ };
+ dpmcp@6 {
+ };
+ dpmcp@7 {
+ };
+ dpmcp@8 {
+ };
+ dpmcp@9 {
+ };
+ dpmcp@10 {
+ };
+ dpmcp@11 {
+ };
+ dpmcp@12 {
+ };
+ dpmcp@13 {
+ };
+ dpmcp@14 {
+ };
+ dpmcp@15 {
+ };
+ dpmcp@16 {
+ };
+ dpmcp@17 {
+ };
+ dpmcp@18 {
+ };
+ dpmcp@19 {
+ };
+ dpmcp@20 {
+ };
+ dpmcp@21 {
+ };
+ dpmcp@22 {
+ };
+ dpmcp@23 {
+ };
+ dpmcp@24 {
+ };
+ dpmcp@25 {
+ };
+ dpmcp@26 {
+ };
+ dpmcp@27 {
+ };
+ dpmcp@28 {
+ };
+ dpmcp@29 {
+ };
+ dpmcp@30 {
+ };
+ dpmcp@31 {
+ };
+ dpmcp@32 {
+ };
+ dpmcp@33 {
+ };
+ dpmcp@34 {
+ };
+ dpmcp@35 {
+ };
+ };
+
+ connections {
+ };
+};
diff --git a/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_9-dpc.dts b/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_9-dpc.dts
new file mode 100644
index 0000000..c780130
--- /dev/null
+++ b/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_9-dpc.dts
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2020 NXP
+ * Copyright 2022 Josua Mayer <josua@solid-run.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/ {
+ resources {
+ icid_pools {
+ icid_pool@1 {
+ num = <0x64>;
+ base_icid = <0x0>;
+ };
+ };
+ };
+
+ mc_general {
+ log {
+ mode = "LOG_MODE_ON";
+ level = "LOG_LEVEL_WARNING";
+ };
+
+ console {
+ mode = "CONSOLE_MODE_OFF";
+ uart_id = <0x4>;
+ level = "LOG_LEVEL_WARNING";
+ };
+ };
+
+ controllers {
+ qbman {
+ /* Transform this number of 8-WQ channels into four times
+ * as many 2-WQ channels. This allows the creation of a
+ * larger number of DPCONs.
+ */
+ wq_ch_conversion = <64>;
+ };
+ };
+
+ board_info {
+ recycle_ports {
+ recycle@1 {
+ max_rate = "1G";
+ };
+
+ recycle@2 {
+ max_rate = "1G";
+ };
+ };
+
+ ports {
+ /* Serdes 2 */
+ mac@11 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@12 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@13 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@14 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@15 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@16 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@17 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@18 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ };
+ };
+};
diff --git a/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_9-dpl.dts b/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_9-dpl.dts
new file mode 100644
index 0000000..066238a
--- /dev/null
+++ b/config/lx2160a/LX2162-USOM/clearfog-s1_0-s2_9-dpl.dts
@@ -0,0 +1,146 @@
+/*
+ * Copyright 2020 NXP
+ * Copyright 2022 Josua Mayer <josua@solid-run.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+/ {
+ dpl-version = <10>;
+
+ containers {
+ dprc@1 {
+ compatible = "fsl,dprc";
+ parent = "none";
+ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_OBJ_CREATE_ALLOWED", "DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED";
+
+ objects {
+ obj_set@dpmac {
+ type = "dpmac";
+ ids = <0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12>;
+ };
+
+ obj_set@dpmcp {
+ type = "dpmcp";
+ ids = <0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23>;
+ };
+ };
+ };
+ };
+
+ objects {
+ /* Serdes 2 */
+ dpmac@11 {
+ };
+ dpmac@12 {
+ };
+ dpmac@13 {
+ };
+ dpmac@14 {
+ };
+ dpmac@15 {
+ };
+ dpmac@16 {
+ };
+ dpmac@17 {
+ };
+ dpmac@18 {
+ };
+
+ dpmcp@1 {
+ };
+ dpmcp@2 {
+ };
+ dpmcp@3 {
+ };
+ dpmcp@4 {
+ };
+ dpmcp@5 {
+ };
+ dpmcp@6 {
+ };
+ dpmcp@7 {
+ };
+ dpmcp@8 {
+ };
+ dpmcp@9 {
+ };
+ dpmcp@10 {
+ };
+ dpmcp@11 {
+ };
+ dpmcp@12 {
+ };
+ dpmcp@13 {
+ };
+ dpmcp@14 {
+ };
+ dpmcp@15 {
+ };
+ dpmcp@16 {
+ };
+ dpmcp@17 {
+ };
+ dpmcp@18 {
+ };
+ dpmcp@19 {
+ };
+ dpmcp@20 {
+ };
+ dpmcp@21 {
+ };
+ dpmcp@22 {
+ };
+ dpmcp@23 {
+ };
+ dpmcp@24 {
+ };
+ dpmcp@25 {
+ };
+ dpmcp@26 {
+ };
+ dpmcp@27 {
+ };
+ dpmcp@28 {
+ };
+ dpmcp@29 {
+ };
+ dpmcp@30 {
+ };
+ dpmcp@31 {
+ };
+ dpmcp@32 {
+ };
+ dpmcp@33 {
+ };
+ dpmcp@34 {
+ };
+ dpmcp@35 {
+ };
+ };
+
+ connections {
+ };
+};
diff --git a/config/lx2160a/LX2162-USOM/clearfog-s1_3-s2_0-dpc.dts b/config/lx2160a/LX2162-USOM/clearfog-s1_3-s2_0-dpc.dts
new file mode 100644
index 0000000..db6f440
--- /dev/null
+++ b/config/lx2160a/LX2162-USOM/clearfog-s1_3-s2_0-dpc.dts
@@ -0,0 +1,94 @@
+/*
+ * Copyright 2020 NXP
+ * Copyright 2022 Josua Mayer <josua@solid-run.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/ {
+ resources {
+ icid_pools {
+ icid_pool@1 {
+ num = <0x64>;
+ base_icid = <0x0>;
+ };
+ };
+ };
+
+ mc_general {
+ log {
+ mode = "LOG_MODE_ON";
+ level = "LOG_LEVEL_WARNING";
+ };
+
+ console {
+ mode = "CONSOLE_MODE_OFF";
+ uart_id = <0x4>;
+ level = "LOG_LEVEL_WARNING";
+ };
+ };
+
+ controllers {
+ qbman {
+ /* Transform this number of 8-WQ channels into four times
+ * as many 2-WQ channels. This allows the creation of a
+ * larger number of DPCONs.
+ */
+ wq_ch_conversion = <64>;
+ };
+ };
+
+ board_info {
+ recycle_ports {
+ recycle@1 {
+ max_rate = "1G";
+ };
+
+ recycle@2 {
+ max_rate = "1G";
+ };
+ };
+
+ ports {
+ /* Serdes 1 */
+ mac@3 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@4 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@5 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@6 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ };
+ };
+};
diff --git a/config/lx2160a/LX2162-USOM/clearfog-s1_3-s2_0-dpl.dts b/config/lx2160a/LX2162-USOM/clearfog-s1_3-s2_0-dpl.dts
new file mode 100644
index 0000000..b76d2c1
--- /dev/null
+++ b/config/lx2160a/LX2162-USOM/clearfog-s1_3-s2_0-dpl.dts
@@ -0,0 +1,138 @@
+/*
+ * Copyright 2020 NXP
+ * Copyright 2022 Josua Mayer <josua@solid-run.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+/ {
+ dpl-version = <10>;
+
+ containers {
+ dprc@1 {
+ compatible = "fsl,dprc";
+ parent = "none";
+ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_OBJ_CREATE_ALLOWED", "DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED";
+
+ objects {
+ obj_set@dpmac {
+ type = "dpmac";
+ ids = <0x3 0x4 0x5 0x6>;
+ };
+
+ obj_set@dpmcp {
+ type = "dpmcp";
+ ids = <0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23>;
+ };
+ };
+ };
+ };
+
+ objects {
+ /* Serdes 1 */
+ dpmac@3 {
+ };
+ dpmac@4 {
+ };
+ dpmac@5 {
+ };
+ dpmac@6 {
+ };
+
+ dpmcp@1 {
+ };
+ dpmcp@2 {
+ };
+ dpmcp@3 {
+ };
+ dpmcp@4 {
+ };
+ dpmcp@5 {
+ };
+ dpmcp@6 {
+ };
+ dpmcp@7 {
+ };
+ dpmcp@8 {
+ };
+ dpmcp@9 {
+ };
+ dpmcp@10 {
+ };
+ dpmcp@11 {
+ };
+ dpmcp@12 {
+ };
+ dpmcp@13 {
+ };
+ dpmcp@14 {
+ };
+ dpmcp@15 {
+ };
+ dpmcp@16 {
+ };
+ dpmcp@17 {
+ };
+ dpmcp@18 {
+ };
+ dpmcp@19 {
+ };
+ dpmcp@20 {
+ };
+ dpmcp@21 {
+ };
+ dpmcp@22 {
+ };
+ dpmcp@23 {
+ };
+ dpmcp@24 {
+ };
+ dpmcp@25 {
+ };
+ dpmcp@26 {
+ };
+ dpmcp@27 {
+ };
+ dpmcp@28 {
+ };
+ dpmcp@29 {
+ };
+ dpmcp@30 {
+ };
+ dpmcp@31 {
+ };
+ dpmcp@32 {
+ };
+ dpmcp@33 {
+ };
+ dpmcp@34 {
+ };
+ dpmcp@35 {
+ };
+ };
+
+ connections {
+ };
+};
diff --git a/config/lx2160a/LX2162-USOM/clearfog-s1_3-s2_9-dpc.dts b/config/lx2160a/LX2162-USOM/clearfog-s1_3-s2_9-dpc.dts
new file mode 100644
index 0000000..5aa4640
--- /dev/null
+++ b/config/lx2160a/LX2162-USOM/clearfog-s1_3-s2_9-dpc.dts
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2020 NXP
+ * Copyright 2022 Josua Mayer <josua@solid-run.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/ {
+ resources {
+ icid_pools {
+ icid_pool@1 {
+ num = <0x64>;
+ base_icid = <0x0>;
+ };
+ };
+ };
+
+ mc_general {
+ log {
+ mode = "LOG_MODE_ON";
+ level = "LOG_LEVEL_WARNING";
+ };
+
+ console {
+ mode = "CONSOLE_MODE_OFF";
+ uart_id = <0x4>;
+ level = "LOG_LEVEL_WARNING";
+ };
+ };
+
+ controllers {
+ qbman {
+ /* Transform this number of 8-WQ channels into four times
+ * as many 2-WQ channels. This allows the creation of a
+ * larger number of DPCONs.
+ */
+ wq_ch_conversion = <64>;
+ };
+ };
+
+ board_info {
+ recycle_ports {
+ recycle@1 {
+ max_rate = "1G";
+ };
+
+ recycle@2 {
+ max_rate = "1G";
+ };
+ };
+
+ ports {
+ /* Serdes 1 */
+ mac@3 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@4 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@5 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@6 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ /* Serdes 2 */
+ mac@11 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@12 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@13 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@14 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@15 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@16 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@17 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@18 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ };
+ };
+};
diff --git a/config/lx2160a/LX2162-USOM/clearfog-s1_3-s2_9-dpl.dts b/config/lx2160a/LX2162-USOM/clearfog-s1_3-s2_9-dpl.dts
new file mode 100644
index 0000000..efe1c60
--- /dev/null
+++ b/config/lx2160a/LX2162-USOM/clearfog-s1_3-s2_9-dpl.dts
@@ -0,0 +1,157 @@
+/*
+ * Copyright 2020 NXP
+ * Copyright 2022 Josua Mayer <josua@solid-run.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+/ {
+ dpl-version = <10>;
+
+ containers {
+ dprc@1 {
+ compatible = "fsl,dprc";
+ parent = "none";
+ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_OBJ_CREATE_ALLOWED", "DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED";
+
+ objects {
+ obj_set@dpmac {
+ type = "dpmac";
+ ids = <0x3 0x4 0x5 0x6 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12>;
+ };
+
+ /* 1x per dpni + 1x per dpmac */
+ obj_set@dpmcp {
+ type = "dpmcp";
+ ids = <0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23>;
+ };
+ };
+ };
+ };
+
+ objects {
+ /* Serdes 1 */
+ dpmac@3 {
+ };
+ dpmac@4 {
+ };
+ dpmac@5 {
+ };
+ dpmac@6 {
+ };
+
+ /* Serdes 2 */
+ dpmac@11 {
+ };
+ dpmac@12 {
+ };
+ dpmac@13 {
+ };
+ dpmac@14 {
+ };
+ dpmac@15 {
+ };
+ dpmac@16 {
+ };
+ dpmac@17 {
+ };
+ dpmac@18 {
+ };
+
+ dpmcp@1 {
+ };
+ dpmcp@2 {
+ };
+ dpmcp@3 {
+ };
+ dpmcp@4 {
+ };
+ dpmcp@5 {
+ };
+ dpmcp@6 {
+ };
+ dpmcp@7 {
+ };
+ dpmcp@8 {
+ };
+ dpmcp@9 {
+ };
+ dpmcp@10 {
+ };
+ dpmcp@11 {
+ };
+ dpmcp@12 {
+ };
+ dpmcp@13 {
+ };
+ dpmcp@14 {
+ };
+ dpmcp@15 {
+ };
+ dpmcp@16 {
+ };
+ dpmcp@17 {
+ };
+ dpmcp@18 {
+ };
+ dpmcp@19 {
+ };
+ dpmcp@20 {
+ };
+ dpmcp@21 {
+ };
+ dpmcp@22 {
+ };
+ dpmcp@23 {
+ };
+ dpmcp@24 {
+ };
+ dpmcp@25 {
+ };
+ dpmcp@26 {
+ };
+ dpmcp@27 {
+ };
+ dpmcp@28 {
+ };
+ dpmcp@29 {
+ };
+ dpmcp@30 {
+ };
+ dpmcp@31 {
+ };
+ dpmcp@32 {
+ };
+ dpmcp@33 {
+ };
+ dpmcp@34 {
+ };
+ dpmcp@35 {
+ };
+ };
+
+ connections {
+ };
+};
--
2.37.3
patches/rcw-LSDK-21.08/0022-lx2162som-add-configurations-for-Clearfog.patch 0 → 100644
View file @ bd2d3fd7
From 0302fb7f64a768d8dd20aeca7e790f739865fd90 Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Thu, 8 Sep 2022 12:37:58 +0300
Subject: [PATCH] lx2162som: add configurations for Clearfog
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
lx2160acex7/configs/lx2162a_clearfog.rcwi | 34 +++++++++++++++++++
.../configs/lx2162a_clearfog_SD1_0.rcwi | 20 +++++++++++
.../configs/lx2162a_clearfog_SD1_17.rcwi | 18 ++++++++++
.../configs/lx2162a_clearfog_SD1_18.rcwi | 18 ++++++++++
.../configs/lx2162a_clearfog_SD1_3.rcwi | 18 ++++++++++
.../configs/lx2162a_clearfog_SD2_0.rcwi | 20 +++++++++++
.../configs/lx2162a_clearfog_SD2_11.rcwi | 25 ++++++++++++++
.../configs/lx2162a_clearfog_SD2_7.rcwi | 25 ++++++++++++++
.../configs/lx2162a_clearfog_SD2_9.rcwi | 22 ++++++++++++
.../configs/lx2162a_clearfog_SD3_0.rcwi | 20 +++++++++++
10 files changed, 220 insertions(+)
create mode 100644 lx2160acex7/configs/lx2162a_clearfog.rcwi
create mode 100644 lx2160acex7/configs/lx2162a_clearfog_SD1_0.rcwi
create mode 100644 lx2160acex7/configs/lx2162a_clearfog_SD1_17.rcwi
create mode 100644 lx2160acex7/configs/lx2162a_clearfog_SD1_18.rcwi
create mode 100644 lx2160acex7/configs/lx2162a_clearfog_SD1_3.rcwi
create mode 100644 lx2160acex7/configs/lx2162a_clearfog_SD2_0.rcwi
create mode 100644 lx2160acex7/configs/lx2162a_clearfog_SD2_11.rcwi
create mode 100644 lx2160acex7/configs/lx2162a_clearfog_SD2_7.rcwi
create mode 100644 lx2160acex7/configs/lx2162a_clearfog_SD2_9.rcwi
create mode 100644 lx2160acex7/configs/lx2162a_clearfog_SD3_0.rcwi
diff --git a/lx2160acex7/configs/lx2162a_clearfog.rcwi b/lx2160acex7/configs/lx2162a_clearfog.rcwi
new file mode 100644
index 0000000..9dbae6e
--- /dev/null
+++ b/lx2160acex7/configs/lx2162a_clearfog.rcwi
@@ -0,0 +1,34 @@
+/* configure IIC1, IIC3, IIC5, IIC6 pins for i2c */
+IIC1_PMUX=0
+IIC3_PMUX=0
+IIC5_PMUX=0
+IIC6_PMUX=0
+
+/*
+ * Configure GPIOs:
+ * EVT0_B: GPIO3_DAT12 (SFP 25 upper LOS)
+ * EVT1_B: GPIO3_DAT13 (SFP 25 upper LED)
+ * EVT2_B: GPIO3_DAT14 (SFP 25 lower LED)
+ * EVT3_B: GPIO3_DAT15 (SFP 25 lower LOS)
+ * EVT4_B: GPIO3_DAT16 (SFP 10 lower LOS)
+ * PROC_IRQ0: GPIO3_DAT00
+ * PROC_IRQ1: GPIO3_DAT01 (SFP 10 upper LOS)
+ * PROC_IRQ2: GPIO3_DAT02
+ * PROC_IRQ3: GPIO3_DAT03
+ * PROC_IRQ4: GPIO3_DAT04
+ * PROC_IRQ5: GPIO3_DAT05 (SFP 10 lower LED)
+ * PROC_IRQ6: GPIO3_DAT06
+ * PROC_IRQ7: GPIO3_DAT07
+ * PROC_IRQ8: GPIO3_DAT08
+ * PROC_IRQ9: GPIO3_DAT09
+ * PROC_IRQ10: GPIO3_DAT10
+ * PROC_IRQ11: GPIO3_DAT11 (SFP 10 upper LED)
+ */
+EVT20_PMUX=1
+EVT43_PMUX=1
+IRQ03_00_PMUX=1
+IRQ07_04_PMUX=1
+IRQ11_08_PMUX=1
+
+/* Configure USB1 Pins for USB */
+USB_EXT_PMUX=0
diff --git a/lx2160acex7/configs/lx2162a_clearfog_SD1_0.rcwi b/lx2160acex7/configs/lx2162a_clearfog_SD1_0.rcwi
new file mode 100644
index 0000000..799e13e
--- /dev/null
+++ b/lx2160acex7/configs/lx2162a_clearfog_SD1_0.rcwi
@@ -0,0 +1,20 @@
+/* Serdes 1 Protocol 0: Disabled */
+SRDS_PRTCL_S1=0
+
+/* Disable Serdes 1 PLLF */
+SRDS_PLL_PD_PLL1=1
+
+/* Disable Serdes 1 PLLF reference clock */
+SRDS_REFCLKF_DIS_S1=1
+
+/* Don't use Serdes 1 PLLF as reference for PLLS */
+SRDS_INTRA_REF_CLK_S1=0
+
+/* Disable Serdes 1 PLLS */
+SRDS_PLL_PD_PLL2=1
+
+/*
+ * Select Serdes 1 PLL Default Fequencies (don't care)
+ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
+ */
+SRDS_PLL_REF_CLK_SEL_S1=0
diff --git a/lx2160acex7/configs/lx2162a_clearfog_SD1_17.rcwi b/lx2160acex7/configs/lx2162a_clearfog_SD1_17.rcwi
new file mode 100644
index 0000000..fec29d0
--- /dev/null
+++ b/lx2160acex7/configs/lx2162a_clearfog_SD1_17.rcwi
@@ -0,0 +1,18 @@
+/* Serdes 1 Protocol 17: 4x25Gbps */
+SRDS_PRTCL_S1=17
+
+/* Enable Serdes 1 PLLF */
+SRDS_PLL_PD_PLL1=0
+
+/* Don't use Serdes 1 PLLF as reference for PLLS */
+SRDS_INTRA_REF_CLK_S1=0
+
+/* Disable Serdes 1 PLLS */
+SRDS_PLL_PD_PLL2=1
+
+/*
+ * Select Serdes 1 PLLF frequency 161.1328125MHz (for 25G mode): Bit 0 = 0
+ * Select Serdes 1 PLLS frequency 100MHz (don't care, not documented in RM): Bit 1 = 0
+ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
+ */
+SRDS_PLL_REF_CLK_SEL_S1=0
diff --git a/lx2160acex7/configs/lx2162a_clearfog_SD1_18.rcwi b/lx2160acex7/configs/lx2162a_clearfog_SD1_18.rcwi
new file mode 100644
index 0000000..34c5be3
--- /dev/null
+++ b/lx2160acex7/configs/lx2162a_clearfog_SD1_18.rcwi
@@ -0,0 +1,18 @@
+/* Serdes 1 Protocol 18: 2x10Gbps + 2x25Gbps */
+SRDS_PRTCL_S1=18
+
+/* Enable Serdes 1 PLLF */
+SRDS_PLL_PD_PLL1=0
+
+/* Enable Serdes 1 PLLS */
+SRDS_PLL_PD_PLL2=0
+
+/* Use Serdes 1 PLLF for PLLS (LX2162A has no physical input for PLLS) */
+SRDS_INTRA_REF_CLK_S1=1
+
+/*
+ * Select Serdes 1 PLLF frequency 161.1328125MHz for 25GE mode (lanes 2+3): Bit 0 = 0
+ * Select Serdes 1 PLLS frequency 161.1328125MHz for 10GE mode (not documented in RM): Bit 1 = 1
+ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932)
+ */
+SRDS_PLL_REF_CLK_SEL_S1=2
diff --git a/lx2160acex7/configs/lx2162a_clearfog_SD1_3.rcwi b/lx2160acex7/configs/lx2162a_clearfog_SD1_3.rcwi
new file mode 100644
index 0000000..c7d3fd6
--- /dev/null
+++ b/lx2160acex7/configs/lx2162a_clearfog_SD1_3.rcwi
@@ -0,0 +1,18 @@
+/* Serdes 1 Protocol 3: 4x10Gbps */
+SRDS_PRTCL_S1=3
+
+/* Disable Serdes 1 PLLF */
+SRDS_PLL_PD_PLL1=1
+
+/* Use Serdes 1 PLLF for PLLS (LX2162A has no physical input for PLLS) */
+SRDS_INTRA_REF_CLK_S1=1
+
+/* Enable Serdes 1 PLLS */
+SRDS_PLL_PD_PLL2=0
+
+/*
+ * Select Serdes 1 PLLF frequency 100MHz (don't care): Bit 0 = 0
+ * Select Serdes 1 PLLS frequency 161.1328125MHz (not documented in RM): Bit 1 = 1
+ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
+ */
+SRDS_PLL_REF_CLK_SEL_S1=2
diff --git a/lx2160acex7/configs/lx2162a_clearfog_SD2_0.rcwi b/lx2160acex7/configs/lx2162a_clearfog_SD2_0.rcwi
new file mode 100644
index 0000000..8e0e0f9
--- /dev/null
+++ b/lx2160acex7/configs/lx2162a_clearfog_SD2_0.rcwi
@@ -0,0 +1,20 @@
+/* Serdes 2 Protocol 0: Disabled */
+SRDS_PRTCL_S2=0
+
+/* Disable Serdes 2 PLLF */
+SRDS_PLL_PD_PLL3=1
+
+/* Disable Serdes 2 PLLF reference clock */
+SRDS_REFCLKF_DIS_S2=1
+
+/* Don't use Serdes 2 PLLF as reference for PLLS */
+SRDS_INTRA_REF_CLK_S2=0
+
+/* Disable Serdes 2 PLLS */
+SRDS_PLL_PD_PLL4=1
+
+/*
+ * Select Serdes 2 PLL Default Fequencies (don't care)
+ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 934-935)
+ */
+SRDS_PLL_REF_CLK_SEL_S2=0
diff --git a/lx2160acex7/configs/lx2162a_clearfog_SD2_11.rcwi b/lx2160acex7/configs/lx2162a_clearfog_SD2_11.rcwi
new file mode 100644
index 0000000..cd7e9ba
--- /dev/null
+++ b/lx2160acex7/configs/lx2162a_clearfog_SD2_11.rcwi
@@ -0,0 +1,25 @@
+/* Serdes 2 Protocol 1: 6x1Gbps + 2x PCIe Gen. 3 x1 */
+SRDS_PRTCL_S2=11
+
+/* Enable Serdes 2 PLLF */
+SRDS_PLL_PD_PLL3=0
+
+/* Enable Serdes 2 PLLS */
+SRDS_PLL_PD_PLL4=0
+
+/* Use Serdes 2 PLLF for PLLS (to share PLLF 100MHz reference clock) */
+SRDS_INTRA_REF_CLK_S2=1
+
+/*
+ * Select Serdes 2 PLLF frequency 100MHz (Bit 0)
+ * Select Serdes 2 PLLS frequency 100MHz (Bit 1)
+ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 934-935)
+ */
+SRDS_PLL_REF_CLK_SEL_S2=0
+
+/* Configure Serdes 2 PCIe frequency divider for max. 8Gbps data rate */
+SRDS_DIV_PEX_S2=1
+
+/* Configure Ethernet Controllers 1+2 Pins as GPIOs to avoid competing for WRIO MACs 17+18 */
+EC1_PMUX=1
+EC2_PMUX=1
diff --git a/lx2160acex7/configs/lx2162a_clearfog_SD2_7.rcwi b/lx2160acex7/configs/lx2162a_clearfog_SD2_7.rcwi
new file mode 100644
index 0000000..dcd8dd1
--- /dev/null
+++ b/lx2160acex7/configs/lx2162a_clearfog_SD2_7.rcwi
@@ -0,0 +1,25 @@
+/* Serdes 2 Protocol 7: 4x1Gbps + 2x PCIe Gen. 2 x1 + 2x 10Gbps */
+SRDS_PRTCL_S2=7
+
+/* Enable Serdes 2 PLLF */
+SRDS_PLL_PD_PLL3=0
+
+/* Enable Serdes 2 PLLS */
+SRDS_PLL_PD_PLL4=0
+
+/* Don't use Serdes 2 PLLF for PLLS */
+SRDS_INTRA_REF_CLK_S2=0
+
+/*
+ * Select Serdes 2 PLLF frequency 100MHz for 1G (and pcie) mode: Bit 0 = 0
+ * Select Serdes 2 PLLS frequency 156.25MHz for 10G mode: Bit 1 = 0
+ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 934-935)
+ */
+SRDS_PLL_REF_CLK_SEL_S2=0
+
+/* Configure Serdes 2 PCIe frequency divider for max. 5Gbps data rate (gen 1+2) */
+SRDS_DIV_PEX_S2=2
+
+/* Configure Ethernet Controllers 1+2 Pins as GPIOs to avoid competing for WRIO MACs 17+18 */
+EC1_PMUX=1
+EC2_PMUX=1
diff --git a/lx2160acex7/configs/lx2162a_clearfog_SD2_9.rcwi b/lx2160acex7/configs/lx2162a_clearfog_SD2_9.rcwi
new file mode 100644
index 0000000..68728ba
--- /dev/null
+++ b/lx2160acex7/configs/lx2162a_clearfog_SD2_9.rcwi
@@ -0,0 +1,22 @@
+/* Serdes 2 Protocol 9: 8x1Gbps */
+SRDS_PRTCL_S2=9
+
+/* Disable Serdes 2 PLLF */
+SRDS_PLL_PD_PLL3=1
+
+/* Enable Serdes 2 PLLS */
+SRDS_PLL_PD_PLL4=0
+
+/* Use Serdes 2 PLLF for PLLS (to share PLLF 100MHz reference clock) */
+SRDS_INTRA_REF_CLK_S2=1
+
+/*
+ * Select Serdes 2 PLLF frequency 100MHz (don't care): Bit 0 = 0
+ * Select Serdes 2 PLLS frequency 100MHz for 1G mode: Bit 1 = 0
+ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 934-935)
+ */
+SRDS_PLL_REF_CLK_SEL_S2=0
+
+/* Configure Ethernet Controllers 1+2 Pins as GPIOs to avoid competing for WRIO MACs 17+18 */
+EC1_PMUX=1
+EC2_PMUX=1
diff --git a/lx2160acex7/configs/lx2162a_clearfog_SD3_0.rcwi b/lx2160acex7/configs/lx2162a_clearfog_SD3_0.rcwi
new file mode 100644
index 0000000..250437c
--- /dev/null
+++ b/lx2160acex7/configs/lx2162a_clearfog_SD3_0.rcwi
@@ -0,0 +1,20 @@
+/* Serdes 3 Protocol 0: Disabled */
+SRDS_PRTCL_S3=0
+
+/* Disable Serdes 3 PLLF */
+SRDS_PLL_PD_PLL5=1
+
+/* Disable Serdes 3 PLLF reference clock */
+SRDS_REFCLKF_DIS_S3=1
+
+/* Don't use Serdes 3 PLLF as reference for PLLS */
+SRDS_INTRA_REF_CLK_S3=0
+
+/* Disable Serdes 3 PLLS */
+SRDS_PLL_PD_PLL6=1
+
+/*
+ * Select Serdes 3 PLL Default Fequencies (don't care)
+ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 936-937)
+ */
+SRDS_PLL_REF_CLK_SEL_S3=0
--
2.37.3
runme.sh
View file @ bd2d3fd7
...@@ -110,6 +110,39 @@ case "${SERDES}" in ...@@ -110,6 +110,39 @@ case "${SERDES}" in
DPC=dpc-6x25g.dtb DPC=dpc-6x25g.dtb
DPL=dpl-eth.6x25g.21.dtb DPL=dpl-eth.6x25g.21.dtb
;; ;;
LX2162A_CLEARFOG_0_0_*)
DPC=LX2162-USOM/clearfog-s1_0-s2_0-dpc.dtb
DPL=LX2162-USOM/clearfog-s1_0-s2_0-dpl.dtb
DEFAULT_FDT_FILE="fsl-lx2162a-clearfog.dtb"
;;
LX2162A_CLEARFOG_0_7_*)
DPC=LX2162-USOM/clearfog-s1_0-s2_7-dpc.dtb
DPL=LX2162-USOM/clearfog-s1_0-s2_7-dpl.dtb
DEFAULT_FDT_FILE="fsl-lx2162a-clearfog.dtb"
MC_FORCE=patches/mc_10.28.100_lx2160a.itb
;;
LX2162A_CLEARFOG_0_9_*)
DPC=LX2162-USOM/clearfog-s1_0-s2_9-dpc.dtb
DPL=LX2162-USOM/clearfog-s1_0-s2_9-dpl.dtb
DEFAULT_FDT_FILE="fsl-lx2162a-clearfog.dtb"
MC_FORCE=patches/mc_10.28.100_lx2160a.itb
;;
LX2162A_CLEARFOG_0_11_*)
DPC=LX2162-USOM/clearfog-s1_0-s2_11-dpc.dtb
DPL=LX2162-USOM/clearfog-s1_0-s2_11-dpl.dtb
DEFAULT_FDT_FILE="fsl-lx2162a-clearfog.dtb"
MC_FORCE=patches/mc_10.28.100_lx2160a.itb
;;
LX2162A_CLEARFOG_3_0_*)
DPC=LX2162-USOM/clearfog-s1_3-s2_0-dpc.dtb
DPL=LX2162-USOM/clearfog-s1_3-s2_0-dpl.dtb
DEFAULT_FDT_FILE="fsl-lx2162a-clearfog.dtb"
;;
LX2162A_CLEARFOG_3_9_*)
DPC=LX2162-USOM/clearfog-s1_3-s2_9-dpc.dtb
DPL=LX2162-USOM/clearfog-s1_3-s2_9-dpl.dtb
DEFAULT_FDT_FILE="fsl-lx2162a-clearfog.dtb"
;;
*) *)
echo "Please define SERDES configuration" echo "Please define SERDES configuration"
exit -1 exit -1
...@@ -262,7 +295,7 @@ case "\$1" in ...@@ -262,7 +295,7 @@ case "\$1" in
echo "127.0.0.1 localhost" > /mnt/etc/hosts echo "127.0.0.1 localhost" > /mnt/etc/hosts
export DEBIAN_FRONTEND=noninteractive DEBCONF_NONINTERACTIVE_SEEN=true LC_ALL=C LANGUAGE=C LANG=C export DEBIAN_FRONTEND=noninteractive DEBCONF_NONINTERACTIVE_SEEN=true LC_ALL=C LANGUAGE=C LANG=C
chroot /mnt apt update chroot /mnt apt update
chroot /mnt apt install --no-install-recommends -y systemd-sysv apt locales less wget procps openssh-server ifupdown net-tools isc-dhcp-client ntpdate lm-sensors i2c-tools psmisc less sudo htop iproute2 iputils-ping kmod network-manager iptables rng-tools apt-utils chroot /mnt apt install --no-install-recommends -y systemd-sysv apt locales less wget procps openssh-server ifupdown net-tools isc-dhcp-client ntpdate lm-sensors i2c-tools psmisc less sudo htop iproute2 iputils-ping kmod network-manager iptables rng-tools apt-utils ethtool
echo -e "root\nroot" | chroot /mnt passwd echo -e "root\nroot" | chroot /mnt passwd
umount /mnt/var/lib/apt/ umount /mnt/var/lib/apt/
umount /mnt/var/cache/apt umount /mnt/var/cache/apt
...@@ -614,10 +647,16 @@ else ...@@ -614,10 +647,16 @@ else
fi fi
# DPAA2 DPL at 0x6800 # DPAA2 DPL at 0x6800
dd if=$ROOTDIR/build/mc-utils/config/lx2160a/CEX7/${DPL} of=images/${IMG} bs=512 seek=26624 conv=notrunc if [[ ! $DPL =~ / ]]; then
DPL="CEX7/$DPL"
fi
dd if=$ROOTDIR/build/mc-utils/config/lx2160a/${DPL} of=images/${IMG} bs=512 seek=26624 conv=notrunc
# DPAA2 DPC at 0x7000 # DPAA2 DPC at 0x7000
dd if=$ROOTDIR/build/mc-utils/config/lx2160a/CEX7/${DPC} of=images/${IMG} bs=512 seek=28672 conv=notrunc if [[ ! $DPC =~ / ]]; then
DPC="CEX7/$DPC"
fi
dd if=$ROOTDIR/build/mc-utils/config/lx2160a/${DPC} of=images/${IMG} bs=512 seek=28672 conv=notrunc
# Kernel at 0x8000 # Kernel at 0x8000
dd if=$ROOTDIR/build/linux/kernel-lx2160acex7.itb of=images/${IMG} bs=512 seek=32768 conv=notrunc dd if=$ROOTDIR/build/linux/kernel-lx2160acex7.itb of=images/${IMG} bs=512 seek=32768 conv=notrunc
......
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