Half-twins motherboard: fix dpmac.16 to dpmac.18

The issue is that dpmac.16 to dpmac.18 links up, but unable to
communicate thru those ports.
This patch series does -
1. Fix dpmac.17 phy-handle type since by default the dpmac is RGMII, and
in half-twins case it is thru SGMII.
2. Add to the build script the usage of MC firmware 10.28.100; which is
based on 10.28.1 that fixes the tx/rx thru dpmac.16, dpmac.17 and
dpmac.18. This firmware is only for LSDK-21.08 and will be fixed in
later LSDK releases with newer MC firmwares.
3. Limit recycle queues in the half twins DPC to 1G; this makes it
possible for dpmac.18 to be able to transmit
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>

patches/linux-LSDK-21.08/0013-arm64-dts-half-twins-fixed-typo-in-dpmac17-phy-handl.patch

+From e7defd76a8434247cb051fbec65a8e98c4843a8d Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Mon, 9 May 2022 10:36:28 +0300
+Subject: [PATCH 13/13] arm64: dts: half-twins: fixed typo in dpmac17
+ phy-handle propery removal
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts
+index ebde6c03f545..55d4bbb6caa2 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts
+@@ -412,7 +412,7 @@ &dpmac16 {
+ 	phys = <&serdes2_lane_f>;
+ };
+ &dpmac17 {
+-	/delete-property/ phy_handle;
++	/delete-property/ phy-handle;
+ 	/delete-property/ phy-connection-type;
+ 	sfp = <&c1_bb_sfp>;
+ 	managed = "in-band-status";
+-- 
+2.25.1
+

patches/mc-utils/0008-lx2160acex7-Limit-internal-MC-recycle-queues-to-1G.patch

+From 01a8324337bf15372c17f7cde7c508ddc4352fe4 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Mon, 9 May 2022 10:30:59 +0300
+Subject: [PATCH 8/8] lx2160acex7: Limit internal MC recycle queues to 1G
+
+This modification makes it possible to send packets thru dpmac.18
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ config/lx2160a/CEX7/dpc-8_x_usxgmii_8_x_sgmii.dts | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/config/lx2160a/CEX7/dpc-8_x_usxgmii_8_x_sgmii.dts b/config/lx2160a/CEX7/dpc-8_x_usxgmii_8_x_sgmii.dts
+index 354de30..55f07cc 100644
+--- a/config/lx2160a/CEX7/dpc-8_x_usxgmii_8_x_sgmii.dts
++++ b/config/lx2160a/CEX7/dpc-8_x_usxgmii_8_x_sgmii.dts
+@@ -70,6 +70,17 @@
+ 	};
+ 
+ 	board_info {
++
++		recycle_ports {
++			recycle@1 {
++				max_rate = "1G";
++			};
++
++			recycle@2 {
++				max_rate = "1G";
++			};
++		};
++
+ 		ports {
+ 			mac@3 {
+ 				link_type = "MAC_LINK_TYPE_PHY";
+-- 
+2.25.1
+

runme.sh

@@ -56,6 +56,10 @@ case "${SERDES}" in
 	8_9_*|8S_9_*)
 		DPC=dpc-8_x_usxgmii_8_x_sgmii.dtb
 		DPL=dpl-eth.8x10g.8x1g.dtb
+		# MC 10.28.1 is incapable of mapping all 16 dpnis. 10.28.100 fixes that
+		if [ "x$RELEASE" == "xLSDK-21.08" ]; then
+			MC_FORCE=patches/mc_10.28.100_lx2160a.itb
+		fi
 	;;
 	2_*)
 		DPC=dpc-8_x_usxgmii.dtb
@@ -573,8 +577,14 @@ if [ "x$RELEASE" == "xLSDK-20.04" ]; then
 	MC=mc_10.24.0_lx2160a.itb
 	dd if=$ROOTDIR/build/qoriq-mc-binary/lx2160a/${MC} of=images/${IMG} bs=512 seek=20480 conv=notrunc
 else
+	if [ "x$MC_FORCE" == "x" ]; then
 		MC=`ls $ROOTDIR/build/qoriq-mc-binary/lx216?a/ | grep -v sha256sum | cut -f1`
 		dd if=$ROOTDIR/build/qoriq-mc-binary/lx216xa/${MC} of=images/${IMG} bs=512 seek=20480 conv=notrunc
+	else
+		echo "Forcing MC firmware selection"
+		MC=$MC_FORCE
+		dd if=$ROOTDIR/$MC_FORCE of=images/${IMG} bs=512 seek=20480 conv=notrunc
+	fi
 fi
 
 # DPAA2 DPL at 0x6800