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Boxiang Sun
slapos
Commits
e2f8a932
Commit
e2f8a932
authored
Feb 22, 2023
by
Lu Xu
👀
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software/ors-amarisoft: add netconf configuration xml files
parent
0be0e1e8
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software/ors-amarisoft/netconf/CreateProcessingEle.jinja2.xml
...ware/ors-amarisoft/netconf/CreateProcessingEle.jinja2.xml
+11
-0
software/ors-amarisoft/netconf/cu_config.jinja2.xml
software/ors-amarisoft/netconf/cu_config.jinja2.xml
+128
-0
No files found.
software/ors-amarisoft/netconf/CreateProcessingEle.jinja2.xml
0 → 100644
View file @
e2f8a932
<config
xmlns=
"urn:ietf:params:xml:ns:netconf:base:1.0"
>
<processing-elements
xmlns=
"urn:o-ran:processing-element:1.0"
>
<transport-session-type>
CPRI-INTERFACE
</transport-session-type>
<ru-elements>
<name>
PE0
</name>
<transport-flow>
<interface-name>
eth1
</interface-name>
</transport-flow>
</ru-elements>
</processing-elements>
</config>
\ No newline at end of file
software/ors-amarisoft/netconf/cu_config.jinja2.xml
0 → 100644
View file @
e2f8a932
<config
xmlns=
"urn:ietf:params:xml:ns:netconf:base:1.0"
>
<user-plane-configuration
xmlns=
"urn:o-ran:uplane-conf:1.0"
>
<!-- low-level-t[r]x-links -->
<low-level-tx-links>
<name>
TXA0P00C00
</name>
<processing-element>
PE0
</processing-element>
<tx-array-carrier>
TXA0CC00
</tx-array-carrier>
<low-level-tx-endpoint>
TXA0P00C00
</low-level-tx-endpoint>
</low-level-tx-links>
<low-level-tx-links>
<name>
TXA0P01C00
</name>
<processing-element>
PE0
</processing-element>
<tx-array-carrier>
TXA0CC00
</tx-array-carrier>
<low-level-tx-endpoint>
TXA0P01C00
</low-level-tx-endpoint>
</low-level-tx-links>
<low-level-rx-links>
<name>
RXA0P00C00
</name>
<processing-element>
PE0
</processing-element>
<rx-array-carrier>
RXA0CC00
</rx-array-carrier>
<low-level-rx-endpoint>
RXA0P00C00
</low-level-rx-endpoint>
</low-level-rx-links>
<low-level-rx-links>
<name>
PRACH0P00C00
</name>
<processing-element>
PE0
</processing-element>
<rx-array-carrier>
RXA0CC00
</rx-array-carrier>
<low-level-rx-endpoint>
PRACH0P00C00
</low-level-rx-endpoint>
</low-level-rx-links>
<low-level-rx-links>
<name>
RXA0P01C00
</name>
<processing-element>
PE0
</processing-element>
<rx-array-carrier>
RXA0CC00
</rx-array-carrier>
<low-level-rx-endpoint>
RXA0P01C00
</low-level-rx-endpoint>
</low-level-rx-links>
<low-level-rx-links>
<name>
PRACH0P01C00
</name>
<processing-element>
PE0
</processing-element>
<rx-array-carrier>
RXA0CC00
</rx-array-carrier>
<low-level-rx-endpoint>
PRACH0P01C00
</low-level-rx-endpoint>
</low-level-rx-links>
<!-- low-level-t[r]x-endpoints -->
<low-level-tx-endpoints>
<name>
TXA0P00C00
</name>
<e-axcid>
<o-du-port-bitmask>
61440
</o-du-port-bitmask>
<band-sector-bitmask>
3968
</band-sector-bitmask>
<ccid-bitmask>
112
</ccid-bitmask>
<ru-port-bitmask>
15
</ru-port-bitmask>
<eaxc-id>
0
</eaxc-id>
</e-axcid>
</low-level-tx-endpoints>
<low-level-tx-endpoints>
<name>
TXA0P01C00
</name>
<e-axcid>
<o-du-port-bitmask>
61440
</o-du-port-bitmask>
<band-sector-bitmask>
3968
</band-sector-bitmask>
<ccid-bitmask>
112
</ccid-bitmask>
<ru-port-bitmask>
15
</ru-port-bitmask>
<eaxc-id>
1
</eaxc-id>
</e-axcid>
</low-level-tx-endpoints>
<low-level-rx-endpoints>
<name>
RXA0P00C00
</name>
<e-axcid>
<o-du-port-bitmask>
61440
</o-du-port-bitmask>
<band-sector-bitmask>
3968
</band-sector-bitmask>
<ccid-bitmask>
112
</ccid-bitmask>
<ru-port-bitmask>
15
</ru-port-bitmask>
<eaxc-id>
0
</eaxc-id>
</e-axcid>
</low-level-rx-endpoints>
<low-level-rx-endpoints>
<name>
PRACH0P00C00
</name>
<e-axcid>
<o-du-port-bitmask>
61440
</o-du-port-bitmask>
<band-sector-bitmask>
3968
</band-sector-bitmask>
<ccid-bitmask>
112
</ccid-bitmask>
<ru-port-bitmask>
15
</ru-port-bitmask>
<eaxc-id>
8
</eaxc-id>
</e-axcid>
</low-level-rx-endpoints>
<low-level-rx-endpoints>
<name>
RXA0P01C00
</name>
<e-axcid>
<o-du-port-bitmask>
61440
</o-du-port-bitmask>
<band-sector-bitmask>
3968
</band-sector-bitmask>
<ccid-bitmask>
112
</ccid-bitmask>
<ru-port-bitmask>
15
</ru-port-bitmask>
<eaxc-id>
1
</eaxc-id>
</e-axcid>
</low-level-rx-endpoints>
<low-level-rx-endpoints>
<name>
PRACH0P01C00
</name>
<e-axcid>
<o-du-port-bitmask>
61440
</o-du-port-bitmask>
<band-sector-bitmask>
3968
</band-sector-bitmask>
<ccid-bitmask>
112
</ccid-bitmask>
<ru-port-bitmask>
15
</ru-port-bitmask>
<eaxc-id>
9
</eaxc-id>
</e-axcid>
</low-level-rx-endpoints>
<!-- t[r]x-array-carriers -->
<tx-array-carriers>
<name>
TXA0CC00
</name>
<absolute-frequency-center>
300
</absolute-frequency-center>
<center-of-channel-bandwidth>
2140000000
</center-of-channel-bandwidth>
<channel-bandwidth>
20000000
</channel-bandwidth>
<active>
{{ slapparameter_dict.get('txa0cc00_active', 'ACTIVE') }}
</active>
<rw-duplex-scheme>
FDD
</rw-duplex-scheme>
<gain>
50
</gain>
<downlink-radio-frame-offset>
0
</downlink-radio-frame-offset>
<downlink-sfn-offset>
0
</downlink-sfn-offset>
</tx-array-carriers>
<rx-array-carriers>
<name>
RXA0CC00
</name>
<absolute-frequency-center>
18300
</absolute-frequency-center>
<center-of-channel-bandwidth>
1950000000
</center-of-channel-bandwidth>
<channel-bandwidth>
20000000
</channel-bandwidth>
<active>
{{ slapparameter_dict.get('rxa0cc00_active', 'ACTIVE') }}
</active>
<downlink-radio-frame-offset>
0
</downlink-radio-frame-offset>
<downlink-sfn-offset>
0
</downlink-sfn-offset>
<gain-correction>
0.0
</gain-correction>
<n-ta-offset>
0
</n-ta-offset>
</rx-array-carriers>
</user-plane-configuration>
</config>
\ No newline at end of file
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