hns_roce_device.h 33.6 KB
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/*
 * Copyright (c) 2016 Hisilicon Limited.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef _HNS_ROCE_DEVICE_H
#define _HNS_ROCE_DEVICE_H

#include <rdma/ib_verbs.h>
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#include <rdma/hns-abi.h>
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#include "hns_roce_debugfs.h"
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#define PCI_REVISION_ID_HIP08			0x21
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#define PCI_REVISION_ID_HIP09			0x30
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#define HNS_ROCE_MAX_MSG_LEN			0x80000000

#define HNS_ROCE_IB_MIN_SQ_STRIDE		6

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#define BA_BYTE_LEN				8

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#define HNS_ROCE_MIN_CQE_NUM			0x40
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#define HNS_ROCE_MIN_SRQ_WQE_NUM		1
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#define HNS_ROCE_MAX_IRQ_NUM			128
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#define HNS_ROCE_SGE_IN_WQE			2
#define HNS_ROCE_SGE_SHIFT			4

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#define EQ_ENABLE				1
#define EQ_DISABLE				0
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#define HNS_ROCE_CEQ				0
#define HNS_ROCE_AEQ				1

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#define HNS_ROCE_CEQE_SIZE 0x4
#define HNS_ROCE_AEQE_SIZE 0x10

#define HNS_ROCE_V3_EQE_SIZE 0x40
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#define HNS_ROCE_V2_CQE_SIZE 32
#define HNS_ROCE_V3_CQE_SIZE 64

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#define HNS_ROCE_V2_QPC_SZ 256
#define HNS_ROCE_V3_QPC_SZ 512

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#define HNS_ROCE_MAX_PORTS			6
#define HNS_ROCE_GID_SIZE			16
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#define HNS_ROCE_SGE_SIZE			16
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#define HNS_ROCE_DWQE_SIZE			65536
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#define HNS_ROCE_HOP_NUM_0			0xff

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#define MR_TYPE_MR				0x00
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#define MR_TYPE_FRMR				0x01
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#define MR_TYPE_DMA				0x03

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#define HNS_ROCE_FRMR_MAX_PA			512

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#define PKEY_ID					0xffff
#define NODE_DESC_SIZE				64
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#define DB_REG_OFFSET				0x1000
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/* Configure to HW for PAGE_SIZE larger than 4KB */
#define PG_SHIFT_OFFSET				(PAGE_SHIFT - 12)

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#define HNS_ROCE_IDX_QUE_ENTRY_SZ		4
#define SRQ_DB_REG				0x230

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#define HNS_ROCE_QP_BANK_NUM 8
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#define HNS_ROCE_CQ_BANK_NUM 4

#define CQ_BANKID_SHIFT 2
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#define CQ_BANKID_MASK GENMASK(1, 0)
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enum {
	SERV_TYPE_RC,
	SERV_TYPE_UC,
	SERV_TYPE_RD,
	SERV_TYPE_UD,
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	SERV_TYPE_XRC = 5,
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};

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enum hns_roce_event {
	HNS_ROCE_EVENT_TYPE_PATH_MIG                  = 0x01,
	HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED           = 0x02,
	HNS_ROCE_EVENT_TYPE_COMM_EST                  = 0x03,
	HNS_ROCE_EVENT_TYPE_SQ_DRAINED                = 0x04,
	HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR            = 0x05,
	HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR    = 0x06,
	HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR     = 0x07,
	HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH           = 0x08,
	HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH        = 0x09,
	HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR           = 0x0a,
	HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR           = 0x0b,
	HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW               = 0x0c,
	HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID             = 0x0d,
	HNS_ROCE_EVENT_TYPE_PORT_CHANGE               = 0x0f,
	/* 0x10 and 0x11 is unused in currently application case */
	HNS_ROCE_EVENT_TYPE_DB_OVERFLOW               = 0x12,
	HNS_ROCE_EVENT_TYPE_MB                        = 0x13,
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	HNS_ROCE_EVENT_TYPE_FLR			      = 0x15,
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	HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION	      = 0x16,
	HNS_ROCE_EVENT_TYPE_INVALID_XRCETH	      = 0x17,
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};

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enum {
	HNS_ROCE_CAP_FLAG_REREG_MR		= BIT(0),
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	HNS_ROCE_CAP_FLAG_ROCE_V1_V2		= BIT(1),
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	HNS_ROCE_CAP_FLAG_RQ_INLINE		= BIT(2),
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	HNS_ROCE_CAP_FLAG_CQ_RECORD_DB		= BIT(3),
	HNS_ROCE_CAP_FLAG_QP_RECORD_DB		= BIT(4),
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	HNS_ROCE_CAP_FLAG_SRQ			= BIT(5),
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	HNS_ROCE_CAP_FLAG_XRC			= BIT(6),
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	HNS_ROCE_CAP_FLAG_MW			= BIT(7),
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	HNS_ROCE_CAP_FLAG_FRMR                  = BIT(8),
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	HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL		= BIT(9),
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	HNS_ROCE_CAP_FLAG_ATOMIC		= BIT(10),
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	HNS_ROCE_CAP_FLAG_DIRECT_WQE		= BIT(12),
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	HNS_ROCE_CAP_FLAG_SDI_MODE		= BIT(14),
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	HNS_ROCE_CAP_FLAG_STASH			= BIT(17),
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	HNS_ROCE_CAP_FLAG_CQE_INLINE		= BIT(19),
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	HNS_ROCE_CAP_FLAG_SRQ_RECORD_DB         = BIT(22),
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};

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#define HNS_ROCE_DB_TYPE_COUNT			2
#define HNS_ROCE_DB_UNIT_SIZE			4

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enum {
	HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
};

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enum hns_roce_reset_stage {
	HNS_ROCE_STATE_NON_RST,
	HNS_ROCE_STATE_RST_BEF_DOWN,
	HNS_ROCE_STATE_RST_DOWN,
	HNS_ROCE_STATE_RST_UNINIT,
	HNS_ROCE_STATE_RST_INIT,
	HNS_ROCE_STATE_RST_INITED,
};

enum hns_roce_instance_state {
	HNS_ROCE_STATE_NON_INIT,
	HNS_ROCE_STATE_INIT,
	HNS_ROCE_STATE_INITED,
	HNS_ROCE_STATE_UNINIT,
};

enum {
	HNS_ROCE_RST_DIRECT_RETURN		= 0,
};

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#define HNS_ROCE_CMD_SUCCESS			1

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/* The minimum page size is 4K for hardware */
#define HNS_HW_PAGE_SHIFT			12
#define HNS_HW_PAGE_SIZE			(1 << HNS_HW_PAGE_SHIFT)
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struct hns_roce_uar {
	u64		pfn;
	unsigned long	index;
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	unsigned long	logic_idx;
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};

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enum hns_roce_mmap_type {
	HNS_ROCE_MMAP_TYPE_DB = 1,
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	HNS_ROCE_MMAP_TYPE_DWQE,
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};

struct hns_user_mmap_entry {
	struct rdma_user_mmap_entry rdma_entry;
	enum hns_roce_mmap_type mmap_type;
	u64 address;
};

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struct hns_roce_ucontext {
	struct ib_ucontext	ibucontext;
	struct hns_roce_uar	uar;
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	struct list_head	page_list;
	struct mutex		page_mutex;
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	struct hns_user_mmap_entry *db_mmap_entry;
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	u32			config;
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};

struct hns_roce_pd {
	struct ib_pd		ibpd;
	unsigned long		pdn;
};

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struct hns_roce_xrcd {
	struct ib_xrcd ibxrcd;
	u32 xrcdn;
};

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struct hns_roce_bitmap {
	/* Bitmap Traversal last a bit which is 1 */
	unsigned long		last;
	unsigned long		top;
	unsigned long		max;
	unsigned long		reserved_top;
	unsigned long		mask;
	spinlock_t		lock;
	unsigned long		*table;
};

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struct hns_roce_ida {
	struct ida ida;
	u32 min; /* Lowest ID to allocate.  */
	u32 max; /* Highest ID to allocate. */
};

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/* For Hardware Entry Memory */
struct hns_roce_hem_table {
	/* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
	u32		type;
	/* HEM array elment num */
	unsigned long	num_hem;
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	/* Single obj size */
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	unsigned long	obj_size;
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	unsigned long	table_chunk_size;
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	struct mutex	mutex;
	struct hns_roce_hem **hem;
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	u64		**bt_l1;
	dma_addr_t	*bt_l1_dma_addr;
	u64		**bt_l0;
	dma_addr_t	*bt_l0_dma_addr;
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};

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struct hns_roce_buf_region {
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	u32 offset; /* page offset */
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	u32 count; /* page count */
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	int hopnum; /* addressing hop num */
};

#define HNS_ROCE_MAX_BT_REGION	3
#define HNS_ROCE_MAX_BT_LEVEL	3
struct hns_roce_hem_list {
	struct list_head root_bt;
	/* link all bt dma mem by hop config */
	struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL];
	struct list_head btm_bt; /* link all bottom bt in @mid_bt */
	dma_addr_t root_ba; /* pointer to the root ba table */
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};

struct hns_roce_buf_attr {
	struct {
		size_t	size;  /* region size */
		int	hopnum; /* multi-hop addressing hop num */
	} region[HNS_ROCE_MAX_BT_REGION];
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	unsigned int region_count; /* valid region count */
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	unsigned int page_shift;  /* buffer page shift */
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	unsigned int user_access; /* umem access flag */
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	bool mtt_only; /* only alloc buffer-required MTT memory */
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};

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struct hns_roce_hem_cfg {
	dma_addr_t	root_ba; /* root BA table's address */
	bool		is_direct; /* addressing without BA table */
	unsigned int	ba_pg_shift; /* BA table page shift */
	unsigned int	buf_pg_shift; /* buffer page shift */
	unsigned int	buf_pg_count;  /* buffer page count */
	struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION];
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	unsigned int	region_count;
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};

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/* memory translate region */
struct hns_roce_mtr {
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	struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */
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	struct ib_umem		*umem; /* user space buffer */
	struct hns_roce_buf	*kmem; /* kernel space buffer */
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	struct hns_roce_hem_cfg  hem_cfg; /* config for hardware addressing */
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};

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struct hns_roce_mw {
	struct ib_mw		ibmw;
	u32			pdn;
	u32			rkey;
	int			enabled; /* MW's active status */
	u32			pbl_hop_num;
	u32			pbl_ba_pg_sz;
	u32			pbl_buf_pg_sz;
};

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struct hns_roce_mr {
	struct ib_mr		ibmr;
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	u64			iova; /* MR's virtual original addr */
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	u64			size; /* Address range of MR */
	u32			key; /* Key of MR */
	u32			pd;   /* PD num of MR */
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	u32			access; /* Access permission of MR */
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	int			enabled; /* MR's active status */
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	int			type; /* MR's register type */
	u32			pbl_hop_num; /* multi-hop number */
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	struct hns_roce_mtr	pbl_mtr;
	u32			npages;
	dma_addr_t		*page_list;
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};

struct hns_roce_mr_table {
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	struct hns_roce_ida mtpt_ida;
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	struct hns_roce_hem_table	mtpt_table;
};

struct hns_roce_wq {
	u64		*wrid;     /* Work request ID */
	spinlock_t	lock;
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	u32		wqe_cnt;  /* WQE num */
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	u32		max_gs;
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	u32		rsv_sge;
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	u32		offset;
	u32		wqe_shift; /* WQE size */
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	u32		head;
	u32		tail;
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	void __iomem	*db_reg;
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	u32		ext_sge_cnt;
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};

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struct hns_roce_sge {
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	unsigned int	sge_cnt; /* SGE num */
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	u32		offset;
	u32		sge_shift; /* SGE size */
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};

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struct hns_roce_buf_list {
	void		*buf;
	dma_addr_t	map;
};

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/*
 * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous
 * dma address range.
 *
 * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep.
 *
 * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even
 * the allocated size is smaller than the required size.
 */
enum {
	HNS_ROCE_BUF_DIRECT = BIT(0),
	HNS_ROCE_BUF_NOSLEEP = BIT(1),
	HNS_ROCE_BUF_NOFAIL = BIT(2),
};

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struct hns_roce_buf {
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	struct hns_roce_buf_list	*trunk_list;
	u32				ntrunks;
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	u32				npages;
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	unsigned int			trunk_shift;
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	unsigned int			page_shift;
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};

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struct hns_roce_db_pgdir {
	struct list_head	list;
	DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
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	DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT);
	unsigned long		*bits[HNS_ROCE_DB_TYPE_COUNT];
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	u32			*page;
	dma_addr_t		db_dma;
};

struct hns_roce_user_db_page {
	struct list_head	list;
	struct ib_umem		*umem;
	unsigned long		user_virt;
	refcount_t		refcount;
};

struct hns_roce_db {
	u32		*db_record;
	union {
		struct hns_roce_db_pgdir *pgdir;
		struct hns_roce_user_db_page *user_page;
	} u;
	dma_addr_t	dma;
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	void		*virt_addr;
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	unsigned long	index;
	unsigned long	order;
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};

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struct hns_roce_cq {
	struct ib_cq			ib_cq;
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	struct hns_roce_mtr		mtr;
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	struct hns_roce_db		db;
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	u32				flags;
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	spinlock_t			lock;
	u32				cq_depth;
	u32				cons_index;
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	u32				*set_ci_db;
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	void __iomem			*db_reg;
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	int				arm_sn;
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	int				cqe_size;
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	unsigned long			cqn;
	u32				vector;
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	refcount_t			refcount;
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	struct completion		free;
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	struct list_head		sq_list; /* all qps on this send cq */
	struct list_head		rq_list; /* all qps on this recv cq */
	int				is_armed; /* cq is armed */
	struct list_head		node; /* all armed cqs are on a list */
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};

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struct hns_roce_idx_que {
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	struct hns_roce_mtr		mtr;
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	u32				entry_shift;
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	unsigned long			*bitmap;
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	u32				head;
	u32				tail;
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};

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struct hns_roce_srq {
	struct ib_srq		ibsrq;
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	unsigned long		srqn;
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	u32			wqe_cnt;
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	int			max_gs;
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	u32			rsv_sge;
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	u32			wqe_shift;
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	u32			cqn;
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	u32			xrcdn;
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	void __iomem		*db_reg;
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	refcount_t		refcount;
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	struct completion	free;

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	struct hns_roce_mtr	buf_mtr;

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	u64		       *wrid;
	struct hns_roce_idx_que idx_que;
	spinlock_t		lock;
	struct mutex		mutex;
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	void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event);
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	struct hns_roce_db	rdb;
	u32			cap_flags;
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};

struct hns_roce_uar_table {
	struct hns_roce_bitmap bitmap;
};

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struct hns_roce_bank {
	struct ida ida;
	u32 inuse; /* Number of IDs allocated */
	u32 min; /* Lowest ID to allocate.  */
	u32 max; /* Highest ID to allocate. */
	u32 next; /* Next ID to allocate. */
};

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struct hns_roce_idx_table {
	u32 *spare_idx;
	u32 head;
	u32 tail;
};

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struct hns_roce_qp_table {
	struct hns_roce_hem_table	qp_table;
	struct hns_roce_hem_table	irrl_table;
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	struct hns_roce_hem_table	trrl_table;
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	struct hns_roce_hem_table	sccc_table;
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	struct mutex			scc_mutex;
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	struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM];
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	struct mutex bank_mutex;
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	struct hns_roce_idx_table	idx_table;
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};

struct hns_roce_cq_table {
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	struct xarray			array;
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	struct hns_roce_hem_table	table;
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	struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM];
	struct mutex			bank_mutex;
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};

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struct hns_roce_srq_table {
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	struct hns_roce_ida		srq_ida;
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	struct xarray			xa;
	struct hns_roce_hem_table	table;
};

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struct hns_roce_av {
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	u8 port;
	u8 gid_index;
	u8 stat_rate;
	u8 hop_limit;
	u32 flowlabel;
	u16 udp_sport;
	u8 sl;
	u8 tclass;
	u8 dgid[HNS_ROCE_GID_SIZE];
	u8 mac[ETH_ALEN];
	u16 vlan_id;
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	u8 vlan_en;
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};

struct hns_roce_ah {
	struct ib_ah		ibah;
	struct hns_roce_av	av;
};

struct hns_roce_cmd_context {
	struct completion	done;
	int			result;
	int			next;
	u64			out_param;
	u16			token;
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	u16			busy;
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};

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enum hns_roce_cmdq_state {
	HNS_ROCE_CMDQ_STATE_NORMAL,
	HNS_ROCE_CMDQ_STATE_FATAL_ERR,
};

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struct hns_roce_cmdq {
	struct dma_pool		*pool;
	struct semaphore	poll_sem;
	/*
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	 * Event mode: cmd register mutex protection,
	 * ensure to not exceed max_cmds and user use limit region
	 */
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	struct semaphore	event_sem;
	int			max_cmds;
	spinlock_t		context_lock;
	int			free_head;
	struct hns_roce_cmd_context *context;
	/*
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	 * Process whether use event mode, init default non-zero
	 * After the event queue of cmd event ready,
	 * can switch into event mode
	 * close device, switch into poll mode(non event mode)
	 */
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	u8			use_events;
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	enum hns_roce_cmdq_state state;
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};

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struct hns_roce_cmd_mailbox {
	void		       *buf;
	dma_addr_t		dma;
};

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struct hns_roce_mbox_msg {
	u64 in_param;
	u64 out_param;
	u8 cmd;
	u32 tag;
	u16 token;
	u8 event_en;
};

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struct hns_roce_dev;

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enum {
	HNS_ROCE_FLUSH_FLAG = 0,
};

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struct hns_roce_work {
	struct hns_roce_dev *hr_dev;
	struct work_struct work;
	int event_type;
	int sub_type;
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	u32 queue_num;
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};

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struct hns_roce_qp {
	struct ib_qp		ibqp;
	struct hns_roce_wq	rq;
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	struct hns_roce_db	rdb;
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	struct hns_roce_db	sdb;
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	unsigned long		en_flags;
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	enum ib_sig_type	sq_signal_bits;
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	struct hns_roce_wq	sq;

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	struct hns_roce_mtr	mtr;

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	u32			buff_size;
	struct mutex		mutex;
	u8			port;
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	u8			phy_port;
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	u8			sl;
	u8			resp_depth;
	u8			state;
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	u32                     atomic_rd_en;
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	u32			qkey;
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	void			(*event)(struct hns_roce_qp *qp,
					 enum hns_roce_event event_type);
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	unsigned long		qpn;

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	u32			xrcdn;

614
	refcount_t		refcount;
615
	struct completion	free;
616 617 618

	struct hns_roce_sge	sge;
	u32			next_sge;
619 620
	enum ib_mtu		path_mtu;
	u32			max_inline_data;
621
	u8			free_mr_en;
622

623 624
	/* 0: flush needed, 1: unneeded */
	unsigned long		flush_flag;
625
	struct hns_roce_work	flush_work;
626 627 628
	struct list_head	node; /* all qps are on a list */
	struct list_head	rq_node; /* all recv qps are on a list */
	struct list_head	sq_node; /* all send qps are on a list */
629
	struct hns_user_mmap_entry *dwqe_mmap_entry;
630
	u32			config;
631 632 633 634 635 636 637 638 639
};

struct hns_roce_ib_iboe {
	spinlock_t		lock;
	struct net_device      *netdevs[HNS_ROCE_MAX_PORTS];
	struct notifier_block	nb;
	u8			phy_port[HNS_ROCE_MAX_PORTS];
};

640
struct hns_roce_ceqe {
641 642
	__le32	comp;
	__le32	rsv[15];
643 644
};

645 646 647 648 649
#define CEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_ceqe, h, l)

#define CEQE_CQN CEQE_FIELD_LOC(23, 0)
#define CEQE_OWNER CEQE_FIELD_LOC(31, 31)

650
struct hns_roce_aeqe {
651
	__le32 asyn;
652 653
	union {
		struct {
654
			__le32 num;
655 656
			u32 rsv0;
			u32 rsv1;
657
		} queue_event;
658 659 660 661 662 663 664 665

		struct {
			__le64  out_param;
			__le16  token;
			u8	status;
			u8	rsv0;
		} __packed cmd;
	 } event;
666
	__le32 rsv[12];
667 668
};

669 670 671 672 673 674 675
#define AEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_aeqe, h, l)

#define AEQE_EVENT_TYPE AEQE_FIELD_LOC(7, 0)
#define AEQE_SUB_TYPE AEQE_FIELD_LOC(15, 8)
#define AEQE_OWNER AEQE_FIELD_LOC(31, 31)
#define AEQE_EVENT_QUEUE_NUM AEQE_FIELD_LOC(55, 32)

676 677
struct hns_roce_eq {
	struct hns_roce_dev		*hr_dev;
678
	void __iomem			*db_reg;
679

680
	int				type_flag; /* Aeq:1 ceq:0 */
681 682 683 684
	int				eqn;
	u32				entries;
	int				eqe_size;
	int				irq;
685
	u32				cons_index;
686 687 688 689
	int				over_ignore;
	int				coalesce;
	int				arm_st;
	int				hop_num;
690
	struct hns_roce_mtr		mtr;
691
	u16				eq_max_cnt;
692
	u32				eq_period;
693
	int				shift;
694 695
	int				event_type;
	int				sub_type;
696 697 698 699 700 701
};

struct hns_roce_eq_table {
	struct hns_roce_eq	*eq;
};

702 703 704 705 706 707 708
enum cong_type {
	CONG_TYPE_DCQCN,
	CONG_TYPE_LDCP,
	CONG_TYPE_HC3,
	CONG_TYPE_DIP,
};

709
struct hns_roce_caps {
710
	u64		fw_ver;
711 712 713 714 715 716
	u8		num_ports;
	int		gid_table_len[HNS_ROCE_MAX_PORTS];
	int		pkey_table_len[HNS_ROCE_MAX_PORTS];
	int		local_ca_ack_delay;
	int		num_uars;
	u32		phy_num_uars;
717 718 719
	u32		max_sq_sg;
	u32		max_sq_inline;
	u32		max_rq_sg;
720
	u32		rsv0;
721 722
	u32		num_qps;
	u32		reserved_qps;
723
	u32		num_srqs;
724
	u32		max_wqes;
725 726
	u32		max_srq_wrs;
	u32		max_srq_sges;
727 728
	u32		max_sq_desc_sz;
	u32		max_rq_desc_sz;
729
	u32		rsv2;
730 731
	int		max_qp_init_rdma;
	int		max_qp_dest_rdma;
732
	u32		num_cqs;
733 734
	u32		max_cqes;
	u32		min_cqes;
735
	u32		min_wqes;
736
	u32		reserved_cqs;
737
	u32		reserved_srqs;
738
	int		num_aeq_vectors;
739
	int		num_comp_vectors;
740
	int		num_other_vectors;
741
	u32		num_mtpts;
742
	u32		rsv1;
743 744
	u32		num_srqwqe_segs;
	u32		num_idx_segs;
745 746 747 748
	int		reserved_mrws;
	int		reserved_uars;
	int		num_pds;
	int		reserved_pds;
749 750
	u32		num_xrcds;
	u32		reserved_xrcds;
751
	u32		mtt_entry_sz;
752
	u32		cqe_sz;
753 754 755
	u32		page_size_cap;
	u32		reserved_lkey;
	int		mtpt_entry_sz;
756
	int		qpc_sz;
757
	int		irrl_entry_sz;
758
	int		trrl_entry_sz;
759
	int		cqc_entry_sz;
760
	int		sccc_sz;
761 762
	int		qpc_timer_entry_sz;
	int		cqc_timer_entry_sz;
763 764
	int		srqc_entry_sz;
	int		idx_entry_sz;
765 766 767
	u32		pbl_ba_pg_sz;
	u32		pbl_buf_pg_sz;
	u32		pbl_hop_num;
768
	int		aeqe_depth;
769
	int		ceqe_depth;
770 771
	u32		aeqe_size;
	u32		ceqe_size;
772
	enum ib_mtu	max_mtu;
773
	u32		qpc_bt_num;
774
	u32		qpc_timer_bt_num;
775 776
	u32		srqc_bt_num;
	u32		cqc_bt_num;
777
	u32		cqc_timer_bt_num;
778
	u32		mpt_bt_num;
779 780 781
	u32		eqc_bt_num;
	u32		smac_bt_num;
	u32		sgid_bt_num;
782
	u32		sccc_bt_num;
783
	u32		gmv_bt_num;
784 785 786 787 788 789 790 791 792 793 794 795
	u32		qpc_ba_pg_sz;
	u32		qpc_buf_pg_sz;
	u32		qpc_hop_num;
	u32		srqc_ba_pg_sz;
	u32		srqc_buf_pg_sz;
	u32		srqc_hop_num;
	u32		cqc_ba_pg_sz;
	u32		cqc_buf_pg_sz;
	u32		cqc_hop_num;
	u32		mpt_ba_pg_sz;
	u32		mpt_buf_pg_sz;
	u32		mpt_hop_num;
796 797 798
	u32		mtt_ba_pg_sz;
	u32		mtt_buf_pg_sz;
	u32		mtt_hop_num;
799 800 801
	u32		wqe_sq_hop_num;
	u32		wqe_sge_hop_num;
	u32		wqe_rq_hop_num;
802 803 804
	u32		sccc_ba_pg_sz;
	u32		sccc_buf_pg_sz;
	u32		sccc_hop_num;
805 806 807 808 809 810
	u32		qpc_timer_ba_pg_sz;
	u32		qpc_timer_buf_pg_sz;
	u32		qpc_timer_hop_num;
	u32		cqc_timer_ba_pg_sz;
	u32		cqc_timer_buf_pg_sz;
	u32		cqc_timer_hop_num;
811
	u32		cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */
812 813
	u32		cqe_buf_pg_sz;
	u32		cqe_hop_num;
814 815 816 817 818 819
	u32		srqwqe_ba_pg_sz;
	u32		srqwqe_buf_pg_sz;
	u32		srqwqe_hop_num;
	u32		idx_ba_pg_sz;
	u32		idx_buf_pg_sz;
	u32		idx_hop_num;
820 821 822
	u32		eqe_ba_pg_sz;
	u32		eqe_buf_pg_sz;
	u32		eqe_hop_num;
823 824 825 826 827
	u32		gmv_entry_num;
	u32		gmv_entry_sz;
	u32		gmv_ba_pg_sz;
	u32		gmv_buf_pg_sz;
	u32		gmv_hop_num;
828
	u32		sl_num;
829
	u32		llm_buf_pg_sz;
830
	u32		chunk_sz; /* chunk size in non multihop mode */
831
	u64		flags;
832 833 834 835 836 837
	u16		default_ceq_max_cnt;
	u16		default_ceq_period;
	u16		default_aeq_max_cnt;
	u16		default_aeq_period;
	u16		default_aeq_arm_st;
	u16		default_ceq_arm_st;
838
	enum cong_type	cong_type;
839 840
};

841 842 843 844 845 846
enum hns_roce_device_state {
	HNS_ROCE_DEVICE_STATE_INITED,
	HNS_ROCE_DEVICE_STATE_RST_DOWN,
	HNS_ROCE_DEVICE_STATE_UNINIT,
};

847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872
enum hns_roce_hw_pkt_stat_index {
	HNS_ROCE_HW_RX_RC_PKT_CNT,
	HNS_ROCE_HW_RX_UC_PKT_CNT,
	HNS_ROCE_HW_RX_UD_PKT_CNT,
	HNS_ROCE_HW_RX_XRC_PKT_CNT,
	HNS_ROCE_HW_RX_PKT_CNT,
	HNS_ROCE_HW_RX_ERR_PKT_CNT,
	HNS_ROCE_HW_RX_CNP_PKT_CNT,
	HNS_ROCE_HW_TX_RC_PKT_CNT,
	HNS_ROCE_HW_TX_UC_PKT_CNT,
	HNS_ROCE_HW_TX_UD_PKT_CNT,
	HNS_ROCE_HW_TX_XRC_PKT_CNT,
	HNS_ROCE_HW_TX_PKT_CNT,
	HNS_ROCE_HW_TX_ERR_PKT_CNT,
	HNS_ROCE_HW_TX_CNP_PKT_CNT,
	HNS_ROCE_HW_TRP_GET_MPT_ERR_PKT_CNT,
	HNS_ROCE_HW_TRP_GET_IRRL_ERR_PKT_CNT,
	HNS_ROCE_HW_ECN_DB_CNT,
	HNS_ROCE_HW_RX_BUF_CNT,
	HNS_ROCE_HW_TRP_RX_SOF_CNT,
	HNS_ROCE_HW_CQ_CQE_CNT,
	HNS_ROCE_HW_CQ_POE_CNT,
	HNS_ROCE_HW_CQ_NOTIFY_CNT,
	HNS_ROCE_HW_CNT_TOTAL
};

873
struct hns_roce_hw {
874 875
	int (*cmq_init)(struct hns_roce_dev *hr_dev);
	void (*cmq_exit)(struct hns_roce_dev *hr_dev);
876
	int (*hw_profile)(struct hns_roce_dev *hr_dev);
877 878
	int (*hw_init)(struct hns_roce_dev *hr_dev);
	void (*hw_exit)(struct hns_roce_dev *hr_dev);
879 880
	int (*post_mbox)(struct hns_roce_dev *hr_dev,
			 struct hns_roce_mbox_msg *mbox_msg);
881
	int (*poll_mbox_done)(struct hns_roce_dev *hr_dev);
882
	bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy);
883
	int (*set_gid)(struct hns_roce_dev *hr_dev, int gid_index,
884
		       const union ib_gid *gid, const struct ib_gid_attr *attr);
885 886
	int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port,
		       const u8 *addr);
887
	int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
888
			  struct hns_roce_mr *mr);
889
	int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
890
				struct hns_roce_mr *mr, int flags,
891
				void *mb_buf);
892 893
	int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
			       struct hns_roce_mr *mr);
894
	int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw);
895 896
	void (*write_cqc)(struct hns_roce_dev *hr_dev,
			  struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
897
			  dma_addr_t dma_handle);
898
	int (*set_hem)(struct hns_roce_dev *hr_dev,
899
		       struct hns_roce_hem_table *table, int obj, u32 step_idx);
900
	int (*clear_hem)(struct hns_roce_dev *hr_dev,
901
			 struct hns_roce_hem_table *table, int obj,
902
			 u32 step_idx);
903 904
	int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
			 int attr_mask, enum ib_qp_state cur_state,
905
			 enum ib_qp_state new_state, struct ib_udata *udata);
906 907
	int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev,
			 struct hns_roce_qp *hr_qp);
908
	void (*dereg_mr)(struct hns_roce_dev *hr_dev);
909 910
	int (*init_eq)(struct hns_roce_dev *hr_dev);
	void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
911
	int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf);
912
	int (*query_cqc)(struct hns_roce_dev *hr_dev, u32 cqn, void *buffer);
913
	int (*query_qpc)(struct hns_roce_dev *hr_dev, u32 qpn, void *buffer);
914
	int (*query_mpt)(struct hns_roce_dev *hr_dev, u32 key, void *buffer);
915
	int (*query_srqc)(struct hns_roce_dev *hr_dev, u32 srqn, void *buffer);
916 917
	int (*query_hw_counter)(struct hns_roce_dev *hr_dev,
				u64 *stats, u32 port, int *hw_counters);
918 919
	const struct ib_device_ops *hns_roce_dev_ops;
	const struct ib_device_ops *hns_roce_dev_srq_ops;
920 921 922 923
};

struct hns_roce_dev {
	struct ib_device	ib_dev;
924 925
	struct pci_dev		*pci_dev;
	struct device		*dev;
926
	struct hns_roce_uar     priv_uar;
927
	const char		*irq_names[HNS_ROCE_MAX_IRQ_NUM];
928
	spinlock_t		sm_lock;
929 930
	bool			active;
	bool			is_reset;
931
	bool			dis_db;
932
	unsigned long		reset_cnt;
933
	struct hns_roce_ib_iboe iboe;
934 935 936
	enum hns_roce_device_state state;
	struct list_head	qp_list; /* list of all qps on this dev */
	spinlock_t		qp_list_lock; /* protect qp_list */
937 938
	struct list_head	dip_list; /* list of all dest ips on this dev */
	spinlock_t		dip_list_lock; /* protect dip_list */
939

940 941
	struct list_head        pgdir_list;
	struct mutex            pgdir_mutex;
942 943
	int			irq[HNS_ROCE_MAX_IRQ_NUM];
	u8 __iomem		*reg_base;
944
	void __iomem		*mem_base;
945
	struct hns_roce_caps	caps;
946
	struct xarray		qp_table_xa;
947

948
	unsigned char	dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN];
949 950 951 952 953 954 955
	u64			sys_image_guid;
	u32                     vendor_id;
	u32                     vendor_part_id;
	u32                     hw_rev;
	void __iomem            *priv_addr;

	struct hns_roce_cmdq	cmd;
956
	struct hns_roce_ida pd_ida;
957
	struct hns_roce_ida xrcd_ida;
958
	struct hns_roce_ida uar_ida;
959 960
	struct hns_roce_mr_table  mr_table;
	struct hns_roce_cq_table  cq_table;
961
	struct hns_roce_srq_table srq_table;
962 963
	struct hns_roce_qp_table  qp_table;
	struct hns_roce_eq_table  eq_table;
964 965
	struct hns_roce_hem_table  qpc_timer_table;
	struct hns_roce_hem_table  cqc_timer_table;
966 967 968 969
	/* GMV is the memory area that the driver allocates for the hardware
	 * to store SGID, SMAC and VLAN information.
	 */
	struct hns_roce_hem_table  gmv_table;
970 971 972

	int			cmd_mod;
	int			loop_idc;
973 974
	u32			sdb_offset;
	u32			odb_offset;
975
	const struct hns_roce_hw *hw;
976
	void			*priv;
977
	struct workqueue_struct *irq_workq;
978
	struct work_struct ecc_work;
979
	u32 func_num;
980
	u32 is_vf;
981
	u32 cong_algo_tmpl_id;
982
	u64 dwqe_page;
983
	struct hns_roce_dev_debugfs dbgfs;
984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001
};

static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
{
	return container_of(ib_dev, struct hns_roce_dev, ib_dev);
}

static inline struct hns_roce_ucontext
			*to_hr_ucontext(struct ib_ucontext *ibucontext)
{
	return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
}

static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
{
	return container_of(ibpd, struct hns_roce_pd, ibpd);
}

1002 1003 1004 1005 1006
static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd)
{
	return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd);
}

1007 1008 1009 1010 1011 1012 1013 1014 1015 1016
static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
{
	return container_of(ibah, struct hns_roce_ah, ibah);
}

static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
{
	return container_of(ibmr, struct hns_roce_mr, ibmr);
}

1017 1018 1019 1020 1021
static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw)
{
	return container_of(ibmw, struct hns_roce_mw, ibmw);
}

1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036
static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
{
	return container_of(ibqp, struct hns_roce_qp, ibqp);
}

static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
{
	return container_of(ib_cq, struct hns_roce_cq, ib_cq);
}

static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
{
	return container_of(ibsrq, struct hns_roce_srq, ibsrq);
}

1037 1038 1039 1040 1041 1042
static inline struct hns_user_mmap_entry *
to_hns_mmap(struct rdma_user_mmap_entry *rdma_entry)
{
	return container_of(rdma_entry, struct hns_user_mmap_entry, rdma_entry);
}

1043
static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
1044
{
1045
	writeq(*(u64 *)val, dest);
1046 1047 1048 1049 1050
}

static inline struct hns_roce_qp
	*__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
{
1051
	return xa_load(&hr_dev->qp_table_xa, qpn);
1052 1053
}

1054 1055
static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf,
					unsigned int offset)
1056
{
1057 1058
	return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) +
			(offset & ((1 << buf->trunk_shift) - 1));
1059 1060
}

1061 1062
static inline dma_addr_t hns_roce_buf_dma_addr(struct hns_roce_buf *buf,
					       unsigned int offset)
1063
{
1064 1065
	return buf->trunk_list[offset >> buf->trunk_shift].map +
			(offset & ((1 << buf->trunk_shift) - 1));
1066 1067
}

1068 1069 1070 1071 1072
static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx)
{
	return hns_roce_buf_dma_addr(buf, idx << buf->page_shift);
}

1073
#define hr_hw_page_align(x)		ALIGN(x, 1 << HNS_HW_PAGE_SHIFT)
1074

1075 1076
static inline u64 to_hr_hw_page_addr(u64 addr)
{
1077
	return addr >> HNS_HW_PAGE_SHIFT;
1078 1079 1080 1081
}

static inline u32 to_hr_hw_page_shift(u32 page_shift)
{
1082
	return page_shift - HNS_HW_PAGE_SHIFT;
1083 1084
}

1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104
static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count)
{
	if (count > 0)
		return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum;

	return 0;
}

static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift)
{
	return hr_hw_page_align(count << buf_shift);
}

static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift)
{
	return hr_hw_page_align(count << buf_shift) >> buf_shift;
}

static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift)
{
1105 1106 1107
	if (!count)
		return 0;

1108 1109 1110
	return ilog2(to_hr_hem_entries_count(count, buf_shift));
}

1111 1112 1113 1114 1115 1116 1117 1118
#define DSCP_SHIFT 2

static inline u8 get_tclass(const struct ib_global_route *grh)
{
	return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ?
	       grh->traffic_class >> DSCP_SHIFT : grh->traffic_class;
}

1119
void hns_roce_init_uar_table(struct hns_roce_dev *dev);
1120 1121 1122 1123 1124 1125 1126 1127 1128
int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);

int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
			u64 out_param);
int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);

1129 1130 1131
/* hns roce hw need current block and next block addr from mtt */
#define MTT_MIN_COUNT	 2
int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1132
		      u32 offset, u64 *mtt_buf, int mtt_max, u64 *base_addr);
1133
int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1134 1135 1136
			struct hns_roce_buf_attr *buf_attr,
			unsigned int page_shift, struct ib_udata *udata,
			unsigned long user_addr);
1137 1138 1139
void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev,
			  struct hns_roce_mtr *mtr);
int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1140
		     dma_addr_t *pages, unsigned int page_cnt);
1141

1142
void hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
1143
void hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
1144
void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
1145
int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
1146
void hns_roce_init_srq_table(struct hns_roce_dev *hr_dev);
1147
void hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev);
1148 1149 1150 1151 1152 1153

void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);

void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);

1154 1155
int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
		       struct ib_udata *udata);
1156
int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1157 1158 1159 1160
static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags)
{
	return 0;
}
1161

1162
int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1163
int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1164 1165 1166 1167 1168

struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
				   u64 virt_addr, int access_flags,
				   struct ib_udata *udata);
1169 1170 1171 1172
struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start,
				     u64 length, u64 virt_addr,
				     int mr_access_flags, struct ib_pd *pd,
				     struct ib_udata *udata);
1173
struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1174
				u32 max_num_sg);
1175 1176
int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
		       unsigned int *sg_offset);
1177
int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1178
unsigned long key_to_hw_index(u32 key);
1179

1180
int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
1181 1182
int hns_roce_dealloc_mw(struct ib_mw *ibmw);

1183
void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf);
1184 1185
struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size,
					u32 page_shift, u32 flags);
1186

1187
int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1188 1189
			   int buf_cnt, struct hns_roce_buf *buf,
			   unsigned int page_shift);
1190
int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1191
			   int buf_cnt, struct ib_umem *umem,
1192
			   unsigned int page_shift);
1193

1194 1195 1196
int hns_roce_create_srq(struct ib_srq *srq,
			struct ib_srq_init_attr *srq_init_attr,
			struct ib_udata *udata);
1197
int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata);
1198

1199 1200 1201
int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata);
int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata);

1202 1203
int hns_roce_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *init_attr,
		       struct ib_udata *udata);
1204 1205
int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
		       int attr_mask, struct ib_udata *udata);
1206
void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1207 1208 1209 1210
void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n);
bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq,
1211 1212 1213 1214 1215 1216
			  struct ib_cq *ib_cq);
void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
		       struct hns_roce_cq *recv_cq);
void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
			 struct hns_roce_cq *recv_cq);
void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1217 1218
void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
			 struct ib_udata *udata);
1219
__be32 send_ieth(const struct ib_send_wr *wr);
1220 1221
int to_hr_qp_type(int qp_type);

1222 1223
int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
		       struct ib_udata *udata);
1224

1225
int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
1226
int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt,
1227 1228 1229
			 struct hns_roce_db *db);
void hns_roce_db_unmap_user(struct hns_roce_ucontext *context,
			    struct hns_roce_db *db);
1230 1231 1232 1233
int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db,
		      int order);
void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db);

1234 1235
void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
1236
void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp);
1237
void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
1238
void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type);
1239
void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev);
1240 1241
int hns_roce_init(struct hns_roce_dev *hr_dev);
void hns_roce_exit(struct hns_roce_dev *hr_dev);
1242
int hns_roce_fill_res_cq_entry(struct sk_buff *msg, struct ib_cq *ib_cq);
1243
int hns_roce_fill_res_cq_entry_raw(struct sk_buff *msg, struct ib_cq *ib_cq);
1244
int hns_roce_fill_res_qp_entry(struct sk_buff *msg, struct ib_qp *ib_qp);
1245
int hns_roce_fill_res_qp_entry_raw(struct sk_buff *msg, struct ib_qp *ib_qp);
1246
int hns_roce_fill_res_mr_entry(struct sk_buff *msg, struct ib_mr *ib_mr);
1247
int hns_roce_fill_res_mr_entry_raw(struct sk_buff *msg, struct ib_mr *ib_mr);
1248 1249
int hns_roce_fill_res_srq_entry(struct sk_buff *msg, struct ib_srq *ib_srq);
int hns_roce_fill_res_srq_entry_raw(struct sk_buff *msg, struct ib_srq *ib_srq);
1250 1251 1252 1253
struct hns_user_mmap_entry *
hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address,
				size_t length,
				enum hns_roce_mmap_type mmap_type);
1254
#endif /* _HNS_ROCE_DEVICE_H */