• Sai Prakash Ranjan's avatar
    drm/msm/a6xx: Create an A6XX GPU specific address space · 45596f25
    Sai Prakash Ranjan authored
    A6XX GPUs have support for last level cache(LLC) also known
    as system cache and need to set the bus attributes to
    use it. Currently we use a generic adreno iommu address space
    implementation which are also used by older GPU generations
    which do not have LLC and might introduce issues accidentally
    and is not clean in a way that anymore additions of GPUs
    supporting LLC would have to be guarded under ifdefs. So keep
    the generic code separate and make the address space creation
    A6XX specific. We also have a helper to set the llc attributes
    so that if the newer GPU generations do support them, we can
    use it instead of open coding domain attribute setting for each
    GPU.
    Signed-off-by: default avatarSai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
    Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
    45596f25
adreno_gpu.c 23.2 KB