• Pallavi Mishra's avatar
    drm/xe/uapi: Add support for CPU caching mode · 622f709c
    Pallavi Mishra authored
    Allow userspace to specify the CPU caching mode at object creation.
    Modify gem create handler and introduce xe_bo_create_user to replace
    xe_bo_create. In a later patch we will support setting the pat_index as
    part of vm_bind, where expectation is that the coherency mode extracted
    from the pat_index must be least 1way coherent if using cpu_caching=wb.
    
    v2
      - s/smem_caching/smem_cpu_caching/ and
        s/XE_GEM_CACHING/XE_GEM_CPU_CACHING/. (Matt Roper)
      - Drop COH_2WAY and just use COH_NONE + COH_AT_LEAST_1WAY; KMD mostly
        just cares that zeroing/swap-in can't be bypassed with the given
        smem_caching mode. (Matt Roper)
      - Fix broken range check for coh_mode and smem_cpu_caching and also
        don't use constant value, but the already defined macros. (José)
      - Prefer switch statement for smem_cpu_caching -> ttm_caching. (José)
      - Add note in kernel-doc for dgpu and coherency modes for system
        memory. (José)
    v3 (José):
      - Make sure to reject coh_mode == 0 for VRAM-only.
      - Also make sure to actually pass along the (start, end) for
        __xe_bo_create_locked.
    v4
      - Drop UC caching mode. Can be added back if we need it. (Matt Roper)
      - s/smem_cpu_caching/cpu_caching. Idea is that VRAM is always WC, but
        that is currently implicit and KMD controlled. Make it explicit in
        the uapi with the limitation that it currently must be WC. For VRAM
        + SYS objects userspace must now select WC. (José)
      - Make sure to initialize bo_flags. (José)
    v5
      - Make to align with the other uapi and prefix uapi constants with
        DRM_ (José)
    v6:
      - Make it clear that zero cpu_caching is only allowed for kernel
        objects. (José)
    v7: (Oak)
      - With all the changes from the original design, it looks we can
        further simplify here and drop the explicit coh_mode. We can just
        infer the coh_mode from the cpu_caching. i.e reject cpu_caching=wb +
        coh_none. It's one less thing for userspace to maintain so seems
        worth it.
    v8:
      - Make sure to also update the kselftests.
    
    Testcase: igt@xe_mmap@cpu-caching
    Signed-off-by: default avatarPallavi Mishra <pallavi.mishra@intel.com>
    Co-developed-by: default avatarMatthew Auld <matthew.auld@intel.com>
    Signed-off-by: default avatarMatthew Auld <matthew.auld@intel.com>
    Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
    Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
    Cc: Lucas De Marchi <lucas.demarchi@intel.com>
    Cc: Matt Roper <matthew.d.roper@intel.com>
    Cc: José Roberto de Souza <jose.souza@intel.com>
    Cc: Filip Hazubski <filip.hazubski@intel.com>
    Cc: Carl Zhang <carl.zhang@intel.com>
    Cc: Effie Yu <effie.yu@intel.com>
    Cc: Zhengguo Xu <zhengguo.xu@intel.com>
    Cc: Francois Dugast <francois.dugast@intel.com>
    Cc: Oak Zeng <oak.zeng@intel.com>
    Reviewed-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
    Acked-by: default avatarZhengguo Xu <zhengguo.xu@intel.com>
    Acked-by: default avatarBartosz Dunajski <bartosz.dunajski@intel.com>
    Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
    622f709c
xe_bo.c 8.06 KB