This fixes a few issues with context switch on ppc32:

 - Makes sure we properly flush out all stores to the coherency domain
   when switching out, since the same thread could be switched back in
   on another CPU right away, those stores must be visible to all other
   CPUs. 

 - Remove dssall in the assembly calls and do it now once in switch_mm
   (stop vmx streams).  Assume the G5 doesn't need a sync after dssall. 

 - Remove bogus isync in the loop setting the userland segment registers

 - Do not switch the userland segments when the mm stays the same