• Animesh Manna's avatar
    drm/i915/panelreplay: Initializaton and compute config for panel replay · b8cf5b5d
    Animesh Manna authored
    Modify existing PSR implementation to enable panel replay feature of DP 2.0
    which is similar to PSR feature of EDP panel. There is different DPCD
    address to check panel capability compare to PSR and vsc sdp header
    is different.
    
    v1: Initial version.
    v2:
    - Set source_panel_replay_support flag under HAS_PANEL_REPLAY()
    condition check. [Jouni]
    - Code restructured around intel_panel_replay_init
    and renamed to intel_panel_replay_init_dpcd. [Jouni]
    - Remove the initial code modification around has_psr2 flag. [Jouni]
    - Add CAN_PANEL_REPLAY() in intel_encoder_can_psr which is used to
    enable in intel_psr_post_plane_update. [Jouni]
    v3:
    - Initialize both psr and panel-replay. [Jouni]
    - Initialize both panel replay and psr if detected. [Jouni]
    - Refactoring psr function by introducing _psr_compute_config(). [Jouni]
    - Add check for !is_edp while deriving source_panel_replay_support. [Jouni]
    - Enable panel replay dpcd initialization in a separate patch. [Jouni]
    
    v4:
    - HAS_PANEL_REPLAY() check not needed during sink capability check. [Jouni]
    - Set either panel replay source support or psr. [Jouni]
    
    v5:
    - HAS_PANEL_REPLAY() removed and use HAS_DP20() instead. [Jouni]
    - Move psr related code to intel_psr.c. [Jani]
    - Reset sink_panel_replay_support flag during disconnection. [Jani]
    
    v6: return statement restored which is removed by misatke. [Jouni]
    v7: cosmetic changes. [Arun]
    
    Cc: Jouni Högander <jouni.hogander@intel.com>
    Cc: Arun R Murthy <arun.r.murthy@intel.com>
    Cc: Jani Nikula <jani.nikula@intel.com>
    Reviewed-by: default avatarArun R Murthy <arun.r.murthy@intel.com>
    Signed-off-by: default avatarAnimesh Manna <animesh.manna@intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20231108072303.3414118-4-animesh.manna@intel.com
    b8cf5b5d
intel_dp.c 188 KB