• Sean Christopherson's avatar
    KVM: x86: SEV: Treat C-bit as legal GPA bit regardless of vCPU mode · ca29e145
    Sean Christopherson authored
    Rename cr3_lm_rsvd_bits to reserved_gpa_bits, and use it for all GPA
    legality checks.  AMD's APM states:
    
      If the C-bit is an address bit, this bit is masked from the guest
      physical address when it is translated through the nested page tables.
    
    Thus, any access that can conceivably be run through NPT should ignore
    the C-bit when checking for validity.
    
    For features that KVM emulates in software, e.g. MTRRs, there is no
    clear direction in the APM for how the C-bit should be handled.  For
    such cases, follow the SME behavior inasmuch as possible, since SEV is
    is essentially a VM-specific variant of SME.  For SME, the APM states:
    
      In this case the upper physical address bits are treated as reserved
      when the feature is enabled except where otherwise indicated.
    
    Collecting the various relavant SME snippets in the APM and cross-
    referencing the omissions with Linux kernel code, this leaves MTTRs and
    APIC_BASE as the only flows that KVM emulates that should _not_ ignore
    the C-bit.
    
    Note, this means the reserved bit checks in the page tables are
    technically broken.  This will be remedied in a future patch.
    
    Although the page table checks are technically broken, in practice, it's
    all but guaranteed to be irrelevant.  NPT is required for SEV, i.e.
    shadowing page tables isn't needed in the common case.  Theoretically,
    the checks could be in play for nested NPT, but it's extremely unlikely
    that anyone is running nested VMs on SEV, as doing so would require L1
    to expose sensitive data to L0, e.g. the entire VMCB.  And if anyone is
    running nested VMs, L0 can't read the guest's encrypted memory, i.e. L1
    would need to put its NPT in shared memory, in which case the C-bit will
    never be set.  Or, L1 could use shadow paging, but again, if L0 needs to
    read page tables, e.g. to load PDPTRs, the memory can't be encrypted if
    L1 has any expectation of L0 doing the right thing.
    
    Cc: Tom Lendacky <thomas.lendacky@amd.com>
    Cc: Brijesh Singh <brijesh.singh@amd.com>
    Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
    Message-Id: <20210204000117.3303214-8-seanjc@google.com>
    Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
    ca29e145
cpuid.h 9.63 KB