Commit 01e66bec authored by Dave Jones's avatar Dave Jones Committed by Dave Jones

[AGPGART] add bridge parameter to driver functions

From: Michael Werner <werner@mrcoffee.engr.sgi.com>

Add bridge parameter to create_gatt_table, free_gatt_table and mask_memory
Signed-off-by: default avatarMike Werner <werner@sgi.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
parent 2704ec57
......@@ -101,13 +101,14 @@ struct agp_bridge_driver {
struct gatt_mask *masks;
int (*fetch_size)(void);
int (*configure)(void);
void (*agp_enable)(u32);
void (*agp_enable)(struct agp_bridge_data *, u32);
void (*cleanup)(void);
void (*tlb_flush)(struct agp_memory *);
unsigned long (*mask_memory)(unsigned long, int);
unsigned long (*mask_memory)(struct agp_bridge_data *,
unsigned long, int);
void (*cache_flush)(void);
int (*create_gatt_table)(void);
int (*free_gatt_table)(void);
int (*create_gatt_table)(struct agp_bridge_data *);
int (*free_gatt_table)(struct agp_bridge_data *);
int (*insert_memory)(struct agp_memory *, off_t, int);
int (*remove_memory)(struct agp_memory *, off_t, int);
struct agp_memory *(*alloc_by_type) (size_t, int);
......@@ -246,9 +247,9 @@ int agp_frontend_initialize(void);
void agp_frontend_cleanup(void);
/* Generic routines. */
void agp_generic_enable(u32 mode);
int agp_generic_create_gatt_table(void);
int agp_generic_free_gatt_table(void);
void agp_generic_enable(struct agp_bridge_data *bridge, u32 mode);
int agp_generic_create_gatt_table(struct agp_bridge_data *bridge);
int agp_generic_free_gatt_table(struct agp_bridge_data *bridge);
struct agp_memory *agp_create_memory(int scratch_pages);
int agp_generic_insert_memory(struct agp_memory *mem, off_t pg_start, int type);
int agp_generic_remove_memory(struct agp_memory *mem, off_t pg_start, int type);
......@@ -263,7 +264,8 @@ void agp_device_command(u32 command, int agp_v3);
int agp_3_5_enable(struct agp_bridge_data *bridge);
void global_cache_flush(void);
void get_agp_version(struct agp_bridge_data *bridge);
unsigned long agp_generic_mask_memory(unsigned long addr, int type);
unsigned long agp_generic_mask_memory(struct agp_bridge_data *bridge,
unsigned long addr, int type);
struct agp_bridge_data *agp_generic_find_bridge(struct pci_dev *pdev);
/* generic routines for agp>=3 */
......
......@@ -76,11 +76,12 @@ static void alpha_core_agp_tlbflush(struct agp_memory *mem)
alpha_mv.mv_pci_tbi(agp->hose, 0, -1);
}
static void alpha_core_agp_enable(u32 mode)
static void alpha_core_agp_enable(struct agp_bridge_data *bridge, u32 mode)
{
alpha_agp_info *agp = agp_bridge->dev_private_data;
alpha_agp_info *agp = bridge->dev_private_data;
agp->mode.lw = agp_collect_device_status(mode, agp->capability.lw);
agp->mode.lw = agp_collect_device_status(bridge, mode,
agp->capability.lw);
agp->mode.bits.enable = 1;
agp->ops->configure(agp);
......
......@@ -132,7 +132,7 @@ static int amd_create_gatt_pages(int nr_tables)
#define GET_GATT(addr) (amd_irongate_private.gatt_pages[\
GET_PAGE_DIR_IDX(addr)]->remapped)
static int amd_create_gatt_table(void)
static int amd_create_gatt_table(struct agp_bridge_data *bridge)
{
struct aper_size_info_lvl2 *value;
struct amd_page_map page_dir;
......@@ -175,7 +175,7 @@ static int amd_create_gatt_table(void)
return 0;
}
static int amd_free_gatt_table(void)
static int amd_free_gatt_table(struct agp_bridge_data *bridge)
{
struct amd_page_map page_dir;
......@@ -314,7 +314,8 @@ static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = GET_GATT(addr);
writel(agp_generic_mask_memory(mem->memory[i], mem->type), cur_gatt+GET_GATT_OFF(addr));
writel(agp_generic_mask_memory(agp_bridge,
mem->memory[i], mem->type), cur_gatt+GET_GATT_OFF(addr));
readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */
}
amd_irongate_tlbflush(mem);
......
......@@ -106,7 +106,8 @@ static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
}
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
tmp = agp_bridge->driver->mask_memory(mem->memory[i], mem->type);
tmp = agp_bridge->driver->mask_memory(agp_bridge,
mem->memory[i], mem->type);
BUG_ON(tmp & 0xffffff0000000ffcULL);
pte = (tmp & 0x000000ff00000000ULL) >> 28;
......
......@@ -291,7 +291,8 @@ static int ati_insert_memory(struct agp_memory * mem,
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = GET_GATT(addr);
writel(agp_bridge->driver->mask_memory(mem->memory[i], mem->type), cur_gatt+GET_GATT_OFF(addr));
writel(agp_bridge->driver->mask_memory(agp_bridge,
mem->memory[i], mem->type), cur_gatt+GET_GATT_OFF(addr));
readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */
}
agp_bridge->driver->tlb_flush(mem);
......@@ -319,7 +320,7 @@ static int ati_remove_memory(struct agp_memory * mem, off_t pg_start,
return 0;
}
static int ati_create_gatt_table(void)
static int ati_create_gatt_table(struct agp_bridge_data *bridge)
{
struct aper_size_info_lvl2 *value;
ati_page_map page_dir;
......@@ -380,7 +381,7 @@ static int ati_create_gatt_table(void)
return 0;
}
static int ati_free_gatt_table(void)
static int ati_free_gatt_table(struct agp_bridge_data *bridge)
{
ati_page_map page_dir;
......
......@@ -149,7 +149,7 @@ static int agp_backend_initialize(struct agp_bridge_data *bridge)
bridge->scratch_page_real = virt_to_phys(addr);
bridge->scratch_page =
bridge->driver->mask_memory(bridge->scratch_page_real, 0);
bridge->driver->mask_memory(bridge, bridge->scratch_page_real, 0);
}
size_value = bridge->driver->fetch_size();
......@@ -158,7 +158,7 @@ static int agp_backend_initialize(struct agp_bridge_data *bridge)
rc = -EINVAL;
goto err_out;
}
if (bridge->driver->create_gatt_table()) {
if (bridge->driver->create_gatt_table(bridge)) {
printk(KERN_ERR PFX
"unable to get memory for graphics translation table.\n");
rc = -ENOMEM;
......@@ -190,7 +190,7 @@ static int agp_backend_initialize(struct agp_bridge_data *bridge)
bridge->driver->agp_destroy_page(
phys_to_virt(bridge->scratch_page_real));
if (got_gatt)
bridge->driver->free_gatt_table();
bridge->driver->free_gatt_table(bridge);
if (got_keylist) {
vfree(bridge->key_list);
bridge->key_list = NULL;
......@@ -204,7 +204,7 @@ static void agp_backend_cleanup(struct agp_bridge_data *bridge)
if (bridge->driver->cleanup)
bridge->driver->cleanup();
if (bridge->driver->free_gatt_table)
bridge->driver->free_gatt_table();
bridge->driver->free_gatt_table(bridge);
if (bridge->key_list) {
vfree(bridge->key_list);
bridge->key_list = NULL;
......
......@@ -148,7 +148,7 @@ static int efficeon_configure(void)
return 0;
}
static int efficeon_free_gatt_table(void)
static int efficeon_free_gatt_table(struct agp_bridge_data *bridge)
{
int index, freed = 0;
......@@ -183,7 +183,7 @@ static int efficeon_free_gatt_table(void)
#define GET_GATT(addr) (efficeon_private.gatt_pages[\
GET_PAGE_DIR_IDX(addr)]->remapped)
static int efficeon_create_gatt_table(void)
static int efficeon_create_gatt_table(struct agp_bridge_data *bridge)
{
int index;
const int pati = EFFICEON_PATI;
......@@ -209,7 +209,7 @@ static int efficeon_create_gatt_table(void)
page = get_zeroed_page(GFP_KERNEL);
if (!page) {
efficeon_free_gatt_table();
efficeon_free_gatt_table(agp_bridge);
return -ENOMEM;
}
SetPageReserved(virt_to_page((char *)page));
......
......@@ -720,7 +720,7 @@ void get_agp_version(struct agp_bridge_data *bridge)
EXPORT_SYMBOL(get_agp_version);
void agp_generic_enable(u32 requested_mode)
void agp_generic_enable(struct agp_bridge_data *bridge, u32 requested_mode)
{
u32 bridge_agpstat, temp;
......@@ -742,19 +742,21 @@ void agp_generic_enable(u32 requested_mode)
bridge_agpstat |= AGPSTAT_AGP_ENABLE;
/* Do AGP version specific frobbing. */
if(agp_bridge->major_version >= 3) {
if (check_bridge_mode(agp_bridge->dev)) {
if (bridge->major_version >= 3) {
if (check_bridge_mode(bridge->dev)) {
/* If we have 3.5, we can do the isoch stuff. */
if (agp_bridge->minor_version >= 5)
agp_3_5_enable(agp_bridge);
if (bridge->minor_version >= 5)
agp_3_5_enable(bridge);
agp_device_command(bridge_agpstat, TRUE);
return;
} else {
/* Disable calibration cycle in RX91<1> when not in AGP3.0 mode of operation.*/
bridge_agpstat &= ~(7<<10) ;
pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+AGPCTRL, &temp);
pci_read_config_dword(bridge->dev,
bridge->capndx+AGPCTRL, &temp);
temp |= (1<<9);
pci_write_config_dword(agp_bridge->dev, agp_bridge->capndx+AGPCTRL, temp);
pci_write_config_dword(bridge->dev,
bridge->capndx+AGPCTRL, temp);
printk (KERN_INFO PFX "Device is in legacy mode,"
" falling back to 2.x\n");
......@@ -767,7 +769,7 @@ void agp_generic_enable(u32 requested_mode)
EXPORT_SYMBOL(agp_generic_enable);
int agp_generic_create_gatt_table(void)
int agp_generic_create_gatt_table(struct agp_bridge_data *bridge)
{
char *table;
char *table_end;
......@@ -779,17 +781,17 @@ int agp_generic_create_gatt_table(void)
struct page *page;
/* The generic routines can't handle 2 level gatt's */
if (agp_bridge->driver->size_type == LVL2_APER_SIZE)
if (bridge->driver->size_type == LVL2_APER_SIZE)
return -EINVAL;
table = NULL;
i = agp_bridge->aperture_size_idx;
temp = agp_bridge->current_size;
i = bridge->aperture_size_idx;
temp = bridge->current_size;
size = page_order = num_entries = 0;
if (agp_bridge->driver->size_type != FIXED_APER_SIZE) {
if (bridge->driver->size_type != FIXED_APER_SIZE) {
do {
switch (agp_bridge->driver->size_type) {
switch (bridge->driver->size_type) {
case U8_APER_SIZE:
size = A_SIZE_8(temp)->size;
page_order =
......@@ -820,29 +822,29 @@ int agp_generic_create_gatt_table(void)
if (table == NULL) {
i++;
switch (agp_bridge->driver->size_type) {
switch (bridge->driver->size_type) {
case U8_APER_SIZE:
agp_bridge->current_size = A_IDX8(agp_bridge);
bridge->current_size = A_IDX8(bridge);
break;
case U16_APER_SIZE:
agp_bridge->current_size = A_IDX16(agp_bridge);
bridge->current_size = A_IDX16(bridge);
break;
case U32_APER_SIZE:
agp_bridge->current_size = A_IDX32(agp_bridge);
bridge->current_size = A_IDX32(bridge);
break;
/* This case will never really happen. */
case FIXED_APER_SIZE:
case LVL2_APER_SIZE:
default:
agp_bridge->current_size =
agp_bridge->current_size;
bridge->current_size =
bridge->current_size;
break;
}
temp = agp_bridge->current_size;
temp = bridge->current_size;
} else {
agp_bridge->aperture_size_idx = i;
bridge->aperture_size_idx = i;
}
} while (!table && (i < agp_bridge->driver->num_aperture_sizes));
} while (!table && (i < bridge->driver->num_aperture_sizes));
} else {
size = ((struct aper_size_info_fixed *) temp)->size;
page_order = ((struct aper_size_info_fixed *) temp)->page_order;
......@@ -858,15 +860,15 @@ int agp_generic_create_gatt_table(void)
for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
SetPageReserved(page);
agp_bridge->gatt_table_real = (u32 *) table;
bridge->gatt_table_real = (u32 *) table;
agp_gatt_table = (void *)table;
agp_bridge->driver->cache_flush();
agp_bridge->gatt_table = ioremap_nocache(virt_to_phys(table),
bridge->driver->cache_flush();
bridge->gatt_table = ioremap_nocache(virt_to_phys(table),
(PAGE_SIZE * (1 << page_order)));
agp_bridge->driver->cache_flush();
bridge->driver->cache_flush();
if (agp_bridge->gatt_table == NULL) {
if (bridge->gatt_table == NULL) {
for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
ClearPageReserved(page);
......@@ -874,28 +876,28 @@ int agp_generic_create_gatt_table(void)
return -ENOMEM;
}
agp_bridge->gatt_bus_addr = virt_to_phys(agp_bridge->gatt_table_real);
bridge->gatt_bus_addr = virt_to_phys(bridge->gatt_table_real);
/* AK: bogus, should encode addresses > 4GB */
for (i = 0; i < num_entries; i++) {
writel(agp_bridge->scratch_page, agp_bridge->gatt_table+i);
readl(agp_bridge->gatt_table+i); /* PCI Posting. */
writel(bridge->scratch_page, bridge->gatt_table+i);
readl(bridge->gatt_table+i); /* PCI Posting. */
}
return 0;
}
EXPORT_SYMBOL(agp_generic_create_gatt_table);
int agp_generic_free_gatt_table(void)
int agp_generic_free_gatt_table(struct agp_bridge_data *bridge)
{
int page_order;
char *table, *table_end;
void *temp;
struct page *page;
temp = agp_bridge->current_size;
temp = bridge->current_size;
switch (agp_bridge->driver->size_type) {
switch (bridge->driver->size_type) {
case U8_APER_SIZE:
page_order = A_SIZE_8(temp)->page_order;
break;
......@@ -921,19 +923,19 @@ int agp_generic_free_gatt_table(void)
* called, then all agp memory is deallocated and removed
* from the table. */
iounmap(agp_bridge->gatt_table);
table = (char *) agp_bridge->gatt_table_real;
iounmap(bridge->gatt_table);
table = (char *) bridge->gatt_table_real;
table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1);
for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
ClearPageReserved(page);
free_pages((unsigned long) agp_bridge->gatt_table_real, page_order);
free_pages((unsigned long) bridge->gatt_table_real, page_order);
agp_gatt_table = NULL;
agp_bridge->gatt_table = NULL;
agp_bridge->gatt_table_real = NULL;
agp_bridge->gatt_bus_addr = 0;
bridge->gatt_table = NULL;
bridge->gatt_table_real = NULL;
bridge->gatt_bus_addr = 0;
return 0;
}
......@@ -1002,7 +1004,7 @@ int agp_generic_insert_memory(struct agp_memory * mem, off_t pg_start, int type)
}
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
writel(bridge->driver->mask_memory(mem->memory[i], mem->type), bridge->gatt_table+j);
writel(bridge->driver->mask_memory(bridge, mem->memory[i], mem->type), bridge->gatt_table+j);
readl(bridge->gatt_table+j); /* PCI Posting. */
}
......@@ -1110,7 +1112,7 @@ void agp_enable(struct agp_bridge_data *bridge, u32 mode)
{
if (!bridge)
return;
bridge->driver->agp_enable(mode);
bridge->driver->agp_enable(bridge, mode);
}
EXPORT_SYMBOL(agp_enable);
......@@ -1138,11 +1140,12 @@ void global_cache_flush(void)
}
EXPORT_SYMBOL(global_cache_flush);
unsigned long agp_generic_mask_memory(unsigned long addr, int type)
unsigned long agp_generic_mask_memory(struct agp_bridge_data *bridge,
unsigned long addr, int type)
{
/* memory type is ignored in the generic routine */
if (agp_bridge->driver->masks)
return addr | agp_bridge->driver->masks[0].mask;
if (bridge->driver->masks)
return addr | bridge->driver->masks[0].mask;
else
return addr;
}
......
......@@ -289,7 +289,7 @@ hp_zx1_tlbflush (struct agp_memory *mem)
}
static int
hp_zx1_create_gatt_table (void)
hp_zx1_create_gatt_table (struct agp_bridge_data *bridge)
{
struct _hp_private *hp = &hp_private;
int i;
......@@ -317,7 +317,7 @@ hp_zx1_create_gatt_table (void)
}
static int
hp_zx1_free_gatt_table (void)
hp_zx1_free_gatt_table (struct agp_bridge_data *bridge)
{
struct _hp_private *hp = &hp_private;
......@@ -367,7 +367,9 @@ hp_zx1_insert_memory (struct agp_memory *mem, off_t pg_start, int type)
for (k = 0;
k < hp->io_pages_per_kpage;
k++, j++, paddr += hp->io_page_size) {
hp->gatt[j] = agp_bridge->driver->mask_memory(paddr, type);
hp->gatt[j] =
agp_bridge->driver->mask_memory(agp_bridge,
paddr, type);
}
}
......@@ -396,19 +398,20 @@ hp_zx1_remove_memory (struct agp_memory *mem, off_t pg_start, int type)
}
static unsigned long
hp_zx1_mask_memory (unsigned long addr, int type)
hp_zx1_mask_memory (struct agp_bridge_data *bridge,
unsigned long addr, int type)
{
return HP_ZX1_PDIR_VALID_BIT | addr;
}
static void
hp_zx1_enable (u32 mode)
hp_zx1_enable (struct agp_bridge_data *bridge, u32 mode)
{
struct _hp_private *hp = &hp_private;
u32 command;
command = readl(hp->lba_regs+hp->lba_cap_offset+PCI_AGP_STATUS);
command = agp_collect_device_status(mode, command);
command = agp_collect_device_status(bridge, mode, command);
command |= 0x00000100;
writel(command, hp->lba_regs+hp->lba_cap_offset+PCI_AGP_COMMAND);
......
......@@ -233,7 +233,7 @@ static int i460_configure (void)
return 0;
}
static int i460_create_gatt_table (void)
static int i460_create_gatt_table (struct agp_bridge_data *bridge)
{
int page_order, num_entries, i;
void *temp;
......@@ -258,7 +258,7 @@ static int i460_create_gatt_table (void)
return 0;
}
static int i460_free_gatt_table (void)
static int i460_free_gatt_table (struct agp_bridge_data *bridge)
{
int num_entries, i;
void *temp;
......@@ -314,7 +314,8 @@ static int i460_insert_memory_small_io_page (struct agp_memory *mem,
for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
paddr = mem->memory[i];
for (k = 0; k < I460_IOPAGES_PER_KPAGE; k++, j++, paddr += io_page_size)
WR_GATT(j, agp_bridge->driver->mask_memory(paddr, mem->type));
WR_GATT(j, agp_bridge->driver->mask_memory(agp_bridge,
paddr, mem->type));
}
WR_FLUSH_GATT(j - 1);
return 0;
......@@ -427,7 +428,8 @@ static int i460_insert_memory_large_io_page (struct agp_memory *mem,
if (i460_alloc_large_page(lp) < 0)
return -ENOMEM;
pg = lp - i460.lp_desc;
WR_GATT(pg, agp_bridge->driver->mask_memory(lp->paddr, 0));
WR_GATT(pg, agp_bridge->driver->mask_memory(agp_bridge,
lp->paddr, 0));
WR_FLUSH_GATT(pg);
}
......@@ -529,10 +531,11 @@ static void i460_destroy_page (void *page)
#endif /* I460_LARGE_IO_PAGES */
static unsigned long i460_mask_memory (unsigned long addr, int type)
static unsigned long i460_mask_memory (struct agp_bridge_data *bridge,
unsigned long addr, int type)
{
/* Make sure the returned address is a valid GATT entry */
return agp_bridge->driver->masks[0].mask
return bridge->driver->masks[0].mask
| (((addr & ~((1 << I460_IO_PAGE_SHIFT) - 1)) & 0xffffff000) >> 12);
}
......
......@@ -150,7 +150,7 @@ static void intel_i810_tlbflush(struct agp_memory *mem)
return;
}
static void intel_i810_agp_enable(u32 mode)
static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
{
return;
}
......@@ -229,8 +229,9 @@ static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
insert:
global_cache_flush();
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
writel(agp_bridge->driver->mask_memory(mem->memory[i], mem->type),
intel_i810_private.registers+I810_PTE_BASE+(j*4));
writel(agp_bridge->driver->mask_memory(agp_bridge,
mem->memory[i], mem->type),
intel_i810_private.registers+I810_PTE_BASE+(j*4));
readl(intel_i810_private.registers+I810_PTE_BASE+(j*4)); /* PCI Posting. */
}
global_cache_flush();
......@@ -337,10 +338,11 @@ static void intel_i810_free_by_type(struct agp_memory *curr)
kfree(curr);
}
static unsigned long intel_i810_mask_memory(unsigned long addr, int type)
static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
unsigned long addr, int type)
{
/* Type checking must be done elsewhere */
return addr | agp_bridge->driver->masks[type].mask;
return addr | bridge->driver->masks[type].mask;
}
static struct aper_size_info_fixed intel_i830_sizes[] =
......@@ -447,7 +449,7 @@ static void intel_i830_init_gtt_entries(void)
/* The intel i830 automatically initializes the agp aperture during POST.
* Use the memory already set aside for in the GTT.
*/
static int intel_i830_create_gatt_table(void)
static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
{
int page_order;
struct aper_size_info_fixed *size;
......@@ -482,7 +484,7 @@ static int intel_i830_create_gatt_table(void)
/* Return the gatt table to a sane state. Use the top of stolen
* memory for the GTT.
*/
static int intel_i830_free_gatt_table(void)
static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
{
return 0;
}
......@@ -582,8 +584,9 @@ static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int
global_cache_flush(); /* FIXME: Necessary ?*/
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
writel(agp_bridge->driver->mask_memory(mem->memory[i], mem->type),
intel_i830_private.registers+I810_PTE_BASE+(j*4));
writel(agp_bridge->driver->mask_memory(agp_bridge,
mem->memory[i], mem->type),
intel_i830_private.registers+I810_PTE_BASE+(j*4));
readl(intel_i830_private.registers+I810_PTE_BASE+(j*4)); /* PCI Posting. */
}
......@@ -691,7 +694,8 @@ static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
global_cache_flush();
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
writel(agp_bridge->driver->mask_memory(mem->memory[i], mem->type), intel_i830_private.gtt+j);
writel(agp_bridge->driver->mask_memory(agp_bridge,
mem->memory[i], mem->type), intel_i830_private.gtt+j);
readl(intel_i830_private.gtt+j); /* PCI Posting. */
}
......@@ -743,7 +747,7 @@ static int intel_i915_fetch_size(void)
/* The intel i915 automatically initializes the agp aperture during POST.
* Use the memory already set aside for in the GTT.
*/
static int intel_i915_create_gatt_table(void)
static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
{
int page_order;
struct aper_size_info_fixed *size;
......
......@@ -215,7 +215,8 @@ static int nvidia_insert_memory(struct agp_memory *mem, off_t pg_start, int type
mem->is_flushed = TRUE;
}
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
writel(agp_bridge->driver->mask_memory(mem->memory[i], mem->type),
writel(agp_bridge->driver->mask_memory(agp_bridge,
mem->memory[i], mem->type),
agp_bridge->gatt_table+nvidia_private.pg_offset+j);
readl(agp_bridge->gatt_table+nvidia_private.pg_offset+j); /* PCI Posting. */
}
......
......@@ -70,7 +70,7 @@ static void sis_cleanup(void)
(previous_size->size_value & ~(0x03)));
}
static void sis_delayed_enable(u32 mode)
static void sis_delayed_enable(struct agp_bridge_data *bridge, u32 mode)
{
struct pci_dev *device = NULL;
u32 command;
......@@ -82,7 +82,7 @@ static void sis_delayed_enable(u32 mode)
agp_bridge->dev->slot_name);
pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + PCI_AGP_STATUS, &command);
command = agp_collect_device_status(agp_bridge, mode, command);
command = agp_collect_device_status(bridge, mode, command);
command |= AGPSTAT_AGP_ENABLE;
rate = (command & 0x7) << 2;
......@@ -101,7 +101,7 @@ static void sis_delayed_enable(u32 mode)
* command register triggers a 5ms screwup during which the master
* cannot be configured
*/
if (device->device == agp_bridge->dev->device) {
if (device->device == bridge->dev->device) {
printk(KERN_INFO PFX "SiS delay workaround: giving bridge time to recover.\n");
msleep(10);
}
......
......@@ -141,7 +141,7 @@ static int serverworks_create_gatt_pages(int nr_tables)
#define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
#endif
static int serverworks_create_gatt_table(void)
static int serverworks_create_gatt_table(struct agp_bridge_data *bridge)
{
struct aper_size_info_lvl2 *value;
struct serverworks_page_map page_dir;
......@@ -192,7 +192,7 @@ static int serverworks_create_gatt_table(void)
return 0;
}
static int serverworks_free_gatt_table(void)
static int serverworks_free_gatt_table(struct agp_bridge_data *bridge)
{
struct serverworks_page_map page_dir;
......@@ -341,7 +341,7 @@ static int serverworks_insert_memory(struct agp_memory *mem,
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = SVRWRKS_GET_GATT(addr);
writel(agp_bridge->driver->mask_memory(mem->memory[i], mem->type), cur_gatt+GET_GATT_OFF(addr));
writel(agp_bridge->driver->mask_memory(agp_bridge, mem->memory[i], mem->type), cur_gatt+GET_GATT_OFF(addr));
}
serverworks_tlbflush(mem);
return 0;
......@@ -387,15 +387,15 @@ static struct aper_size_info_lvl2 serverworks_sizes[7] =
{32, 8192, 0xfe000000}
};
static void serverworks_agp_enable(u32 mode)
static void serverworks_agp_enable(struct agp_bridge_data *bridge, u32 mode)
{
u32 command;
pci_read_config_dword(serverworks_private.svrwrks_dev,
agp_bridge->capndx + PCI_AGP_STATUS,
bridge->capndx + PCI_AGP_STATUS,
&command);
command = agp_collect_device_status(agp_bridge, mode, command);
command = agp_collect_device_status(bridge, mode, command);
command &= ~0x10; /* disable FW */
command &= ~0x08;
......@@ -403,7 +403,7 @@ static void serverworks_agp_enable(u32 mode)
command |= 0x100;
pci_write_config_dword(serverworks_private.svrwrks_dev,
agp_bridge->capndx + PCI_AGP_COMMAND,
bridge->capndx + PCI_AGP_COMMAND,
command);
agp_device_command(command, 0);
......
......@@ -124,27 +124,27 @@ static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start,
return 0;
}
static void uninorth_agp_enable(u32 mode)
static void uninorth_agp_enable(struct agp_bridge_data *bridge, u32 mode)
{
u32 command, scratch;
int timeout;
pci_read_config_dword(agp_bridge->dev,
agp_bridge->capndx + PCI_AGP_STATUS,
pci_read_config_dword(bridge->dev,
bridge->capndx + PCI_AGP_STATUS,
&command);
command = agp_collect_device_status(mode, command);
command = agp_collect_device_status(bridge, mode, command);
command |= 0x100;
uninorth_tlbflush(NULL);
timeout = 0;
do {
pci_write_config_dword(agp_bridge->dev,
agp_bridge->capndx + PCI_AGP_COMMAND,
pci_write_config_dword(bridge->dev,
bridge->capndx + PCI_AGP_COMMAND,
command);
pci_read_config_dword(agp_bridge->dev,
agp_bridge->capndx + PCI_AGP_COMMAND,
pci_read_config_dword(bridge->dev,
bridge->capndx + PCI_AGP_COMMAND,
&scratch);
} while ((scratch & 0x100) == 0 && ++timeout < 1000);
if ((scratch & 0x100) == 0)
......@@ -155,7 +155,7 @@ static void uninorth_agp_enable(u32 mode)
uninorth_tlbflush(NULL);
}
static int uninorth_create_gatt_table(void)
static int uninorth_create_gatt_table(struct agp_bridge_data *bridge)
{
char *table;
char *table_end;
......@@ -212,7 +212,7 @@ static int uninorth_create_gatt_table(void)
return 0;
}
static int uninorth_free_gatt_table(void)
static int uninorth_free_gatt_table(struct agp_bridge_data *bridge)
{
int page_order;
char *table, *table_end;
......
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