KVM: arm/arm64: vgic: Don't notify EOI for non-SPIs

commit 8ca18eec upstream.

When we inject a level triggerered interrupt (and unless it
is backed by the physical distributor - timer style), we request
a maintenance interrupt. Part of the processing for that interrupt
is to feed to the rest of KVM (and to the eventfd subsystem) the
information that the interrupt has been EOIed.

But that notification only makes sense for SPIs, and not PPIs
(such as the PMU interrupt). Skip over the notification if
the interrupt is not an SPI.

Fixes: 140b086d ("KVM: arm/arm64: vgic-new: Add GICv2 world switch backend")
Fixes: 59529f69 ("KVM: arm/arm64: vgic-new: Add GICv3 world switch backend")
Reported-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

virt/kvm/arm/vgic/vgic-v2.c

@@ -50,6 +50,8 @@ void vgic_v2_process_maintenance(struct kvm_vcpu *vcpu)
 
 			WARN_ON(cpuif->vgic_lr[lr] & GICH_LR_STATE);
 
+			/* Only SPIs require notification */
+			if (vgic_valid_spi(vcpu->kvm, intid))
 				kvm_notify_acked_irq(vcpu->kvm, 0,
 						     intid - VGIC_NR_PRIVATE_IRQS);
 		}

virt/kvm/arm/vgic/vgic-v3.c

@@ -41,6 +41,8 @@ void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu)
 
 			WARN_ON(cpuif->vgic_lr[lr] & ICH_LR_STATE);
 
+			/* Only SPIs require notification */
+			if (vgic_valid_spi(vcpu->kvm, intid))
 				kvm_notify_acked_irq(vcpu->kvm, 0,
 						     intid - VGIC_NR_PRIVATE_IRQS);
 		}