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Commit 0943d92c authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Shawn Guo
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arm64: dts: freescale: use defines for interrupts 

Replace hard-coded interrupt parts (GIC, flags) with standard defines
for readability.  No changes in resulting DTBs.
Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarPeng Fan <peng.fan@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 152f7a99
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Showing with 181 additions and 181 deletions
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
View file @ 0943d92c
......@@ -74,15 +74,15 @@ coreclk: coreclk {
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
<1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
<1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
<1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@1400000 {
......@@ -93,7 +93,7 @@ gic: interrupt-controller@1400000 {
<0x0 0x1402000 0 0x2000>, /* GICC */
<0x0 0x1404000 0 0x2000>, /* GICH */
<0x0 0x1406000 0 0x2000>; /* GICV */
interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
reboot {
......@@ -159,7 +159,7 @@ QORIQ_CLK_PLL_DIV(1)>,
esdhc0: esdhc@1560000 {
compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
reg = <0x0 0x1560000 0x0 0x10000>;
interrupts = <0 62 0x4>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
voltage-ranges = <1800 1800 3300 3300>;
......@@ -178,7 +178,7 @@ scfg: scfg@1570000 {
esdhc1: esdhc@1580000 {
compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
reg = <0x0 0x1580000 0x0 0x10000>;
interrupts = <0 65 0x4>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
voltage-ranges = <1800 1800 3300 3300>;
......@@ -305,7 +305,7 @@ clockgen: clocking@1ee1000 {
tmu: tmu@1f00000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f00000 0x0 0x10000>;
interrupts = <0 33 0x4>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x60062>;
fsl,tmu-calibration =
<0x00000000 0x00000025>,
......@@ -355,7 +355,7 @@ i2c0: i2c@2180000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
scl-gpios = <&gpio0 2 0>;
......@@ -367,7 +367,7 @@ i2c1: i2c@2190000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2190000 0x0 0x10000>;
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
scl-gpios = <&gpio0 13 0>;
......@@ -379,7 +379,7 @@ dspi: spi@2100000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
......@@ -391,7 +391,7 @@ dspi: spi@2100000 {
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0500 0x0 0x100>;
interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
status = "disabled";
......@@ -400,7 +400,7 @@ duart0: serial@21c0500 {
duart1: serial@21c0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0600 0x0 0x100>;
interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
status = "disabled";
......@@ -409,7 +409,7 @@ duart1: serial@21c0600 {
gpio0: gpio@2300000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
......@@ -419,7 +419,7 @@ gpio0: gpio@2300000 {
gpio1: gpio@2310000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
......@@ -430,7 +430,7 @@ wdog0: watchdog@2ad0000 {
compatible = "fsl,ls1012a-wdt",
"fsl,imx21-wdt";
reg = <0x0 0x2ad0000 0x0 0x10000>;
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>;
big-endian;
};
......@@ -439,7 +439,7 @@ sai1: sai@2b50000 {
#sound-dai-cells = <0>;
compatible = "fsl,vf610-sai";
reg = <0x0 0x2b50000 0x0 0x10000>;
interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>,
<&clockgen QORIQ_CLK_PLATFORM_PLL
......@@ -459,7 +459,7 @@ sai2: sai@2b60000 {
#sound-dai-cells = <0>;
compatible = "fsl,vf610-sai";
reg = <0x0 0x2b60000 0x0 0x10000>;
interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>,
<&clockgen QORIQ_CLK_PLATFORM_PLL
......@@ -481,8 +481,8 @@ edma0: dma-controller@2c00000 {
reg = <0x0 0x2c00000 0x0 0x10000>,
<0x0 0x2c10000 0x0 0x10000>,
<0x0 0x2c20000 0x0 0x10000>;
interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
<0 103 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma-tx", "edma-err";
dma-channels = <32>;
big-endian;
......@@ -496,7 +496,7 @@ QORIQ_CLK_PLL_DIV(4)>,
usb0: usb@2f00000 {
compatible = "snps,dwc3";
reg = <0x0 0x2f00000 0x0 0x10000>;
interrupts = <0 60 0x4>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
......@@ -509,7 +509,7 @@ sata: sata@3200000 {
reg = <0x0 0x3200000 0x0 0x10000>,
<0x0 0x20140520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
dma-coherent;
......@@ -519,7 +519,7 @@ sata: sata@3200000 {
usb1: usb@8600000 {
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
reg = <0x0 0x8600000 0x0 0x1000>;
interrupts = <0 139 0x4>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
phy_type = "ulpi";
};
......@@ -528,7 +528,7 @@ msi: msi-controller1@1572000 {
compatible = "fsl,ls1012a-msi";
reg = <0x0 0x1572000 0x0 0x8>;
msi-controller;
interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
};
pcie1: pcie@3400000 {
......@@ -536,8 +536,8 @@ pcie1: pcie@3400000 {
reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
<0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 118 0x4>, /* controller interrupt */
<0 117 0x4>; /* PME interrupt */
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
interrupt-names = "aer", "pme";
#address-cells = <3>;
#size-cells = <2>;
......
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View file @ 0943d92c
......@@ -859,8 +859,8 @@ QORIQ_CLK_PLL_DIV(16)>,
malidp0: display@f080000 {
compatible = "arm,mali-dp500";
reg = <0x0 0xf080000 0x0 0x10000>;
interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
<0 223 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "DE", "SE";
clocks = <&dpclk>,
<&clockgen QORIQ_CLK_HWACCEL 2>,
......@@ -1024,7 +1024,7 @@ dpclk: clock-controller@f1f0000 {
tmu: tmu@1f80000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f80000 0x0 0x10000>;
interrupts = <0 23 0x4>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
fsl,tmu-calibration =
<0x00000000 0x00000024>,
......
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View file @ 0943d92c
......@@ -441,7 +441,7 @@ clockgen: clocking@1ee1000 {
tmu: tmu@1f00000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f00000 0x0 0x10000>;
interrupts = <0 33 0x4>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
fsl,tmu-calibration =
/* Calibration data group 1 */
......
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
View file @ 0943d92c
......@@ -118,7 +118,7 @@ gic: interrupt-controller@6000000 {
<0x0 0x0c0c0000 0 0x2000>, /* GICC */
<0x0 0x0c0d0000 0 0x1000>, /* GICH */
<0x0 0x0c0e0000 0 0x20000>; /* GICV */
interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
......@@ -183,10 +183,10 @@ soc-crit {
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
<1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
<1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
<1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
};
pmu {
......@@ -280,7 +280,7 @@ sfp: efuse@1e80000 {
tmu: tmu@1f80000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f80000 0x0 0x10000>;
interrupts = <0 23 0x4>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
fsl,tmu-calibration =
/* Calibration data group 1 */
......@@ -347,7 +347,7 @@ duart0: serial@21c0500 {
reg = <0x0 0x21c0500 0x0 0x100>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
......@@ -356,14 +356,14 @@ duart1: serial@21c0600 {
reg = <0x0 0x21c0600 0x0 0x100>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
gpio0: gpio@2300000 {
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
gpio-controller;
#gpio-cells = <2>;
......@@ -374,7 +374,7 @@ gpio0: gpio@2300000 {
gpio1: gpio@2310000 {
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
gpio-controller;
#gpio-cells = <2>;
......@@ -385,7 +385,7 @@ gpio1: gpio@2310000 {
gpio2: gpio@2320000 {
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
gpio-controller;
#gpio-cells = <2>;
......@@ -396,7 +396,7 @@ gpio2: gpio@2320000 {
gpio3: gpio@2330000 {
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
gpio-controller;
#gpio-cells = <2>;
......@@ -407,7 +407,7 @@ gpio3: gpio@2330000 {
ifc: memory-controller@2240000 {
compatible = "fsl,ifc";
reg = <0x0 0x2240000 0x0 0x20000>;
interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
#address-cells = <2>;
#size-cells = <1>;
......@@ -419,7 +419,7 @@ i2c0: i2c@2000000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(8)>;
status = "disabled";
......@@ -430,7 +430,7 @@ i2c1: i2c@2010000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2010000 0x0 0x10000>;
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(8)>;
status = "disabled";
......@@ -441,7 +441,7 @@ i2c2: i2c@2020000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2020000 0x0 0x10000>;
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(8)>;
status = "disabled";
......@@ -452,7 +452,7 @@ i2c3: i2c@2030000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2030000 0x0 0x10000>;
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(8)>;
status = "disabled";
......@@ -477,7 +477,7 @@ QORIQ_CLK_PLL_DIV(4)>,
esdhc: esdhc@2140000 {
compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
reg = <0x0 0x2140000 0x0 0x10000>;
interrupts = <0 28 0x4>; /* Level high type */
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <0>;
clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
voltage-ranges = <1800 1800 3300 3300>;
......@@ -490,7 +490,7 @@ esdhc: esdhc@2140000 {
usb0: usb@3100000 {
compatible = "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
......@@ -501,7 +501,7 @@ usb0: usb@3100000 {
usb1: usb@3110000 {
compatible = "snps,dwc3";
reg = <0x0 0x3110000 0x0 0x10000>;
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
......@@ -514,7 +514,7 @@ sata: sata@3200000 {
reg = <0x0 0x3200000 0x0 0x10000>,
<0x7 0x100520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
dma-coherent;
......@@ -565,7 +565,7 @@ pcie1: pcie@3400000 {
reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
<0x20 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "aer";
#address-cells = <3>;
#size-cells = <2>;
......@@ -604,7 +604,7 @@ pcie2: pcie@3500000 {
reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
<0x28 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "aer";
#address-cells = <3>;
#size-cells = <2>;
......@@ -642,7 +642,7 @@ pcie3: pcie@3600000 {
reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
<0x30 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "aer";
#address-cells = <3>;
#size-cells = <2>;
......
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
View file @ 0943d92c
......@@ -15,7 +15,7 @@
/ {
pmu {
compatible = "arm,cortex-a57-pmu";
interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
};
......
arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
View file @ 0943d92c
......@@ -15,7 +15,7 @@
/ {
pmu {
compatible = "arm,cortex-a72-pmu";
interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
};
......
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View file @ 0943d92c
......@@ -928,7 +928,7 @@ dspi2: spi@2120000 {
esdhc0: esdhc@2140000 {
compatible = "fsl,esdhc";
reg = <0x0 0x2140000 0x0 0x10000>;
interrupts = <0 28 0x4>; /* Level high type */
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
dma-coherent;
......@@ -942,7 +942,7 @@ esdhc0: esdhc@2140000 {
esdhc1: esdhc@2150000 {
compatible = "fsl,esdhc";
reg = <0x0 0x2150000 0x0 0x10000>;
interrupts = <0 63 0x4>; /* Level high type */
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
dma-coherent;
......
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