Commit 0cb26ec3 authored by Sean Christopherson's avatar Sean Christopherson

KVM: selftests: Verify the guest can read back the x2APIC ICR it wrote

Now that the BUSY bit mess is gone (for x2APIC), verify that the *guest*
can read back the ICR value that it wrote.  Due to the divergent
behavior between AMD and Intel with respect to the backing storage of the
ICR in the vAPIC page, emulating a seemingly simple MSR write is quite
complex.

Link: https://lore.kernel.org/r/20240719235107.3023592-10-seanjc@google.comSigned-off-by: default avatarSean Christopherson <seanjc@google.com>
parent 3426cb48
...@@ -45,10 +45,12 @@ static void x2apic_guest_code(void) ...@@ -45,10 +45,12 @@ static void x2apic_guest_code(void)
uint64_t val = x2apic_read_reg(APIC_IRR) | uint64_t val = x2apic_read_reg(APIC_IRR) |
x2apic_read_reg(APIC_IRR + 0x10) << 32; x2apic_read_reg(APIC_IRR + 0x10) << 32;
if (val & X2APIC_RSVD_BITS_MASK) if (val & X2APIC_RSVD_BITS_MASK) {
x2apic_write_reg_fault(APIC_ICR, val); x2apic_write_reg_fault(APIC_ICR, val);
else } else {
x2apic_write_reg(APIC_ICR, val); x2apic_write_reg(APIC_ICR, val);
GUEST_ASSERT_EQ(x2apic_read_reg(APIC_ICR), val);
}
GUEST_SYNC(val); GUEST_SYNC(val);
} while (1); } while (1);
} }
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment