Commit 0db5ee73 authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'ti-k3-soc-for-v5.7' of...

Merge tag 'ti-k3-soc-for-v5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into arm/dt

Texas Instruments K3 SoC family changes for v5.7

- Add missing clocks to dwc3 nodes on am65x (fixes USB)
- Add DMA entries for main_spi0 on am65x
- Add phy-gmii-sel nodes for both am65x and j721e (towards ethernet
  support)
- Add DMA entries for ADC for both am65x and j721e
- Add MCU system control module on j721e (needed by phy-gmii-sel)

* tag 'ti-k3-soc-for-v5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
  arm64: dts: ti: k3-j721e-mcu: add scm node and phy-gmii-sel nodes
  arm64: dts: ti: k3-am65-mcu: add phy-gmii-sel node
  arm64: dts: ti: k3-am65-mcu: Add DMA entries for ADC
  arm64: dts: ti: k3-am65-main: Add DMA entries for main_spi0
  arm64: dts: ti: k3-j721e-mcu-wakeup: Add DMA entries for ADC
  arm64: dts: ti: k3-am65: Add clocks to dwc3 nodes

Link: https://lore.kernel.org/r/4b6b7804-4bcb-07ba-5e76-6a411e1f457f@ti.comSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents c1cf2b3d ad3bcb0f
...@@ -189,6 +189,8 @@ main_spi0: spi@2100000 { ...@@ -189,6 +189,8 @@ main_spi0: spi@2100000 {
power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
dma-names = "tx0", "rx0";
}; };
main_spi1: spi@2110000 { main_spi1: spi@2110000 {
...@@ -296,6 +298,7 @@ dwc3_0: dwc3@4000000 { ...@@ -296,6 +298,7 @@ dwc3_0: dwc3@4000000 {
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent; dma-coherent;
power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
<&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
...@@ -335,6 +338,7 @@ dwc3_1: dwc3@4020000 { ...@@ -335,6 +338,7 @@ dwc3_1: dwc3@4020000 {
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent; dma-coherent;
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 152 2>;
assigned-clocks = <&k3_clks 152 2>; assigned-clocks = <&k3_clks 152 2>;
assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
......
...@@ -12,6 +12,12 @@ mcu_conf: scm_conf@40f00000 { ...@@ -12,6 +12,12 @@ mcu_conf: scm_conf@40f00000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x0 0x40f00000 0x20000>; ranges = <0x0 0x0 0x40f00000 0x20000>;
phy_gmii_sel: phy@4040 {
compatible = "ti,am654-phy-gmii-sel";
reg = <0x4040 0x4>;
#phy-cells = <1>;
};
}; };
mcu_uart0: serial@40a00000 { mcu_uart0: serial@40a00000 {
...@@ -82,6 +88,9 @@ tscadc0: tscadc@40200000 { ...@@ -82,6 +88,9 @@ tscadc0: tscadc@40200000 {
assigned-clocks = <&k3_clks 0 2>; assigned-clocks = <&k3_clks 0 2>;
assigned-clock-rates = <60000000>; assigned-clock-rates = <60000000>;
clock-names = "adc_tsc_fck"; clock-names = "adc_tsc_fck";
dmas = <&mcu_udmap 0x7100>,
<&mcu_udmap 0x7101 >;
dma-names = "fifo0", "fifo1";
adc { adc {
#io-channel-cells = <1>; #io-channel-cells = <1>;
...@@ -97,6 +106,9 @@ tscadc1: tscadc@40210000 { ...@@ -97,6 +106,9 @@ tscadc1: tscadc@40210000 {
assigned-clocks = <&k3_clks 1 2>; assigned-clocks = <&k3_clks 1 2>;
assigned-clock-rates = <60000000>; assigned-clock-rates = <60000000>;
clock-names = "adc_tsc_fck"; clock-names = "adc_tsc_fck";
dmas = <&mcu_udmap 0x7102>,
<&mcu_udmap 0x7103>;
dma-names = "fifo0", "fifo1";
adc { adc {
#io-channel-cells = <1>; #io-channel-cells = <1>;
......
...@@ -34,6 +34,20 @@ k3_reset: reset-controller { ...@@ -34,6 +34,20 @@ k3_reset: reset-controller {
}; };
}; };
mcu_conf: syscon@40f00000 {
compatible = "syscon", "simple-mfd";
reg = <0x0 0x40f00000 0x0 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x40f00000 0x20000>;
phy_gmii_sel: phy@4040 {
compatible = "ti,am654-phy-gmii-sel";
reg = <0x4040 0x4>;
#phy-cells = <1>;
};
};
wkup_pmx0: pinmux@4301c000 { wkup_pmx0: pinmux@4301c000 {
compatible = "pinctrl-single"; compatible = "pinctrl-single";
/* Proxy 0 addressing */ /* Proxy 0 addressing */
...@@ -203,6 +217,9 @@ tscadc0: tscadc@40200000 { ...@@ -203,6 +217,9 @@ tscadc0: tscadc@40200000 {
assigned-clocks = <&k3_clks 0 3>; assigned-clocks = <&k3_clks 0 3>;
assigned-clock-rates = <60000000>; assigned-clock-rates = <60000000>;
clock-names = "adc_tsc_fck"; clock-names = "adc_tsc_fck";
dmas = <&main_udmap 0x7400>,
<&main_udmap 0x7401>;
dma-names = "fifo0", "fifo1";
adc { adc {
#io-channel-cells = <1>; #io-channel-cells = <1>;
...@@ -219,6 +236,9 @@ tscadc1: tscadc@40210000 { ...@@ -219,6 +236,9 @@ tscadc1: tscadc@40210000 {
assigned-clocks = <&k3_clks 1 3>; assigned-clocks = <&k3_clks 1 3>;
assigned-clock-rates = <60000000>; assigned-clock-rates = <60000000>;
clock-names = "adc_tsc_fck"; clock-names = "adc_tsc_fck";
dmas = <&main_udmap 0x7402>,
<&main_udmap 0x7403>;
dma-names = "fifo0", "fifo1";
adc { adc {
#io-channel-cells = <1>; #io-channel-cells = <1>;
......
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