Commit 1bc277f7 authored by Dmitry Kravkov's avatar Dmitry Kravkov Committed by David S. Miller

bnx2x: add RSS capability for GRE traffic

The patch drives FW to perform RSS for GRE traffic,
based on inner headers.
Signed-off-by: default avatarDmitry Kravkov <dmitry@broadcom.com>
Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent a848ade4
...@@ -973,6 +973,9 @@ static inline int bnx2x_func_start(struct bnx2x *bp) ...@@ -973,6 +973,9 @@ static inline int bnx2x_func_start(struct bnx2x *bp)
else /* CHIP_IS_E1X */ else /* CHIP_IS_E1X */
start_params->network_cos_mode = FW_WRR; start_params->network_cos_mode = FW_WRR;
start_params->gre_tunnel_mode = IPGRE_TUNNEL;
start_params->gre_tunnel_rss = GRE_INNER_HEADERS_RSS;
return bnx2x_func_state_change(bp, &func_params); return bnx2x_func_state_change(bp, &func_params);
} }
......
...@@ -5679,17 +5679,18 @@ static inline int bnx2x_func_send_start(struct bnx2x *bp, ...@@ -5679,17 +5679,18 @@ static inline int bnx2x_func_send_start(struct bnx2x *bp,
memset(rdata, 0, sizeof(*rdata)); memset(rdata, 0, sizeof(*rdata));
/* Fill the ramrod data with provided parameters */ /* Fill the ramrod data with provided parameters */
rdata->function_mode = (u8)start_params->mf_mode; rdata->function_mode = (u8)start_params->mf_mode;
rdata->sd_vlan_tag = cpu_to_le16(start_params->sd_vlan_tag); rdata->sd_vlan_tag = cpu_to_le16(start_params->sd_vlan_tag);
rdata->path_id = BP_PATH(bp); rdata->path_id = BP_PATH(bp);
rdata->network_cos_mode = start_params->network_cos_mode; rdata->network_cos_mode = start_params->network_cos_mode;
rdata->gre_tunnel_mode = start_params->gre_tunnel_mode;
/* rdata->gre_tunnel_rss = start_params->gre_tunnel_rss;
* No need for an explicit memory barrier here as long we would
* need to ensure the ordering of writing to the SPQ element /* No need for an explicit memory barrier here as long we would
* and updating of the SPQ producer which involves a memory * need to ensure the ordering of writing to the SPQ element
* read and we will have to put a full memory barrier there * and updating of the SPQ producer which involves a memory
* (inside bnx2x_sp_post()). * read and we will have to put a full memory barrier there
* (inside bnx2x_sp_post()).
*/ */
return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0, return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0,
......
...@@ -1123,6 +1123,15 @@ struct bnx2x_func_start_params { ...@@ -1123,6 +1123,15 @@ struct bnx2x_func_start_params {
/* Function cos mode */ /* Function cos mode */
u8 network_cos_mode; u8 network_cos_mode;
/* NVGRE classification enablement */
u8 nvgre_clss_en;
/* NO_GRE_TUNNEL/NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */
u8 gre_tunnel_mode;
/* GRE_OUTER_HEADERS_RSS/GRE_INNER_HEADERS_RSS/NVGRE_KEY_ENTROPY_RSS */
u8 gre_tunnel_rss;
}; };
struct bnx2x_func_switch_update_params { struct bnx2x_func_switch_update_params {
......
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