Merge http://lia64.bkbits.net/linux-ia64-release-2.6.10

into ppc970.osdl.org:/home/torvalds/v2.6/linux

arch/ia64/pci/pci.c

@@ -124,7 +124,7 @@ pci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val
 				  devfn, where, size, value);
 }
 
-static struct pci_ops pci_root_ops = {
+struct pci_ops pci_root_ops = {
 	.read = pci_read,
 	.write = pci_write,
 };

arch/ia64/sn/Makefile

@@ -4,9 +4,11 @@
 # License.  See the file "COPYING" in the main directory of this archive
 # for more details.
 #
-# Copyright (C) 2003 Silicon Graphics, Inc.  All Rights Reserved.
+# Copyright (C) 2004 Silicon Graphics, Inc.  All Rights Reserved.
 #
 # Makefile for the sn ia64 subplatform
 #
 
-obj-y += kernel/ io/
+CPPFLAGS += -I$(srctree)/arch/ia64/sn/include
+
+obj-y += kernel/ pci/

include/asm-ia64/sn/ioerror.h → arch/ia64/sn/include/ioerror.h

@@ -8,90 +8,6 @@
 #ifndef _ASM_IA64_SN_IOERROR_H
 #define _ASM_IA64_SN_IOERROR_H
 
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-#include <asm/sn/types.h>
-
-/*
- * Macros defining the various Errors to be handled as part of
- * IO Error handling.
- */
-
-/*
- * List of errors to be handled by each subsystem.
- * "error_code" field will take one of these values.
- * The error code is built up of single bits expressing
- * our confidence that the error was that type; note
- * that it is possible to have a PIO or DMA error where
- * we don't know whether it was a READ or a WRITE, or
- * even a READ or WRITE error that we're not sure whether
- * to call a PIO or DMA.
- *
- * It is also possible to set both PIO and DMA, and possible
- * to set both READ and WRITE; the first may be nonsensical
- * but the second *could* be used to designate an access
- * that is known to be a read-modify-write cycle. It is
- * quite possible that nobody will ever use PIO|DMA or
- * READ|WRITE ... but being flexible is good.
- */
-#define	IOECODE_UNSPEC		0
-#define	IOECODE_READ		1
-#define	IOECODE_WRITE		2
-#define	IOECODE_PIO		4
-#define	IOECODE_DMA		8
-
-#define	IOECODE_PIO_READ	(IOECODE_PIO|IOECODE_READ)
-#define	IOECODE_PIO_WRITE	(IOECODE_PIO|IOECODE_WRITE)
-#define	IOECODE_DMA_READ	(IOECODE_DMA|IOECODE_READ)
-#define	IOECODE_DMA_WRITE	(IOECODE_DMA|IOECODE_WRITE)
-
-/* support older names, but try to move everything
- * to using new names that identify which package
- * controls their values ...
- */
-#define	PIO_READ_ERROR		IOECODE_PIO_READ
-#define	PIO_WRITE_ERROR		IOECODE_PIO_WRITE
-#define	DMA_READ_ERROR		IOECODE_DMA_READ
-#define	DMA_WRITE_ERROR		IOECODE_DMA_WRITE
-
-/*
- * List of error numbers returned by error handling sub-system.
- */
-
-#define	IOERROR_HANDLED		0	/* Error Properly handled.        */
-#define	IOERROR_NODEV		0x1	/* No such device attached        */
-#define	IOERROR_BADHANDLE	0x2	/* Received bad handle            */
-#define	IOERROR_BADWIDGETNUM	0x3	/* Bad widget number              */
-#define	IOERROR_BADERRORCODE	0x4	/* Bad error code passed in       */
-#define	IOERROR_INVALIDADDR	0x5	/* Invalid address specified      */
-
-#define	IOERROR_WIDGETLEVEL	0x6	/* Some failure at widget level    */
-#define	IOERROR_XTALKLEVEL	0x7
-
-#define	IOERROR_HWGRAPH_LOOKUP	0x8	/* hwgraph lookup failed for path  */
-#define	IOERROR_UNHANDLED	0x9	/* handler rejected error          */
-
-#define	IOERROR_PANIC		0xA	/* subsidiary handler has already
-					 * started decode: continue error
-					 * data dump, and panic from top
-					 * caller in error chain.
-					 */
-
-/*
- * IO errors at the bus/device driver level
- */
-
-#define	IOERROR_DEV_NOTFOUND	0x10	/* Device matching bus addr not found */
-#define	IOERROR_DEV_SHUTDOWN	0x11	/* Device has been shutdown        */
-
-/*
- * Type of address.
- * Indicates the direction of transfer that caused the error.
- */
-#define	IOERROR_ADDR_PIO	1	/* Error Address generated due to PIO */
-#define	IOERROR_ADDR_DMA	2	/* Error address generated due to DMA */
-
 /*
  * IO error structure.
  *
@@ -153,7 +69,7 @@ typedef struct io_error_s {
     iopaddr_t               ie_busspace;	/* Bus specific address space    */
     iopaddr_t               ie_busaddr;		/* Bus specific address          */
     caddr_t                 ie_vaddr;	/* Virtual address of error      */
-    paddr_t                 ie_memaddr;		/* Physical memory address       */
+    iopaddr_t               ie_memaddr;		/* Physical memory address       */
     caddr_t		    ie_epc;		/* pc when error reported	 */
     caddr_t		    ie_ef;		/* eframe when error reported	 */
     short		    ie_tnum;		/* Xtalk TNUM field */
@@ -161,33 +77,5 @@ typedef struct io_error_s {
 
 #define	IOERROR_INIT(e)		do { (e)->ie_v.iev_a = 0; } while (0)
 #define	IOERROR_SETVALUE(e,f,v)	do { (e)->ie_ ## f = (v); (e)->ie_v.iev_b.ievb_ ## f = 1; } while (0)
-#define	IOERROR_FIELDVALID(e,f)	((unsigned long long)((e)->ie_v.iev_b.ievb_ ## f) != (unsigned long long) 0)
-#define	IOERROR_NOGETVALUE(e,f)	(ASSERT(IOERROR_FIELDVALID(e,f)), ((e)->ie_ ## f))
-#define	IOERROR_GETVALUE(p,e,f)	ASSERT(IOERROR_FIELDVALID(e,f)); p=((e)->ie_ ## f)
-
-/* hub code likes to call the SysAD address "hubaddr" ... */
-#define	ie_hubaddr	ie_sysioaddr
-#define	ievb_hubaddr	ievb_sysioaddr
-#endif
-
-/*
- * Error handling Modes.
- */
-typedef enum {
-    MODE_DEVPROBE,		/* Probing mode. Errors not fatal */
-    MODE_DEVERROR,		/* Error while system is running */
-    MODE_DEVUSERERROR,		/* Device Error created due to user mode access */
-    MODE_DEVREENABLE		/* Reenable pass                */
-} ioerror_mode_t;
-
-
-typedef int             error_handler_f(void *, int, ioerror_mode_t, ioerror_t *);
-typedef void           *error_handler_arg_t;
-
-#ifdef	ERROR_DEBUG
-#define	IOERR_PRINTF(x)	(x)
-#else
-#define	IOERR_PRINTF(x)
-#endif				/* ERROR_DEBUG */
 
 #endif /* _ASM_IA64_SN_IOERROR_H */

arch/ia64/sn/include/pci/pcibr_provider.h

+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992-1997,2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
+#define _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
+
+/* Workarounds */
+#define PV907516 (1 << 1) /* TIOCP: Don't write the write buffer flush reg */
+
+#define BUSTYPE_MASK                    0x1
+
+/* Macros given a pcibus structure */
+#define IS_PCIX(ps)     ((ps)->pbi_bridge_mode & BUSTYPE_MASK)
+#define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \
+                asic == PCIIO_ASIC_TYPE_TIOCP)
+#define IS_PIC_SOFT(ps)     (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC)
+
+
+/* 
+ * The different PCI Bridge types supported on the SGI Altix platforms
+ */
+#define PCIBR_BRIDGETYPE_UNKNOWN       -1
+#define PCIBR_BRIDGETYPE_PIC            2
+#define PCIBR_BRIDGETYPE_TIOCP          3
+
+/*
+ * Bridge 64bit Direct Map Attributes
+ */
+#define PCI64_ATTR_PREF                 (1ull << 59)
+#define PCI64_ATTR_PREC                 (1ull << 58)
+#define PCI64_ATTR_VIRTUAL              (1ull << 57)
+#define PCI64_ATTR_BAR                  (1ull << 56)
+#define PCI64_ATTR_SWAP                 (1ull << 55)
+#define PCI64_ATTR_VIRTUAL1             (1ull << 54)
+
+#define PCI32_LOCAL_BASE                0
+#define PCI32_MAPPED_BASE               0x40000000
+#define PCI32_DIRECT_BASE               0x80000000
+
+#define IS_PCI32_MAPPED(x)              ((uint64_t)(x) < PCI32_DIRECT_BASE && \
+                                         (uint64_t)(x) >= PCI32_MAPPED_BASE)
+#define IS_PCI32_DIRECT(x)              ((uint64_t)(x) >= PCI32_MAPPED_BASE)
+
+
+/*
+ * Bridge PMU Address Transaltion Entry Attibutes
+ */
+#define PCI32_ATE_V                     (0x1 << 0)
+#define PCI32_ATE_CO                    (0x1 << 1)
+#define PCI32_ATE_PREC                  (0x1 << 2)
+#define PCI32_ATE_PREF                  (0x1 << 3)
+#define PCI32_ATE_BAR                   (0x1 << 4)
+#define PCI32_ATE_ADDR_SHFT             12
+
+#define MINIMAL_ATES_REQUIRED(addr, size) \
+	(IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1))
+
+#define MINIMAL_ATE_FLAG(addr, size) \
+	(MINIMAL_ATES_REQUIRED((uint64_t)addr, size) ? 1 : 0)
+
+/* bit 29 of the pci address is the SWAP bit */
+#define ATE_SWAPSHIFT                   29
+#define ATE_SWAP_ON(x)                  ((x) |= (1 << ATE_SWAPSHIFT))
+#define ATE_SWAP_OFF(x)                 ((x) &= ~(1 << ATE_SWAPSHIFT))
+
+/*
+ * I/O page size
+ */
+#if PAGE_SIZE < 16384
+#define IOPFNSHIFT                      12      /* 4K per mapped page */
+#else
+#define IOPFNSHIFT                      14      /* 16K per mapped page */
+#endif
+
+#define IOPGSIZE                        (1 << IOPFNSHIFT)
+#define IOPG(x)                         ((x) >> IOPFNSHIFT)
+#define IOPGOFF(x)                      ((x) & (IOPGSIZE-1))
+
+#define PCIBR_DEV_SWAP_DIR              (1ull << 19)
+#define PCIBR_CTRL_PAGE_SIZE            (0x1 << 21)
+
+/*
+ * PMU resources.
+ */
+struct ate_resource{
+	uint64_t *ate;
+	uint64_t num_ate;
+	uint64_t lowest_free_index;
+};
+
+struct pcibus_info {
+	struct pcibus_bussoft	pbi_buscommon;   /* common header */
+	uint32_t                pbi_moduleid;
+	short                   pbi_bridge_type;
+	short                   pbi_bridge_mode;
+
+	struct ate_resource     pbi_int_ate_resource;
+	uint64_t                pbi_int_ate_size;
+	
+	uint64_t                pbi_dir_xbase;
+	char                    pbi_hub_xid;
+
+	uint64_t                pbi_devreg[8];
+	spinlock_t              pbi_lock;
+
+	uint32_t		pbi_valid_devices;
+	uint32_t		pbi_enabled_devices;
+};
+
+/*
+ * pcibus_info structure locking macros
+ */
+inline static unsigned long
+pcibr_lock(struct pcibus_info *pcibus_info)
+{
+	unsigned long flag;
+	spin_lock_irqsave(&pcibus_info->pbi_lock, flag);
+	return(flag);
+}
+#define pcibr_unlock(pcibus_info, flag)  spin_unlock_irqrestore(&pcibus_info->pbi_lock, flag)
+
+extern void *pcibr_bus_fixup(struct pcibus_bussoft *);
+extern uint64_t pcibr_dma_map(struct pcidev_info *, unsigned long, size_t, unsigned int);
+extern void pcibr_dma_unmap(struct pcidev_info *, dma_addr_t, int);
+
+/*
+ * prototypes for the bridge asic register access routines in pcibr_reg.c
+ */
+extern void             pcireg_control_bit_clr(struct pcibus_info *, uint64_t);
+extern void             pcireg_control_bit_set(struct pcibus_info *, uint64_t);
+extern uint64_t         pcireg_tflush_get(struct pcibus_info *);
+extern uint64_t         pcireg_intr_status_get(struct pcibus_info *);
+extern void             pcireg_intr_enable_bit_clr(struct pcibus_info *, uint64_t);
+extern void             pcireg_intr_enable_bit_set(struct pcibus_info *, uint64_t);
+extern void             pcireg_intr_addr_addr_set(struct pcibus_info *, int, uint64_t);
+extern void             pcireg_force_intr_set(struct pcibus_info *, int);
+extern uint64_t         pcireg_wrb_flush_get(struct pcibus_info *, int);
+extern void             pcireg_int_ate_set(struct pcibus_info *, int, uint64_t);
+extern uint64_t *	pcireg_int_ate_addr(struct pcibus_info *, int);
+extern void 		pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
+extern void 		pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
+extern int 		pcibr_ate_alloc(struct pcibus_info *, int);
+extern void 		pcibr_ate_free(struct pcibus_info *, int);
+extern void 		ate_write(struct pcibus_info *, int, int, uint64_t);
+#endif

arch/ia64/sn/include/pci/pcibus_provider_defs.h

+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
+#define _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
+
+/*
+ * SN pci asic types.  Do not ever renumber these or reuse values.  The
+ * values must agree with what prom thinks they are.
+ */
+
+#define PCIIO_ASIC_TYPE_UNKNOWN	0
+#define PCIIO_ASIC_TYPE_PPB	1
+#define PCIIO_ASIC_TYPE_PIC	2
+#define PCIIO_ASIC_TYPE_TIOCP	3
+
+/*
+ * Common pciio bus provider data.  There should be one of these as the
+ * first field in any pciio based provider soft structure (e.g. pcibr_soft
+ * tioca_soft, etc).
+ */
+
+struct pcibus_bussoft {
+	uint32_t		bs_asic_type;	/* chipset type */
+	uint32_t		bs_xid;		/* xwidget id */
+	uint64_t		bs_persist_busnum; /* Persistent Bus Number */
+	uint64_t		bs_legacy_io;	/* legacy io pio addr */
+	uint64_t		bs_legacy_mem;	/* legacy mem pio addr */
+	uint64_t		bs_base;	/* widget base */
+	struct xwidget_info	*bs_xwidget_info;
+};
+
+/*
+ * DMA mapping flags
+ */
+
+#define SN_PCIDMA_CONSISTENT    0x0001
+
+#endif				/* _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H */

arch/ia64/sn/include/pci/pcidev.h

+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_PCI_PCIDEV_H
+#define _ASM_IA64_SN_PCI_PCIDEV_H
+
+#include <linux/pci.h>
+
+extern struct sn_irq_info **sn_irq;
+
+#define SN_PCIDEV_INFO(pci_dev) \
+        ((struct pcidev_info *)((pci_dev)->sysdata))
+
+/*
+ * Given a pci_bus, return the sn pcibus_bussoft struct.  Note that
+ * this only works for root busses, not for busses represented by PPB's.
+ */
+
+#define SN_PCIBUS_BUSSOFT(pci_bus) \
+        ((struct pcibus_bussoft *)(PCI_CONTROLLER((pci_bus))->platform_data))
+
+/*
+ * Given a struct pci_dev, return the sn pcibus_bussoft struct.  Note
+ * that this is not equivalent to SN_PCIBUS_BUSSOFT(pci_dev->bus) due
+ * due to possible PPB's in the path.
+ */
+
+#define SN_PCIDEV_BUSSOFT(pci_dev) \
+	(SN_PCIDEV_INFO(pci_dev)->pdi_host_pcidev_info->pdi_pcibus_info)
+
+#define PCIIO_BUS_NONE	255      /* bus 255 reserved */
+#define PCIIO_SLOT_NONE 255
+#define PCIIO_FUNC_NONE 255
+#define PCIIO_VENDOR_ID_NONE	(-1)
+
+struct pcidev_info {
+	uint64_t		pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */
+	uint64_t		pdi_slot_host_handle;	/* Bus and devfn Host pci_dev */
+
+	struct pcibus_bussoft	*pdi_pcibus_info;	/* Kernel common bus soft */
+	struct pcidev_info	*pdi_host_pcidev_info;	/* Kernel Host pci_dev */
+	struct pci_dev		*pdi_linux_pcidev;	/* Kernel pci_dev */
+
+	struct sn_irq_info	*pdi_sn_irq_info;
+};
+
+#endif				/* _ASM_IA64_SN_PCI_PCIDEV_H */

arch/ia64/sn/include/pci/tiocp.h

+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_PCI_TIOCP_H
+#define _ASM_IA64_SN_PCI_TIOCP_H
+
+#define TIOCP_HOST_INTR_ADDR            0x003FFFFFFFFFFFFF
+#define TIOCP_PCI64_CMDTYPE_MEM         (0x1ull << 60)
+
+
+/*****************************************************************************
+ *********************** TIOCP MMR structure mapping ***************************
+ *****************************************************************************/
+
+struct tiocp{
+
+    /* 0x000000-0x00FFFF -- Local Registers */
+
+    /* 0x000000-0x000057 -- (Legacy Widget Space) Configuration */
+    uint64_t		cp_id;				/* 0x000000 */
+    uint64_t		cp_stat;			/* 0x000008 */
+    uint64_t		cp_err_upper;			/* 0x000010 */
+    uint64_t		cp_err_lower;			/* 0x000018 */
+    #define cp_err cp_err_lower
+    uint64_t		cp_control;			/* 0x000020 */
+    uint64_t		cp_req_timeout;			/* 0x000028 */
+    uint64_t		cp_intr_upper;			/* 0x000030 */
+    uint64_t		cp_intr_lower;			/* 0x000038 */
+    #define cp_intr cp_intr_lower
+    uint64_t		cp_err_cmdword;			/* 0x000040 */
+    uint64_t		_pad_000048;			/* 0x000048 */
+    uint64_t		cp_tflush;			/* 0x000050 */
+
+    /* 0x000058-0x00007F -- Bridge-specific Configuration */
+    uint64_t		cp_aux_err;			/* 0x000058 */
+    uint64_t		cp_resp_upper;			/* 0x000060 */
+    uint64_t		cp_resp_lower;			/* 0x000068 */
+    #define cp_resp cp_resp_lower
+    uint64_t		cp_tst_pin_ctrl;		/* 0x000070 */
+    uint64_t		cp_addr_lkerr;			/* 0x000078 */
+
+    /* 0x000080-0x00008F -- PMU & MAP */
+    uint64_t		cp_dir_map;			/* 0x000080 */
+    uint64_t		_pad_000088;			/* 0x000088 */
+
+    /* 0x000090-0x00009F -- SSRAM */
+    uint64_t		cp_map_fault;			/* 0x000090 */
+    uint64_t		_pad_000098;			/* 0x000098 */
+
+    /* 0x0000A0-0x0000AF -- Arbitration */
+    uint64_t		cp_arb;				/* 0x0000A0 */
+    uint64_t		_pad_0000A8;			/* 0x0000A8 */
+
+    /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
+    uint64_t		cp_ate_parity_err;		/* 0x0000B0 */
+    uint64_t		_pad_0000B8;			/* 0x0000B8 */
+
+    /* 0x0000C0-0x0000FF -- PCI/GIO */
+    uint64_t		cp_bus_timeout;			/* 0x0000C0 */
+    uint64_t		cp_pci_cfg;			/* 0x0000C8 */
+    uint64_t		cp_pci_err_upper;		/* 0x0000D0 */
+    uint64_t		cp_pci_err_lower;		/* 0x0000D8 */
+    #define cp_pci_err cp_pci_err_lower
+    uint64_t		_pad_0000E0[4];			/* 0x0000{E0..F8} */
+
+    /* 0x000100-0x0001FF -- Interrupt */
+    uint64_t		cp_int_status;			/* 0x000100 */
+    uint64_t		cp_int_enable;			/* 0x000108 */
+    uint64_t		cp_int_rst_stat;		/* 0x000110 */
+    uint64_t		cp_int_mode;			/* 0x000118 */
+    uint64_t		cp_int_device;			/* 0x000120 */
+    uint64_t		cp_int_host_err;		/* 0x000128 */
+    uint64_t		cp_int_addr[8];			/* 0x0001{30,,,68} */
+    uint64_t		cp_err_int_view;		/* 0x000170 */
+    uint64_t		cp_mult_int;			/* 0x000178 */
+    uint64_t		cp_force_always[8];		/* 0x0001{80,,,B8} */
+    uint64_t		cp_force_pin[8];		/* 0x0001{C0,,,F8} */
+
+    /* 0x000200-0x000298 -- Device */
+    uint64_t		cp_device[4];			/* 0x0002{00,,,18} */
+    uint64_t		_pad_000220[4];			/* 0x0002{20,,,38} */
+    uint64_t		cp_wr_req_buf[4];		/* 0x0002{40,,,58} */
+    uint64_t		_pad_000260[4];			/* 0x0002{60,,,78} */
+    uint64_t		cp_rrb_map[2];			/* 0x0002{80,,,88} */
+    #define cp_even_resp cp_rrb_map[0]			/* 0x000280 */
+    #define cp_odd_resp  cp_rrb_map[1]			/* 0x000288 */
+    uint64_t		cp_resp_status;			/* 0x000290 */
+    uint64_t		cp_resp_clear;			/* 0x000298 */
+
+    uint64_t		_pad_0002A0[12];		/* 0x0002{A0..F8} */
+
+    /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
+    struct {
+	uint64_t	upper;				/* 0x0003{00,,,F0} */
+	uint64_t	lower;				/* 0x0003{08,,,F8} */
+    } cp_buf_addr_match[16];
+
+    /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
+    struct {
+	uint64_t	flush_w_touch;			/* 0x000{400,,,5C0} */
+	uint64_t	flush_wo_touch;			/* 0x000{408,,,5C8} */
+	uint64_t	inflight;			/* 0x000{410,,,5D0} */
+	uint64_t	prefetch;			/* 0x000{418,,,5D8} */
+	uint64_t	total_pci_retry;		/* 0x000{420,,,5E0} */
+	uint64_t	max_pci_retry;			/* 0x000{428,,,5E8} */
+	uint64_t	max_latency;			/* 0x000{430,,,5F0} */
+	uint64_t	clear_all;			/* 0x000{438,,,5F8} */
+    } cp_buf_count[8];
+
+    
+    /* 0x000600-0x0009FF -- PCI/X registers */
+    uint64_t		cp_pcix_bus_err_addr;		/* 0x000600 */
+    uint64_t		cp_pcix_bus_err_attr;		/* 0x000608 */
+    uint64_t		cp_pcix_bus_err_data;		/* 0x000610 */
+    uint64_t		cp_pcix_pio_split_addr;		/* 0x000618 */
+    uint64_t		cp_pcix_pio_split_attr;		/* 0x000620 */
+    uint64_t		cp_pcix_dma_req_err_attr;	/* 0x000628 */
+    uint64_t		cp_pcix_dma_req_err_addr;	/* 0x000630 */
+    uint64_t		cp_pcix_timeout;		/* 0x000638 */
+
+    uint64_t		_pad_000640[24];		/* 0x000{640,,,6F8} */
+
+    /* 0x000700-0x000737 -- Debug Registers */
+    uint64_t		cp_ct_debug_ctl;		/* 0x000700 */
+    uint64_t		cp_br_debug_ctl;		/* 0x000708 */
+    uint64_t		cp_mux3_debug_ctl;		/* 0x000710 */
+    uint64_t		cp_mux4_debug_ctl;		/* 0x000718 */
+    uint64_t		cp_mux5_debug_ctl;		/* 0x000720 */
+    uint64_t		cp_mux6_debug_ctl;		/* 0x000728 */
+    uint64_t		cp_mux7_debug_ctl;		/* 0x000730 */
+
+    uint64_t		_pad_000738[89];		/* 0x000{738,,,9F8} */
+
+    /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
+    struct {
+	uint64_t	cp_buf_addr;			/* 0x000{A00,,,AF0} */
+	uint64_t	cp_buf_attr;			/* 0X000{A08,,,AF8} */
+    } cp_pcix_read_buf_64[16];
+
+    struct {
+	uint64_t	cp_buf_addr;			/* 0x000{B00,,,BE0} */
+	uint64_t	cp_buf_attr;			/* 0x000{B08,,,BE8} */
+	uint64_t	cp_buf_valid;			/* 0x000{B10,,,BF0} */
+	uint64_t	__pad1;				/* 0x000{B18,,,BF8} */
+    } cp_pcix_write_buf_64[8];
+
+    /* End of Local Registers -- Start of Address Map space */
+
+    char		_pad_000c00[0x010000 - 0x000c00];
+
+    /* 0x010000-0x011FF8 -- Internal ATE RAM (Auto Parity Generation) */
+    uint64_t		cp_int_ate_ram[1024];		/* 0x010000-0x011FF8 */
+
+    char		_pad_012000[0x14000 - 0x012000];
+
+    /* 0x014000-0x015FF8 -- Internal ATE RAM (Manual Parity Generation) */
+    uint64_t		cp_int_ate_ram_mp[1024];	/* 0x014000-0x015FF8 */
+
+    char		_pad_016000[0x18000 - 0x016000];
+
+    /* 0x18000-0x197F8 -- TIOCP Write Request Ram */
+    uint64_t		cp_wr_req_lower[256];		/* 0x18000 - 0x187F8 */
+    uint64_t		cp_wr_req_upper[256];		/* 0x18800 - 0x18FF8 */
+    uint64_t		cp_wr_req_parity[256];		/* 0x19000 - 0x197F8 */
+
+    char		_pad_019800[0x1C000 - 0x019800];
+
+    /* 0x1C000-0x1EFF8 -- TIOCP Read Response Ram */
+    uint64_t		cp_rd_resp_lower[512];		/* 0x1C000 - 0x1CFF8 */
+    uint64_t		cp_rd_resp_upper[512];		/* 0x1D000 - 0x1DFF8 */
+    uint64_t		cp_rd_resp_parity[512];		/* 0x1E000 - 0x1EFF8 */
+
+    char		_pad_01F000[0x20000 - 0x01F000];
+
+    /* 0x020000-0x021FFF -- Host Device (CP) Configuration Space (not used)  */
+    char		_pad_020000[0x021000 - 0x20000];
+
+    /* 0x021000-0x027FFF -- PCI Device Configuration Spaces */
+    union {
+	uint8_t		c[0x1000 / 1];			/* 0x02{0000,,,7FFF} */
+	uint16_t	s[0x1000 / 2];			/* 0x02{0000,,,7FFF} */
+	uint32_t	l[0x1000 / 4];			/* 0x02{0000,,,7FFF} */
+	uint64_t	d[0x1000 / 8];			/* 0x02{0000,,,7FFF} */
+	union {
+	    uint8_t	c[0x100 / 1];
+	    uint16_t	s[0x100 / 2];
+	    uint32_t	l[0x100 / 4];
+	    uint64_t	d[0x100 / 8];
+	} f[8];
+    } cp_type0_cfg_dev[7];				/* 0x02{1000,,,7FFF} */
+
+    /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
+    union {
+	uint8_t		c[0x1000 / 1];			/* 0x028000-0x029000 */
+	uint16_t	s[0x1000 / 2];			/* 0x028000-0x029000 */
+	uint32_t	l[0x1000 / 4];			/* 0x028000-0x029000 */
+	uint64_t	d[0x1000 / 8];			/* 0x028000-0x029000 */
+	union {
+	    uint8_t	c[0x100 / 1];
+	    uint16_t	s[0x100 / 2];
+	    uint32_t	l[0x100 / 4];
+	    uint64_t	d[0x100 / 8];
+	} f[8];
+    } cp_type1_cfg;					/* 0x028000-0x029000 */
+
+    char		_pad_029000[0x030000-0x029000];
+
+    /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
+    union {
+	uint8_t		c[8 / 1];
+	uint16_t	s[8 / 2];
+	uint32_t	l[8 / 4];
+	uint64_t	d[8 / 8];
+    } cp_pci_iack;					/* 0x030000-0x030007 */
+
+    char		_pad_030007[0x040000-0x030008];
+
+    /* 0x040000-0x040007 -- PCIX Special Cycle */
+    union {
+	uint8_t		c[8 / 1];
+	uint16_t	s[8 / 2];
+	uint32_t	l[8 / 4];
+	uint64_t	d[8 / 8];
+    } cp_pcix_cycle;					/* 0x040000-0x040007 */
+
+    char		_pad_040007[0x200000-0x040008];
+
+    /* 0x200000-0x7FFFFF -- PCI/GIO Device Spaces */
+    union {
+	uint8_t		c[0x100000 / 1];
+	uint16_t	s[0x100000 / 2];
+	uint32_t	l[0x100000 / 4];
+	uint64_t	d[0x100000 / 8];
+    } cp_devio_raw[6];					/* 0x200000-0x7FFFFF */
+
+    #define cp_devio(n)  cp_devio_raw[((n)<2)?(n*2):(n+2)]
+
+    char		_pad_800000[0xA00000-0x800000];
+
+    /* 0xA00000-0xBFFFFF -- PCI/GIO Device Spaces w/flush  */
+    union {
+	uint8_t		c[0x100000 / 1];
+	uint16_t	s[0x100000 / 2];
+	uint32_t	l[0x100000 / 4];
+	uint64_t	d[0x100000 / 8];
+    } cp_devio_raw_flush[6];				/* 0xA00000-0xBFFFFF */
+
+    #define cp_devio_flush(n)  cp_devio_raw_flush[((n)<2)?(n*2):(n+2)]
+
+};
+
+#endif 	/* _ASM_IA64_SN_PCI_TIOCP_H */

include/asm-ia64/sn/sn2/shub.h → arch/ia64/sn/include/shub.h

@@ -3,12 +3,15 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (c) 2001-2003 Silicon Graphics, Inc.  All rights reserved.
+ * Copyright (c) 2001-2004 Silicon Graphics, Inc.  All rights reserved.
  */
 
+#ifndef _ASM_IA64_SN_SHUB_H
+#define _ASM_IA64_SN_SHUB_H
+
+
+#define MD_MEM_BANKS            4
 
-#ifndef _ASM_IA64_SN_SN2_SHUB_H
-#define _ASM_IA64_SN_SN2_SHUB_H
 
 /*
  * Junk Bus Address Space
@@ -33,4 +36,4 @@
 #define SH_JUNK_BUS_UART6               0x7fed40030
 #define SH_JUNK_BUS_UART7               0x7fed40038
 
-#endif /* _ASM_IA64_SN_SN2_SHUB_H */
+#endif /* _ASM_IA64_SN_SHUB_H */

arch/ia64/sn/include/tio.h

+/* 
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_TIO_H
+#define _ASM_IA64_SN_TIO_H
+
+#define	TIO_MMR_ADDR_MOD
+
+#define TIO_NODE_ID     TIO_MMR_ADDR_MOD(0x0000000090060e80)
+
+#define TIO_ITTE_BASE   0xb0008800        /* base of translation table entries */
+#define TIO_ITTE(bigwin)        (TIO_ITTE_BASE + 8*(bigwin))
+
+#define TIO_ITTE_OFFSET_BITS    8       /* size of offset field */
+#define TIO_ITTE_OFFSET_MASK    ((1<<TIO_ITTE_OFFSET_BITS)-1)
+#define TIO_ITTE_OFFSET_SHIFT   0
+
+#define TIO_ITTE_WIDGET_BITS    2       /* size of widget field */
+#define TIO_ITTE_WIDGET_MASK    ((1<<TIO_ITTE_WIDGET_BITS)-1)
+#define TIO_ITTE_WIDGET_SHIFT   12
+#define TIO_ITTE_VALID_MASK	0x1
+#define TIO_ITTE_VALID_SHIFT	16
+
+
+#define TIO_ITTE_PUT(nasid, bigwin, widget, addr, valid) \
+        REMOTE_HUB_S((nasid), TIO_ITTE(bigwin), \
+                (((((addr) >> TIO_BWIN_SIZE_BITS) & \
+                   TIO_ITTE_OFFSET_MASK) << TIO_ITTE_OFFSET_SHIFT) | \
+                (((widget) & TIO_ITTE_WIDGET_MASK) << TIO_ITTE_WIDGET_SHIFT)) | \
+		(( (valid) & TIO_ITTE_VALID_MASK) << TIO_ITTE_VALID_SHIFT))
+
+#endif /*  _ASM_IA64_SN_TIO_H */

arch/ia64/sn/include/xtalk/hubdev.h

+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_XTALK_HUBDEV_H
+#define _ASM_IA64_SN_XTALK_HUBDEV_H
+
+#define HUB_WIDGET_ID_MAX 0xf
+#define DEV_PER_WIDGET (2*2*8)
+#define IIO_ITTE_WIDGET_BITS    4       /* size of widget field */
+#define IIO_ITTE_WIDGET_MASK    ((1<<IIO_ITTE_WIDGET_BITS)-1)
+#define IIO_ITTE_WIDGET_SHIFT   8
+
+/*
+ * Use the top big window as a surrogate for the first small window
+ */
+#define SWIN0_BIGWIN            HUB_NUM_BIG_WINDOW
+#define IIO_NUM_ITTES   7
+#define HUB_NUM_BIG_WINDOW      (IIO_NUM_ITTES - 1)
+
+struct sn_flush_device_list {
+	int sfdl_bus;
+	int sfdl_slot;
+	int sfdl_pin;
+	struct bar_list {
+		unsigned long start;
+		unsigned long end;
+	} sfdl_bar_list[6];
+	unsigned long sfdl_force_int_addr;
+	unsigned long sfdl_flush_value;
+	volatile unsigned long *sfdl_flush_addr;
+	uint64_t sfdl_persistent_busnum;
+	struct pcibus_info *sfdl_pcibus_info;
+	spinlock_t sfdl_flush_lock;
+};
+
+/*
+ * **widget_p - Used as an array[wid_num][device] of sn_flush_device_list.
+ */
+struct sn_flush_nasid_entry  {
+	struct sn_flush_device_list **widget_p; /* Used as a array of wid_num */
+	uint64_t iio_itte[8];
+};
+
+struct hubdev_info {
+	geoid_t				hdi_geoid;
+	short				hdi_nasid;
+	short				hdi_peer_nasid;   /* Dual Porting Peer */
+
+	struct sn_flush_nasid_entry	hdi_flush_nasid_list;
+	struct xwidget_info		hdi_xwidget_info[HUB_WIDGET_ID_MAX + 1];
+
+
+	void				*hdi_nodepda;
+	void				*hdi_node_vertex;
+	void				*hdi_xtalk_vertex;
+};
+
+extern void hubdev_init_node(nodepda_t *, cnodeid_t);
+extern void hub_error_init(struct hubdev_info *);
+extern void ice_error_init(struct hubdev_info *);
+
+
+#endif /* _ASM_IA64_SN_XTALK_HUBDEV_H */

arch/ia64/sn/include/xtalk/xwidgetdev.h

+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All Rights Reserved.
+ */
+#ifndef _ASM_IA64_SN_XTALK_XWIDGET_H
+#define _ASM_IA64_SN_XTALK_XWIDGET_H
+
+/* WIDGET_ID */
+#define WIDGET_REV_NUM                  0xf0000000
+#define WIDGET_PART_NUM                 0x0ffff000
+#define WIDGET_MFG_NUM                  0x00000ffe
+#define WIDGET_REV_NUM_SHFT             28
+#define WIDGET_PART_NUM_SHFT            12
+#define WIDGET_MFG_NUM_SHFT             1
+
+#define XWIDGET_PART_NUM(widgetid) (((widgetid) & WIDGET_PART_NUM) >> WIDGET_PART_NUM_SHFT)
+#define XWIDGET_REV_NUM(widgetid) (((widgetid) & WIDGET_REV_NUM) >> WIDGET_REV_NUM_SHFT)
+#define XWIDGET_MFG_NUM(widgetid) (((widgetid) & WIDGET_MFG_NUM) >> WIDGET_MFG_NUM_SHFT)
+#define XWIDGET_PART_REV_NUM(widgetid) ((XWIDGET_PART_NUM(widgetid) << 4) | \
+                                        XWIDGET_REV_NUM(widgetid))
+#define XWIDGET_PART_REV_NUM_REV(partrev) (partrev & 0xf)
+
+/* widget configuration registers */
+struct widget_cfg{
+	uint32_t	w_id;	/* 0x04 */
+	uint32_t	w_pad_0;	/* 0x00 */
+	uint32_t	w_status;	/* 0x0c */
+	uint32_t	w_pad_1;	/* 0x08 */
+	uint32_t	w_err_upper_addr;	/* 0x14 */
+	uint32_t	w_pad_2;	/* 0x10 */
+	uint32_t	w_err_lower_addr;	/* 0x1c */
+	uint32_t	w_pad_3;	/* 0x18 */
+	uint32_t	w_control;	/* 0x24 */
+	uint32_t	w_pad_4;	/* 0x20 */
+	uint32_t	w_req_timeout;	/* 0x2c */
+	uint32_t	w_pad_5;	/* 0x28 */
+	uint32_t	w_intdest_upper_addr;	/* 0x34 */
+	uint32_t	w_pad_6;	/* 0x30 */
+	uint32_t	w_intdest_lower_addr;	/* 0x3c */
+	uint32_t	w_pad_7;	/* 0x38 */
+	uint32_t	w_err_cmd_word;	/* 0x44 */
+	uint32_t	w_pad_8;	/* 0x40 */
+	uint32_t	w_llp_cfg;	/* 0x4c */
+	uint32_t	w_pad_9;	/* 0x48 */
+	uint32_t	w_tflush;	/* 0x54 */
+	uint32_t	w_pad_10;	/* 0x50 */
+};
+
+/*
+ * Crosstalk Widget Hardware Identification, as defined in the Crosstalk spec.
+ */
+struct xwidget_hwid{
+	int		mfg_num;
+	int		rev_num;
+	int		part_num;
+};
+
+struct xwidget_info{
+
+	struct xwidget_hwid	xwi_hwid;	/* Widget Identification */
+	char			xwi_masterxid;	/* Hub's Widget Port Number */
+	void			*xwi_hubinfo;     /* Hub's provider private info */
+	uint64_t		*xwi_hub_provider; /* prom provider functions */
+	void			*xwi_vertex;
+};
+
+#endif                          /* _ASM_IA64_SN_XTALK_XWIDGET_H */

arch/ia64/sn/io/Makefile

-# arch/ia64/sn/io/Makefile
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License.  See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 2000-2002 Silicon Graphics, Inc.  All Rights Reserved.
-#
-# Makefile for the sn io routines.
-#
-
-obj-y += xswitch.o cdl.o snia_if.o \
-	 io.o machvec/ drivers/ platform_init/ sn2/ hwgfs/

arch/ia64/sn/io/cdl.c

-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
- */
-
-#include <linux/config.h>
-#include <linux/types.h>
-#include <asm/sn/sgi.h>
-#include <asm/io.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/pci/pic.h>
-#include "asm/sn/ioerror_handling.h"
-#include <asm/sn/xtalk/xbow.h>
-
-/* these get called directly in cdl_add_connpt in fops bypass hack */
-extern int xbow_attach(vertex_hdl_t);
-extern int pic_attach(vertex_hdl_t);
-
-/*
- *    cdl: Connection and Driver List
- *
- *	We are not porting this to Linux.  Devices are registered via 
- *	the normal Linux PCI layer.  This is a very simplified version 
- *	of cdl that will allow us to register and call our very own 
- *	IO Infrastructure Drivers e.g. pcibr.
- */
-
-#define MAX_SGI_IO_INFRA_DRVR 5
-
-static struct cdl sgi_infrastructure_drivers[MAX_SGI_IO_INFRA_DRVR] =
-{
-	{ PIC_WIDGET_PART_NUM_BUS0,  PIC_WIDGET_MFGR_NUM,   pic_attach /* &pcibr_fops */},
-	{ PIC_WIDGET_PART_NUM_BUS1,  PIC_WIDGET_MFGR_NUM,   pic_attach /* &pcibr_fops */},
-	{ XXBOW_WIDGET_PART_NUM,   XXBOW_WIDGET_MFGR_NUM,   xbow_attach /* &xbow_fops */},
-	{ XBOW_WIDGET_PART_NUM,    XBOW_WIDGET_MFGR_NUM,    xbow_attach /* &xbow_fops */},
-	{ PXBOW_WIDGET_PART_NUM,   XXBOW_WIDGET_MFGR_NUM,   xbow_attach /* &xbow_fops */},
-};
-
-/*
- * cdl_add_connpt: We found a device and it's connect point.  Call the 
- * attach routine of that driver.
- *
- * May need support for pciba registration here ...
- *
- * This routine use to create /hw/.id/pci/.../.. that links to 
- * /hw/module/006c06/Pbrick/xtalk/15/pci/<slotnum> .. do we still need 
- * it?  The specified driver attach routine does not reference these 
- * vertices.
- */
-int
-cdl_add_connpt(int part_num, int mfg_num, 
-	       vertex_hdl_t connpt, int drv_flags)
-{
-	int i;
-	
-	/*
-	 * Find the driver entry point and call the attach routine.
-	 */
-	for (i = 0; i < MAX_SGI_IO_INFRA_DRVR; i++) {
-		if ( (part_num == sgi_infrastructure_drivers[i].part_num) &&
-		   ( mfg_num == sgi_infrastructure_drivers[i].mfg_num) ) {
-			/*
-			 * Call the device attach routines.
-			 */
-			if (sgi_infrastructure_drivers[i].attach) {
-			    return(sgi_infrastructure_drivers[i].attach(connpt));
-			}
-		} else {
-			continue;
-		}
-	}	
-
-	/* printk("WARNING: cdl_add_connpt: Driver not found for part_num 0x%x mfg_num 0x%x\n", part_num, mfg_num); */
-
-	return (0);
-}

arch/ia64/sn/io/drivers/ioconfig_bus.c

-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- *  ioconfig_bus - SGI's Persistent PCI Bus Numbering.
- *
- * Copyright (C) 1992-1997, 2000-2003 Silicon Graphics, Inc.  All rights reserved.
- */
-
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/ctype.h>
-#include <linux/module.h>
-#include <linux/init.h>
-
-#include <linux/pci.h>
-
-#include <asm/uaccess.h>
-#include <asm/sn/sgi.h>
-#include <asm/io.h>
-#include <asm/sn/iograph.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/labelcl.h>
-#include <asm/sn/sn_sal.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/ioconfig_bus.h>
-
-#define SGI_IOCONFIG_BUS "SGI-PERSISTENT PCI BUS NUMBERING"
-#define SGI_IOCONFIG_BUS_VERSION "1.0"
-
-/*
- * Some Global definitions.
- */
-static vertex_hdl_t ioconfig_bus_handle;
-static unsigned long ioconfig_bus_debug;
-static struct ioconfig_parm parm;
-
-#ifdef IOCONFIG_BUS_DEBUG
-#define DBG(x...)	printk(x)
-#else
-#define DBG(x...)
-#endif
-
-static u64 ioconfig_activated;
-static char ioconfig_kernopts[128];
-
-/*
- * For debugging purpose .. hardcode a table ..
- */
-struct  ascii_moduleid *ioconfig_bus_table;
-
-static int free_entry;
-static int new_entry;
-
-int next_basebus_number;
-
-void
-ioconfig_get_busnum(char *io_moduleid, int *bus_num)
-{
-	struct	ascii_moduleid  *temp;
-	int index;
-
-	DBG("ioconfig_get_busnum io_moduleid %s\n", io_moduleid);
-
-	*bus_num = -1;
-	temp = ioconfig_bus_table;
-	if (!ioconfig_bus_table)
-		return;
-	for (index = 0; index < free_entry; temp++, index++) {
-		if ( (io_moduleid[0] == temp->io_moduleid[0]) &&
-		     (io_moduleid[1] == temp->io_moduleid[1]) &&
-		     (io_moduleid[2] == temp->io_moduleid[2]) &&
-		     (io_moduleid[4] == temp->io_moduleid[4]) &&
-		     (io_moduleid[5] == temp->io_moduleid[5]) ) {
-			*bus_num = index * 0x10;
-			return;
-		}
-	}
-
-	/*
-	 * New IO Brick encountered.
-	 */
-	if (((int)io_moduleid[0]) == 0) {
-		DBG("ioconfig_get_busnum: Invalid Module Id given %s\n", io_moduleid);
-		return;
-	}
-
-	io_moduleid[3] = '#';
-	strcpy((char *)&(ioconfig_bus_table[free_entry].io_moduleid), io_moduleid);
-	*bus_num = free_entry * 0x10;
-	free_entry++;
-}
-
-static void
-dump_ioconfig_table(void)
-{
-
-	int index = 0;
-	struct ascii_moduleid *temp;
-
-	temp = ioconfig_bus_table;
-	if (!temp) {
-		DBG("ioconfig_bus_table tabel empty\n");
-		return;
-	}
-	while (index < free_entry) {
-		DBG("ASSCI Module ID %s\n", temp->io_moduleid);
-		temp++;
-		index++;
-	}
-}
-
-/*
- * nextline
- *	This routine returns the nextline in the buffer.
- */
-int nextline(char *buffer, char **next, char *line)
-{
-
-	char *temp;
-
-	if (buffer[0] == 0x0) {
-		return(0);
-	}
-
-	temp = buffer;
-	while (*temp != 0) {
-		*line = *temp;
-		if (*temp != '\n'){
-			*line = *temp;
-			temp++; line++;
-		} else
-			break;
-	}
-
-	if (*temp == 0)
-		*next = temp;
-	else
-		*next = ++temp;
-
-	return(1);
-}
-
-/*
- * build_pcibus_name
- *	This routine parses the ioconfig contents read into
- *	memory by ioconfig command in EFI and builds the
- *	persistent pci bus naming table.
- */
-int
-build_moduleid_table(char *file_contents, struct ascii_moduleid *table)
-{
-	/*
-	 * Read the whole file into memory.
-	 */
-	int rc;
-	char *name;
-	char *temp;
-	char *next;
-	char *curr;
-	char *line;
-	struct ascii_moduleid *moduleid;
-
-	line = kmalloc(256, GFP_KERNEL);
-	name = kmalloc(125, GFP_KERNEL);
-	if (!line || !name) {
-		if (line)
-			kfree(line);
-		if (name)
-			kfree(name);
-		printk("build_moduleid_table(): Unabled to allocate memmory");
-		return -ENOMEM;
-	}
-
-	memset(line, 0,256);
-	memset(name, 0, 125);
-	moduleid = table;
-	curr = file_contents;
-	while (nextline(curr, &next, line)){
-
-		DBG("curr 0x%lx next 0x%lx\n", curr, next);
-
-		temp = line;
-		/*
-		 * Skip all leading Blank lines ..
-		 */
-		while (isspace(*temp))
-			if (*temp != '\n')
-				temp++;
-			else
-				break;
-
-		if (*temp == '\n') {
-			curr = next;
-			memset(line, 0, 256);
-			continue;
-		}
- 
-		/*
-		 * Skip comment lines
-		 */
-		if (*temp == '#') {
-			curr = next;
-			memset(line, 0, 256);
-			continue;
-		}
-
-		/*
-		 * Get the next free entry in the table.
-		 */
-		rc = sscanf(temp, "%s", name);
-		strcpy(&moduleid->io_moduleid[0], name);
-		DBG("Found %s\n", name);
-		moduleid++;
-		free_entry++;
-		curr = next;
-		memset(line, 0, 256);
-	}
-
-	new_entry = free_entry;
-	kfree(line);
-	kfree(name);
-
-	return 0;
-}
-
-int
-ioconfig_bus_init(void)
-{
-
-	DBG("ioconfig_bus_init called.\n");
-
-	ioconfig_bus_table = kmalloc( 512, GFP_KERNEL );
-	if (!ioconfig_bus_table) {
-		printk("ioconfig_bus_init : cannot allocate memory\n");
-		return -1;
-	}
-
-	memset(ioconfig_bus_table, 0, 512);
-
-	/*
-	 * If ioconfig options are given on the bootline .. take it.
-	 */
-	if (*ioconfig_kernopts != '\0') {
-		/*
-		 * ioconfig="..." kernel options given.
-		 */
-		DBG("ioconfig_bus_init: Kernel Options given.\n");
-		if ( build_moduleid_table((char *)ioconfig_kernopts, ioconfig_bus_table) < 0 )
-			return -1;
-		(void) dump_ioconfig_table();
-	}
-	return 0;
-}
-
-void
-ioconfig_bus_new_entries(void)
-{
-	int index;
-	struct ascii_moduleid *temp;
-
-	if ((ioconfig_activated) && (free_entry > new_entry)) {
-		printk("### Please add the following new IO Bricks Module ID \n");
-		printk("### to your Persistent Bus Numbering Config File\n");
-	} else
-		return;
-
-	index = new_entry;
-	if (!ioconfig_bus_table) {
-		printk("ioconfig_bus_table table is empty\n");
-		return;
-	}
-	temp = &ioconfig_bus_table[index];
-        while (index < free_entry) {
-                printk("%s\n", (char *)temp);
-		temp++;
-                index++;
-        }
-	printk("### End\n");
-
-}
-static int ioconfig_bus_ioctl(struct inode * inode, struct file * file,
-        unsigned int cmd, unsigned long arg)
-{
-	/*
-	 * Copy in the parameters.
-	 */
-	if (copy_from_user(&parm, (char *)arg, sizeof(struct ioconfig_parm)))
-		return -EFAULT;
-	parm.number = free_entry - new_entry;
-	parm.ioconfig_activated = ioconfig_activated;
-	if (copy_to_user((char *)arg, &parm, sizeof(struct ioconfig_parm)))
-		return -EFAULT;
-
-	if (!ioconfig_bus_table)
-		return -EFAULT;
-
-	if (copy_to_user((char *)parm.buffer, &ioconfig_bus_table[new_entry], sizeof(struct  ascii_moduleid) * (free_entry - new_entry)))
-		return -EFAULT;
-
-	return 0;
-}
-
-/*
- * ioconfig_bus_open - Opens the special device node "/dev/hw/.ioconfig_bus".
- */
-static int ioconfig_bus_open(struct inode * inode, struct file * filp)
-{
-	if (ioconfig_bus_debug) {
-        	DBG("ioconfig_bus_open called.\n");
-	}
-
-        return(0);
-
-}
-
-/*
- * ioconfig_bus_close - Closes the special device node "/dev/hw/.ioconfig_bus".
- */
-static int ioconfig_bus_close(struct inode * inode, struct file * filp)
-{
-
-	if (ioconfig_bus_debug) {
-        	DBG("ioconfig_bus_close called.\n");
-	}
-
-        return(0);
-}
-
-struct file_operations ioconfig_bus_fops = {
-	.ioctl	= ioconfig_bus_ioctl,
-	.open	= ioconfig_bus_open,	/* open */
-	.release=ioconfig_bus_close	/* release */
-};
-
-
-/*
- * init_ifconfig_bus() - Boot time initialization.  Ensure that it is called 
- *	after hwgfs has been initialized.
- *
- */
-int init_ioconfig_bus(void)
-{
-	ioconfig_bus_handle = hwgraph_register(hwgraph_root, ".ioconfig_bus",
-		        0, 0,
-			0, 0,
-			S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
-			&ioconfig_bus_fops, NULL);
-
-	if (ioconfig_bus_handle == NULL) {
-		panic("Unable to create SGI PERSISTENT BUS NUMBERING Driver.\n");
-	}
-
-	return 0;
-}
-
-static int __init ioconfig_bus_setup (char *str)
-{
-
-	char *temp;
-
-	DBG("ioconfig_bus_setup: Kernel Options %s\n", str);
-
-	temp = (char *)ioconfig_kernopts;
-	memset(temp, 0, 128);
-	while ( (*str != '\0') && !isspace (*str) ) {
-		if (*str == ',') {
-			*temp = '\n';
-			temp++;
-			str++;
-			continue;
-		}
-		*temp = *str;
-		temp++;
-		str++;
-	}
-
-	return(0);
-		
-}
-__setup("ioconfig=", ioconfig_bus_setup);

arch/ia64/sn/io/hwgfs/Makefile

-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License.  See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 2002-2003 Silicon Graphics, Inc.  All Rights Reserved.
-#
-# Makefile for the sn2 io routines.
-
-obj-y		+= hcl.o labelcl.o hcl_util.o ramfs.o interface.o

arch/ia64/sn/io/hwgfs/hcl_util.c

-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved.
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <asm/sn/sgi.h>
-#include <asm/io.h>
-#include <asm/sn/io.h>
-#include <asm/sn/iograph.h>
-#include <asm/sn/hwgfs.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/labelcl.h>
-#include <asm/sn/hcl_util.h>
-#include <asm/sn/nodepda.h>
-
-static vertex_hdl_t hwgraph_all_cnodes = GRAPH_VERTEX_NONE;
-extern vertex_hdl_t hwgraph_root;
-static vertex_hdl_t hwgraph_all_cpuids = GRAPH_VERTEX_NONE;
-extern int maxcpus;
-
-void
-mark_cpuvertex_as_cpu(vertex_hdl_t vhdl, cpuid_t cpuid)
-{
-	char cpuid_buffer[10];
-
-	if (cpuid == CPU_NONE)
-		return;
-
-	if (hwgraph_all_cpuids == GRAPH_VERTEX_NONE) {
-		(void)hwgraph_path_add( hwgraph_root,
-					EDGE_LBL_CPUNUM,
-					&hwgraph_all_cpuids);
-	}
-
-	sprintf(cpuid_buffer, "%ld", cpuid);
-	(void)hwgraph_edge_add( hwgraph_all_cpuids, vhdl, cpuid_buffer);
-}
-
-/*
-** Return the "master" for a given vertex.  A master vertex is a
-** controller or adapter or other piece of hardware that the given
-** vertex passes through on the way to the rest of the system.
-*/
-vertex_hdl_t
-device_master_get(vertex_hdl_t vhdl)
-{
-	graph_error_t rc;
-	vertex_hdl_t master;
-
-	rc = hwgraph_edge_get(vhdl, EDGE_LBL_MASTER, &master);
-	if (rc == GRAPH_SUCCESS)
-		return(master);
-	else
-		return(GRAPH_VERTEX_NONE);
-}
-
-/*
-** Set the master for a given vertex.
-** Returns 0 on success, non-0 indicates failure
-*/
-int
-device_master_set(vertex_hdl_t vhdl, vertex_hdl_t master)
-{
-	graph_error_t rc;
-
-	rc = hwgraph_edge_add(vhdl, master, EDGE_LBL_MASTER);
-	return(rc != GRAPH_SUCCESS);
-}
-
-
-/*
-** Return the compact node id of the node that ultimately "owns" the specified
-** vertex.  In order to do this, we walk back through masters and connect points
-** until we reach a vertex that represents a node.
-*/
-cnodeid_t
-master_node_get(vertex_hdl_t vhdl)
-{
-	cnodeid_t cnodeid;
-	vertex_hdl_t master;
-
-	for (;;) {
-		cnodeid = nodevertex_to_cnodeid(vhdl);
-		if (cnodeid != CNODEID_NONE)
-			return(cnodeid);
-
-		master = device_master_get(vhdl);
-
-		/* Check for exceptional cases */
-		if (master == vhdl) {
-			/* Since we got a reference to the "master" thru
-			 * device_master_get() we should decrement
-			 * its reference count by 1
-			 */
-			return(CNODEID_NONE);
-		}
-
-		if (master == GRAPH_VERTEX_NONE) {
-			master = hwgraph_connectpt_get(vhdl);
-			if ((master == GRAPH_VERTEX_NONE) ||
-			    (master == vhdl)) {
-				return(CNODEID_NONE);
-			}
-		}
-
-		vhdl = master;
-	}
-}
-
-
-/*
-** If the specified device represents a node, return its
-** compact node ID; otherwise, return CNODEID_NONE.
-*/
-cnodeid_t
-nodevertex_to_cnodeid(vertex_hdl_t vhdl)
-{
-	int rv = 0;
-	arbitrary_info_t cnodeid = CNODEID_NONE;
-
-	rv = labelcl_info_get_LBL(vhdl, INFO_LBL_CNODEID, NULL, &cnodeid);
-
-	return((cnodeid_t)cnodeid);
-}
-
-void
-mark_nodevertex_as_node(vertex_hdl_t vhdl, cnodeid_t cnodeid)
-{
-	if (cnodeid == CNODEID_NONE)
-		return;
-
-	cnodeid_to_vertex(cnodeid) = vhdl;
-	labelcl_info_add_LBL(vhdl, INFO_LBL_CNODEID, INFO_DESC_EXPORT, 
-		(arbitrary_info_t)cnodeid);
-
-	{
-		char cnodeid_buffer[10];
-
-		if (hwgraph_all_cnodes == GRAPH_VERTEX_NONE) {
-			(void)hwgraph_path_add( hwgraph_root,
-						EDGE_LBL_NODENUM,
-						&hwgraph_all_cnodes);
-		}
-
-		sprintf(cnodeid_buffer, "%d", cnodeid);
-		(void)hwgraph_edge_add( hwgraph_all_cnodes,
-					vhdl,
-					cnodeid_buffer);
-		HWGRAPH_DEBUG(__FILE__, __FUNCTION__, __LINE__, hwgraph_all_cnodes, NULL, "Creating path vhdl1\n");
-	}
-}
-
-/*
-** dev_to_name converts a vertex_hdl_t into a canonical name.  If the vertex_hdl_t
-** represents a vertex in the hardware graph, it is converted in the
-** normal way for vertices.  If the vertex_hdl_t is an old vertex_hdl_t (one which
-** does not represent a hwgraph vertex), we synthesize a name based
-** on major/minor number.
-**
-** Usually returns a pointer to the original buffer, filled in as
-** appropriate.  If the buffer is too small to hold the entire name,
-** or if anything goes wrong while determining the name, dev_to_name
-** returns "UnknownDevice".
-*/
-char *
-dev_to_name(vertex_hdl_t dev, char *buf, uint buflen)
-{
-        return(vertex_to_name(dev, buf, buflen));
-}
-

arch/ia64/sn/io/machvec/Makefile

-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License.  See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 2002-2003 Silicon Graphics, Inc.  All Rights Reserved.
-#
-# Makefile for the sn2 io routines.
-
-obj-y				+= pci.o pci_dma.o pci_bus_cvlink.o iomv.o

arch/ia64/sn/io/machvec/pci.c

-/* 
- * SNI64 specific PCI support for SNI IO.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 1997, 1998, 2000-2003 Silicon Graphics, Inc.  All rights reserved.
- */
-#include <asm/sn/hcl.h>
-#include <asm/sn/pci/pcibr_private.h>
-
-/*
- * These routines are only used during sn_pci_init for probing each bus, and
- * can probably be removed with a little more cleanup now that the SAL routines
- * work on sn2.
- */
-
-extern vertex_hdl_t devfn_to_vertex(unsigned char bus, unsigned char devfn);
-
-int sn_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val)
-{
-	unsigned long res = 0;
-	vertex_hdl_t device_vertex;
-
-	device_vertex = devfn_to_vertex(bus->number, devfn);
-
-	if (!device_vertex)
-		return PCIBIOS_DEVICE_NOT_FOUND;
-
-	res = pciio_config_get(device_vertex, (unsigned)where, size);
-	*val = (u32)res;
-	return PCIBIOS_SUCCESSFUL;
-}
-
-int sn_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
-{
-	vertex_hdl_t device_vertex;
-
-	device_vertex = devfn_to_vertex(bus->number, devfn);
-
-	if (!device_vertex)
-		return PCIBIOS_DEVICE_NOT_FOUND;
-
-	pciio_config_set(device_vertex, (unsigned)where, size, (uint64_t)val);
-	return PCIBIOS_SUCCESSFUL;
-}
-
-struct pci_ops sn_pci_ops = {
-	.read = sn_read_config,
-	.write = sn_write_config,
-};

arch/ia64/sn/io/sn2/Makefile

-# arch/ia64/sn/io/sn2/Makefile
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License.  See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 2002-2003 Silicon Graphics, Inc.  All Rights Reserved.
-#
-# Makefile for the sn2 specific io routines.
-#
-
-obj-y += pcibr/ ml_SN_intr.o shub_intr.o shuberror.o shub.o bte_error.o \
-	 pic.o geo_op.o l1_command.o klconflib.o klgraph.o ml_SN_init.o \
-	 ml_iograph.o module.o pciio.o xbow.o xtalk.o shubio.o