Skip to content

L
linux
Commit 2a26daee authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files
Options

Merge tag 'tegra-for-6.2-soc-v2' of... 

Merge tag 'tegra-for-6.2-soc-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers

soc/tegra: Changes for v6.2-rc1

In addition to a number of improvements and cleanups this contains a
fix for the FUSE access on newer chips, adds Tegra234 I/O pad support
and fixes various issues with wake events.

The SoC sysfs revision attribute is updated to include the platform
information so drivers can check for silicon vs. pre-silicon, among
other things.

* tag 'tegra-for-6.2-soc-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: cbb: Remove redundant dev_err call
  soc/tegra: cbb: Use DEFINE_SHOW_ATTRIBUTE to simplify tegra_cbb_err
  firmware: tegra: include IVC header file only once
  soc/tegra: cbb: Check firewall before enabling error reporting
  soc/tegra: cbb: Add checks for potential out of bound errors
  soc/tegra: cbb: Update slave maps for Tegra234
  soc/tegra: cbb: Use correct master_id mask for CBB NOC in Tegra194
  soc/tegra: fuse: Use platform info with SoC revision
  soc/tegra: pmc: Process wake events during resume
  soc/tegra: pmc: Fix dual edge triggered wakes
  soc/tegra: pmc: Add I/O pad table for Tegra234
  soc/tegra: fuse: Add nvmem keepout list
  soc/tegra: fuse: Use SoC specific nvmem cells
  soc/tegra: pmc: Select IRQ_DOMAIN_HIERARCHY

Link: https://lore.kernel.org/r/20221121171239.2041835-1-thierry.reding@gmail.comSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 862fe29b b6c6bbfc
Hide whitespace changes
Inline Side-by-side
Showing with 1092 additions and 427 deletions
drivers/soc/tegra/Kconfig
View file @ 2a26daee
...@@ -143,6 +143,7 @@ config SOC_TEGRA_FLOWCTRL ...@@ -143,6 +143,7 @@ config SOC_TEGRA_FLOWCTRL
config SOC_TEGRA_PMC config SOC_TEGRA_PMC
bool bool
select GENERIC_PINCONF select GENERIC_PINCONF
select IRQ_DOMAIN_HIERARCHY
select PM_OPP select PM_OPP
select PM_GENERIC_DOMAINS select PM_GENERIC_DOMAINS
select REGMAP select REGMAP
......
drivers/soc/tegra/cbb/tegra-cbb.c
View file @ 2a26daee
...@@ -72,18 +72,7 @@ static int tegra_cbb_err_show(struct seq_file *file, void *data) ...@@ -72,18 +72,7 @@ static int tegra_cbb_err_show(struct seq_file *file, void *data)
return cbb->ops->debugfs_show(cbb, file, data); return cbb->ops->debugfs_show(cbb, file, data);
} }
DEFINE_SHOW_ATTRIBUTE(tegra_cbb_err);
static int tegra_cbb_err_open(struct inode *inode, struct file *file)
{
return single_open(file, tegra_cbb_err_show, inode->i_private);
}
static const struct file_operations tegra_cbb_err_fops = {
.open = tegra_cbb_err_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release
};
static int tegra_cbb_err_debugfs_init(struct tegra_cbb *cbb) static int tegra_cbb_err_debugfs_init(struct tegra_cbb *cbb)
{ {
......
drivers/soc/tegra/cbb/tegra194-cbb.c
View file @ 2a26daee
...@@ -102,8 +102,6 @@ ...@@ -102,8 +102,6 @@
#define CLUSTER_NOC_VQC GENMASK(17, 16) #define CLUSTER_NOC_VQC GENMASK(17, 16)
#define CLUSTER_NOC_MSTR_ID GENMASK(21, 18) #define CLUSTER_NOC_MSTR_ID GENMASK(21, 18)
#define USRBITS_MSTR_ID GENMASK(21, 18)
#define CBB_ERR_OPC GENMASK(4, 1) #define CBB_ERR_OPC GENMASK(4, 1)
#define CBB_ERR_ERRCODE GENMASK(10, 8) #define CBB_ERR_ERRCODE GENMASK(10, 8)
#define CBB_ERR_LEN1 GENMASK(27, 16) #define CBB_ERR_LEN1 GENMASK(27, 16)
...@@ -2038,15 +2036,17 @@ static irqreturn_t tegra194_cbb_err_isr(int irq, void *data) ...@@ -2038,15 +2036,17 @@ static irqreturn_t tegra194_cbb_err_isr(int irq, void *data)
smp_processor_id(), priv->noc->name, priv->res->start, smp_processor_id(), priv->noc->name, priv->res->start,
irq); irq);
mstr_id = FIELD_GET(USRBITS_MSTR_ID, priv->errlog5) - 1;
is_fatal = print_errlog(NULL, priv, status); is_fatal = print_errlog(NULL, priv, status);
/* /*
* If illegal request is from CCPLEX(0x1) * If illegal request is from CCPLEX(0x1) initiator
* initiator then call BUG() to crash system. * and error is fatal then call BUG() to crash system.
*/ */
if ((mstr_id == 0x1) && priv->noc->erd_mask_inband_err) if (priv->noc->erd_mask_inband_err) {
is_inband_err = 1; mstr_id = FIELD_GET(CBB_NOC_MSTR_ID, priv->errlog5);
if (mstr_id == 0x1)
is_inband_err = 1;
}
} }
} }
...@@ -2226,10 +2226,8 @@ static int tegra194_cbb_get_bridges(struct tegra194_cbb *cbb, struct device_node ...@@ -2226,10 +2226,8 @@ static int tegra194_cbb_get_bridges(struct tegra194_cbb *cbb, struct device_node
cbb->bridges[i].base = devm_ioremap_resource(cbb->base.dev, cbb->bridges[i].base = devm_ioremap_resource(cbb->base.dev,
&cbb->bridges[i].res); &cbb->bridges[i].res);
if (IS_ERR(cbb->bridges[i].base)) { if (IS_ERR(cbb->bridges[i].base))
dev_err(cbb->base.dev, "failed to map AXI2APB range\n");
return PTR_ERR(cbb->bridges[i].base); return PTR_ERR(cbb->bridges[i].base);
}
} }
} }
......
drivers/soc/tegra/cbb/tegra234-cbb.c
View file @ 2a26daee
...@@ -72,6 +72,11 @@ ...@@ -72,6 +72,11 @@
#define REQ_SOCKET_ID GENMASK(27, 24) #define REQ_SOCKET_ID GENMASK(27, 24)
#define CCPLEX_MSTRID 0x1
#define FIREWALL_APERTURE_SZ 0x10000
/* Write firewall check enable */
#define WEN 0x20000
enum tegra234_cbb_fabric_ids { enum tegra234_cbb_fabric_ids {
CBB_FAB_ID, CBB_FAB_ID,
SCE_FAB_ID, SCE_FAB_ID,
...@@ -92,11 +97,15 @@ struct tegra234_slave_lookup { ...@@ -92,11 +97,15 @@ struct tegra234_slave_lookup {
struct tegra234_cbb_fabric { struct tegra234_cbb_fabric {
const char *name; const char *name;
phys_addr_t off_mask_erd; phys_addr_t off_mask_erd;
bool erd_mask_inband_err; phys_addr_t firewall_base;
unsigned int firewall_ctl;
unsigned int firewall_wr_ctl;
const char * const *master_id; const char * const *master_id;
unsigned int notifier_offset; unsigned int notifier_offset;
const struct tegra_cbb_error *errors; const struct tegra_cbb_error *errors;
const int max_errors;
const struct tegra234_slave_lookup *slave_map; const struct tegra234_slave_lookup *slave_map;
const int max_slaves;
}; };
struct tegra234_cbb { struct tegra234_cbb {
...@@ -128,6 +137,44 @@ static inline struct tegra234_cbb *to_tegra234_cbb(struct tegra_cbb *cbb) ...@@ -128,6 +137,44 @@ static inline struct tegra234_cbb *to_tegra234_cbb(struct tegra_cbb *cbb)
static LIST_HEAD(cbb_list); static LIST_HEAD(cbb_list);
static DEFINE_SPINLOCK(cbb_lock); static DEFINE_SPINLOCK(cbb_lock);
static bool
tegra234_cbb_write_access_allowed(struct platform_device *pdev, struct tegra234_cbb *cbb)
{
u32 val;
if (!cbb->fabric->firewall_base ||
!cbb->fabric->firewall_ctl ||
!cbb->fabric->firewall_wr_ctl) {
dev_info(&pdev->dev, "SoC data missing for firewall\n");
return false;
}
if ((cbb->fabric->firewall_ctl > FIREWALL_APERTURE_SZ) ||
(cbb->fabric->firewall_wr_ctl > FIREWALL_APERTURE_SZ)) {
dev_err(&pdev->dev, "wrong firewall offset value\n");
return false;
}
val = readl(cbb->regs + cbb->fabric->firewall_base + cbb->fabric->firewall_ctl);
/*
* If the firewall check feature for allowing or blocking the
* write accesses through the firewall of a fabric is disabled
* then CCPLEX can write to the registers of that fabric.
*/
if (!(val & WEN))
return true;
/*
* If the firewall check is enabled then check whether CCPLEX
* has write access to the fabric's error notifier registers
*/
val = readl(cbb->regs + cbb->fabric->firewall_base + cbb->fabric->firewall_wr_ctl);
if (val & (BIT(CCPLEX_MSTRID)))
return true;
return false;
}
static void tegra234_cbb_fault_enable(struct tegra_cbb *cbb) static void tegra234_cbb_fault_enable(struct tegra_cbb *cbb)
{ {
struct tegra234_cbb *priv = to_tegra234_cbb(cbb); struct tegra234_cbb *priv = to_tegra234_cbb(cbb);
...@@ -271,6 +318,12 @@ static void tegra234_cbb_print_error(struct seq_file *file, struct tegra234_cbb ...@@ -271,6 +318,12 @@ static void tegra234_cbb_print_error(struct seq_file *file, struct tegra234_cbb
tegra_cbb_print_err(file, "\t Multiple type of errors reported\n"); tegra_cbb_print_err(file, "\t Multiple type of errors reported\n");
while (status) { while (status) {
if (type >= cbb->fabric->max_errors) {
tegra_cbb_print_err(file, "\t Wrong type index:%u, status:%u\n",
type, status);
return;
}
if (status & 0x1) if (status & 0x1)
tegra_cbb_print_err(file, "\t Error Code\t\t: %s\n", tegra_cbb_print_err(file, "\t Error Code\t\t: %s\n",
cbb->fabric->errors[type].code); cbb->fabric->errors[type].code);
...@@ -282,6 +335,12 @@ static void tegra234_cbb_print_error(struct seq_file *file, struct tegra234_cbb ...@@ -282,6 +335,12 @@ static void tegra234_cbb_print_error(struct seq_file *file, struct tegra234_cbb
type = 0; type = 0;
while (overflow) { while (overflow) {
if (type >= cbb->fabric->max_errors) {
tegra_cbb_print_err(file, "\t Wrong type index:%u, overflow:%u\n",
type, overflow);
return;
}
if (overflow & 0x1) if (overflow & 0x1)
tegra_cbb_print_err(file, "\t Overflow\t\t: Multiple %s\n", tegra_cbb_print_err(file, "\t Overflow\t\t: Multiple %s\n",
cbb->fabric->errors[type].code); cbb->fabric->errors[type].code);
...@@ -334,8 +393,11 @@ static void print_errlog_err(struct seq_file *file, struct tegra234_cbb *cbb) ...@@ -334,8 +393,11 @@ static void print_errlog_err(struct seq_file *file, struct tegra234_cbb *cbb)
access_type = FIELD_GET(FAB_EM_EL_ACCESSTYPE, cbb->mn_attr0); access_type = FIELD_GET(FAB_EM_EL_ACCESSTYPE, cbb->mn_attr0);
tegra_cbb_print_err(file, "\n"); tegra_cbb_print_err(file, "\n");
tegra_cbb_print_err(file, "\t Error Code\t\t: %s\n", if (cbb->type < cbb->fabric->max_errors)
cbb->fabric->errors[cbb->type].code); tegra_cbb_print_err(file, "\t Error Code\t\t: %s\n",
cbb->fabric->errors[cbb->type].code);
else
tegra_cbb_print_err(file, "\t Wrong type index:%u\n", cbb->type);
tegra_cbb_print_err(file, "\t MASTER_ID\t\t: %s\n", cbb->fabric->master_id[mstr_id]); tegra_cbb_print_err(file, "\t MASTER_ID\t\t: %s\n", cbb->fabric->master_id[mstr_id]);
tegra_cbb_print_err(file, "\t Address\t\t: %#llx\n", cbb->access); tegra_cbb_print_err(file, "\t Address\t\t: %#llx\n", cbb->access);
...@@ -374,6 +436,11 @@ static void print_errlog_err(struct seq_file *file, struct tegra234_cbb *cbb) ...@@ -374,6 +436,11 @@ static void print_errlog_err(struct seq_file *file, struct tegra234_cbb *cbb)
if ((fab_id == PSC_FAB_ID) || (fab_id == FSI_FAB_ID)) if ((fab_id == PSC_FAB_ID) || (fab_id == FSI_FAB_ID))
return; return;
if (slave_id >= cbb->fabric->max_slaves) {
tegra_cbb_print_err(file, "\t Invalid slave_id:%d\n", slave_id);
return;
}
if (!strcmp(cbb->fabric->errors[cbb->type].code, "TIMEOUT_ERR")) { if (!strcmp(cbb->fabric->errors[cbb->type].code, "TIMEOUT_ERR")) {
tegra234_lookup_slave_timeout(file, cbb, slave_id, fab_id); tegra234_lookup_slave_timeout(file, cbb, slave_id, fab_id);
return; return;
...@@ -517,7 +584,7 @@ static irqreturn_t tegra234_cbb_isr(int irq, void *data) ...@@ -517,7 +584,7 @@ static irqreturn_t tegra234_cbb_isr(int irq, void *data)
u32 status = tegra_cbb_get_status(cbb); u32 status = tegra_cbb_get_status(cbb);
if (status && (irq == priv->sec_irq)) { if (status && (irq == priv->sec_irq)) {
tegra_cbb_print_err(NULL, "CPU:%d, Error: %s@%llx, irq=%d\n", tegra_cbb_print_err(NULL, "CPU:%d, Error: %s@0x%llx, irq=%d\n",
smp_processor_id(), priv->fabric->name, smp_processor_id(), priv->fabric->name,
priv->res->start, irq); priv->res->start, irq);
...@@ -525,14 +592,14 @@ static irqreturn_t tegra234_cbb_isr(int irq, void *data) ...@@ -525,14 +592,14 @@ static irqreturn_t tegra234_cbb_isr(int irq, void *data)
if (err) if (err)
goto unlock; goto unlock;
mstr_id = FIELD_GET(USRBITS_MSTR_ID, priv->mn_user_bits);
/* /*
* If illegal request is from CCPLEX(id:0x1) master then call BUG() to * If illegal request is from CCPLEX(id:0x1) master then call WARN()
* crash system.
*/ */
if ((mstr_id == 0x1) && priv->fabric->off_mask_erd) if (priv->fabric->off_mask_erd) {
is_inband_err = 1; mstr_id = FIELD_GET(USRBITS_MSTR_ID, priv->mn_user_bits);
if (mstr_id == CCPLEX_MSTRID)
is_inband_err = 1;
}
} }
} }
...@@ -640,8 +707,13 @@ static const struct tegra234_cbb_fabric tegra234_aon_fabric = { ...@@ -640,8 +707,13 @@ static const struct tegra234_cbb_fabric tegra234_aon_fabric = {
.name = "aon-fabric", .name = "aon-fabric",
.master_id = tegra234_master_id, .master_id = tegra234_master_id,
.slave_map = tegra234_aon_slave_map, .slave_map = tegra234_aon_slave_map,
.max_slaves = ARRAY_SIZE(tegra234_aon_slave_map),
.errors = tegra234_cbb_errors, .errors = tegra234_cbb_errors,
.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
.notifier_offset = 0x17000, .notifier_offset = 0x17000,
.firewall_base = 0x30000,
.firewall_ctl = 0x8d0,
.firewall_wr_ctl = 0x8c8,
}; };
static const struct tegra234_slave_lookup tegra234_bpmp_slave_map[] = { static const struct tegra234_slave_lookup tegra234_bpmp_slave_map[] = {
...@@ -656,8 +728,13 @@ static const struct tegra234_cbb_fabric tegra234_bpmp_fabric = { ...@@ -656,8 +728,13 @@ static const struct tegra234_cbb_fabric tegra234_bpmp_fabric = {
.name = "bpmp-fabric", .name = "bpmp-fabric",
.master_id = tegra234_master_id, .master_id = tegra234_master_id,
.slave_map = tegra234_bpmp_slave_map, .slave_map = tegra234_bpmp_slave_map,
.max_slaves = ARRAY_SIZE(tegra234_bpmp_slave_map),
.errors = tegra234_cbb_errors, .errors = tegra234_cbb_errors,
.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
.notifier_offset = 0x19000, .notifier_offset = 0x19000,
.firewall_base = 0x30000,
.firewall_ctl = 0x8f0,
.firewall_wr_ctl = 0x8e8,
}; };
static const struct tegra234_slave_lookup tegra234_cbb_slave_map[] = { static const struct tegra234_slave_lookup tegra234_cbb_slave_map[] = {
...@@ -728,55 +805,62 @@ static const struct tegra234_cbb_fabric tegra234_cbb_fabric = { ...@@ -728,55 +805,62 @@ static const struct tegra234_cbb_fabric tegra234_cbb_fabric = {
.name = "cbb-fabric", .name = "cbb-fabric",
.master_id = tegra234_master_id, .master_id = tegra234_master_id,
.slave_map = tegra234_cbb_slave_map, .slave_map = tegra234_cbb_slave_map,
.max_slaves = ARRAY_SIZE(tegra234_cbb_slave_map),
.errors = tegra234_cbb_errors, .errors = tegra234_cbb_errors,
.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
.notifier_offset = 0x60000, .notifier_offset = 0x60000,
.off_mask_erd = 0x3a004 .off_mask_erd = 0x3a004,
.firewall_base = 0x10000,
.firewall_ctl = 0x23f0,
.firewall_wr_ctl = 0x23e8,
}; };
static const struct tegra234_slave_lookup tegra234_dce_slave_map[] = { static const struct tegra234_slave_lookup tegra234_common_slave_map[] = {
{ "AXI2APB", 0x00000 }, { "AXI2APB", 0x00000 },
{ "AST0", 0x15000 }, { "AST0", 0x15000 },
{ "AST1", 0x16000 }, { "AST1", 0x16000 },
{ "CBB", 0x17000 },
{ "RSVD", 0x00000 },
{ "CPU", 0x18000 }, { "CPU", 0x18000 },
}; };
static const struct tegra234_cbb_fabric tegra234_dce_fabric = { static const struct tegra234_cbb_fabric tegra234_dce_fabric = {
.name = "dce-fabric", .name = "dce-fabric",
.master_id = tegra234_master_id, .master_id = tegra234_master_id,
.slave_map = tegra234_dce_slave_map, .slave_map = tegra234_common_slave_map,
.max_slaves = ARRAY_SIZE(tegra234_common_slave_map),
.errors = tegra234_cbb_errors, .errors = tegra234_cbb_errors,
.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
.notifier_offset = 0x19000, .notifier_offset = 0x19000,
}; .firewall_base = 0x30000,
.firewall_ctl = 0x290,
static const struct tegra234_slave_lookup tegra234_rce_slave_map[] = { .firewall_wr_ctl = 0x288,
{ "AXI2APB", 0x00000 },
{ "AST0", 0x15000 },
{ "AST1", 0x16000 },
{ "CPU", 0x18000 },
}; };
static const struct tegra234_cbb_fabric tegra234_rce_fabric = { static const struct tegra234_cbb_fabric tegra234_rce_fabric = {
.name = "rce-fabric", .name = "rce-fabric",
.master_id = tegra234_master_id, .master_id = tegra234_master_id,
.slave_map = tegra234_rce_slave_map, .slave_map = tegra234_common_slave_map,
.max_slaves = ARRAY_SIZE(tegra234_common_slave_map),
.errors = tegra234_cbb_errors, .errors = tegra234_cbb_errors,
.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
.notifier_offset = 0x19000, .notifier_offset = 0x19000,
}; .firewall_base = 0x30000,
.firewall_ctl = 0x290,
static const struct tegra234_slave_lookup tegra234_sce_slave_map[] = { .firewall_wr_ctl = 0x288,
{ "AXI2APB", 0x00000 },
{ "AST0", 0x15000 },
{ "AST1", 0x16000 },
{ "CBB", 0x17000 },
{ "CPU", 0x18000 },
}; };
static const struct tegra234_cbb_fabric tegra234_sce_fabric = { static const struct tegra234_cbb_fabric tegra234_sce_fabric = {
.name = "sce-fabric", .name = "sce-fabric",
.master_id = tegra234_master_id, .master_id = tegra234_master_id,
.slave_map = tegra234_sce_slave_map, .slave_map = tegra234_common_slave_map,
.max_slaves = ARRAY_SIZE(tegra234_common_slave_map),
.errors = tegra234_cbb_errors, .errors = tegra234_cbb_errors,
.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
.notifier_offset = 0x19000, .notifier_offset = 0x19000,
.firewall_base = 0x30000,
.firewall_ctl = 0x290,
.firewall_wr_ctl = 0x288,
}; };
static const char * const tegra241_master_id[] = { static const char * const tegra241_master_id[] = {
...@@ -889,7 +973,7 @@ static const struct tegra_cbb_error tegra241_cbb_errors[] = { ...@@ -889,7 +973,7 @@ static const struct tegra_cbb_error tegra241_cbb_errors[] = {
}; };
static const struct tegra234_slave_lookup tegra241_cbb_slave_map[] = { static const struct tegra234_slave_lookup tegra241_cbb_slave_map[] = {
{ "CCPLEX", 0x50000 }, { "RSVD", 0x00000 },
{ "PCIE_C8", 0x51000 }, { "PCIE_C8", 0x51000 },
{ "PCIE_C9", 0x52000 }, { "PCIE_C9", 0x52000 },
{ "RSVD", 0x00000 }, { "RSVD", 0x00000 },
...@@ -942,20 +1026,30 @@ static const struct tegra234_slave_lookup tegra241_cbb_slave_map[] = { ...@@ -942,20 +1026,30 @@ static const struct tegra234_slave_lookup tegra241_cbb_slave_map[] = {
{ "PCIE_C3", 0x58000 }, { "PCIE_C3", 0x58000 },
{ "PCIE_C0", 0x59000 }, { "PCIE_C0", 0x59000 },
{ "PCIE_C1", 0x5a000 }, { "PCIE_C1", 0x5a000 },
{ "CCPLEX", 0x50000 },
{ "AXI2APB_29", 0x85000 }, { "AXI2APB_29", 0x85000 },
{ "AXI2APB_30", 0x86000 }, { "AXI2APB_30", 0x86000 },
{ "CBB_CENTRAL", 0x00000 },
{ "AXI2APB_31", 0x8E000 },
{ "AXI2APB_32", 0x8F000 },
}; };
static const struct tegra234_cbb_fabric tegra241_cbb_fabric = { static const struct tegra234_cbb_fabric tegra241_cbb_fabric = {
.name = "cbb-fabric", .name = "cbb-fabric",
.master_id = tegra241_master_id, .master_id = tegra241_master_id,
.slave_map = tegra241_cbb_slave_map, .slave_map = tegra241_cbb_slave_map,
.max_slaves = ARRAY_SIZE(tegra241_cbb_slave_map),
.errors = tegra241_cbb_errors, .errors = tegra241_cbb_errors,
.max_errors = ARRAY_SIZE(tegra241_cbb_errors),
.notifier_offset = 0x60000, .notifier_offset = 0x60000,
.off_mask_erd = 0x40004, .off_mask_erd = 0x40004,
.firewall_base = 0x20000,
.firewall_ctl = 0x2370,
.firewall_wr_ctl = 0x2368,
}; };
static const struct tegra234_slave_lookup tegra241_bpmp_slave_map[] = { static const struct tegra234_slave_lookup tegra241_bpmp_slave_map[] = {
{ "RSVD", 0x00000 },
{ "RSVD", 0x00000 }, { "RSVD", 0x00000 },
{ "RSVD", 0x00000 }, { "RSVD", 0x00000 },
{ "CBB", 0x15000 }, { "CBB", 0x15000 },
...@@ -969,8 +1063,13 @@ static const struct tegra234_cbb_fabric tegra241_bpmp_fabric = { ...@@ -969,8 +1063,13 @@ static const struct tegra234_cbb_fabric tegra241_bpmp_fabric = {
.name = "bpmp-fabric", .name = "bpmp-fabric",
.master_id = tegra241_master_id, .master_id = tegra241_master_id,
.slave_map = tegra241_bpmp_slave_map, .slave_map = tegra241_bpmp_slave_map,
.max_slaves = ARRAY_SIZE(tegra241_bpmp_slave_map),
.errors = tegra241_cbb_errors, .errors = tegra241_cbb_errors,
.max_errors = ARRAY_SIZE(tegra241_cbb_errors),
.notifier_offset = 0x19000, .notifier_offset = 0x19000,
.firewall_base = 0x30000,
.firewall_ctl = 0x8f0,
.firewall_wr_ctl = 0x8e8,
}; };
static const struct of_device_id tegra234_cbb_dt_ids[] = { static const struct of_device_id tegra234_cbb_dt_ids[] = {
...@@ -1055,6 +1154,15 @@ static int tegra234_cbb_probe(struct platform_device *pdev) ...@@ -1055,6 +1154,15 @@ static int tegra234_cbb_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, cbb); platform_set_drvdata(pdev, cbb);
/*
* Don't enable error reporting for a Fabric if write to it's registers
* is blocked by CBB firewall.
*/
if (!tegra234_cbb_write_access_allowed(pdev, cbb)) {
dev_info(&pdev->dev, "error reporting not enabled due to firewall\n");
return 0;
}
spin_lock_irqsave(&cbb_lock, flags); spin_lock_irqsave(&cbb_lock, flags);
list_add(&cbb->base.node, &cbb_list); list_add(&cbb->base.node, &cbb_list);
spin_unlock_irqrestore(&cbb_lock, flags); spin_unlock_irqrestore(&cbb_lock, flags);
......
drivers/soc/tegra/fuse/fuse-tegra.c
View file @ 2a26daee
...@@ -35,6 +35,19 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { ...@@ -35,6 +35,19 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
[TEGRA_REVISION_A04] = "A04", [TEGRA_REVISION_A04] = "A04",
}; };
static const char *tegra_platform_name[TEGRA_PLATFORM_MAX] = {
[TEGRA_PLATFORM_SILICON] = "Silicon",
[TEGRA_PLATFORM_QT] = "QT",
[TEGRA_PLATFORM_SYSTEM_FPGA] = "System FPGA",
[TEGRA_PLATFORM_UNIT_FPGA] = "Unit FPGA",
[TEGRA_PLATFORM_ASIM_QT] = "Asim QT",
[TEGRA_PLATFORM_ASIM_LINSIM] = "Asim Linsim",
[TEGRA_PLATFORM_DSIM_ASIM_LINSIM] = "Dsim Asim Linsim",
[TEGRA_PLATFORM_VERIFICATION_SIMULATION] = "Verification Simulation",
[TEGRA_PLATFORM_VDK] = "VDK",
[TEGRA_PLATFORM_VSP] = "VSP",
};
static const struct of_device_id car_match[] __initconst = { static const struct of_device_id car_match[] __initconst = {
{ .compatible = "nvidia,tegra20-car", }, { .compatible = "nvidia,tegra20-car", },
{ .compatible = "nvidia,tegra30-car", }, { .compatible = "nvidia,tegra30-car", },
...@@ -94,112 +107,6 @@ static int tegra_fuse_read(void *priv, unsigned int offset, void *value, ...@@ -94,112 +107,6 @@ static int tegra_fuse_read(void *priv, unsigned int offset, void *value,
return 0; return 0;
} }
static const struct nvmem_cell_info tegra_fuse_cells[] = {
{
.name = "tsensor-cpu1",
.offset = 0x084,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-cpu2",
.offset = 0x088,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-cpu0",
.offset = 0x098,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "xusb-pad-calibration",
.offset = 0x0f0,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-cpu3",
.offset = 0x12c,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "sata-calibration",
.offset = 0x124,
.bytes = 1,
.bit_offset = 0,
.nbits = 2,
}, {
.name = "tsensor-gpu",
.offset = 0x154,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-mem0",
.offset = 0x158,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-mem1",
.offset = 0x15c,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-pllx",
.offset = 0x160,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-common",
.offset = 0x180,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "gpu-gcplex-config-fuse",
.offset = 0x1c8,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-realignment",
.offset = 0x1fc,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "gpu-calibration",
.offset = 0x204,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "xusb-pad-calibration-ext",
.offset = 0x250,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "gpu-pdi0",
.offset = 0x300,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "gpu-pdi1",
.offset = 0x304,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
},
};
static void tegra_fuse_restore(void *base) static void tegra_fuse_restore(void *base)
{ {
fuse->base = (void __iomem *)base; fuse->base = (void __iomem *)base;
...@@ -253,8 +160,10 @@ static int tegra_fuse_probe(struct platform_device *pdev) ...@@ -253,8 +160,10 @@ static int tegra_fuse_probe(struct platform_device *pdev)
nvmem.name = "fuse"; nvmem.name = "fuse";
nvmem.id = -1; nvmem.id = -1;
nvmem.owner = THIS_MODULE; nvmem.owner = THIS_MODULE;
nvmem.cells = tegra_fuse_cells; nvmem.cells = fuse->soc->cells;
nvmem.ncells = ARRAY_SIZE(tegra_fuse_cells); nvmem.ncells = fuse->soc->num_cells;
nvmem.keepout = fuse->soc->keepouts;
nvmem.nkeepout = fuse->soc->num_keepouts;
nvmem.type = NVMEM_TYPE_OTP; nvmem.type = NVMEM_TYPE_OTP;
nvmem.read_only = true; nvmem.read_only = true;
nvmem.root_only = true; nvmem.root_only = true;
...@@ -474,8 +383,13 @@ struct device * __init tegra_soc_device_register(void) ...@@ -474,8 +383,13 @@ struct device * __init tegra_soc_device_register(void)
return NULL; return NULL;
attr->family = kasprintf(GFP_KERNEL, "Tegra"); attr->family = kasprintf(GFP_KERNEL, "Tegra");
attr->revision = kasprintf(GFP_KERNEL, "%s", if (tegra_is_silicon())
tegra_revision_name[tegra_sku_info.revision]); attr->revision = kasprintf(GFP_KERNEL, "%s %s",
tegra_platform_name[tegra_sku_info.platform],
tegra_revision_name[tegra_sku_info.revision]);
else
attr->revision = kasprintf(GFP_KERNEL, "%s",
tegra_platform_name[tegra_sku_info.platform]);
attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id()); attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id());
attr->custom_attr_group = fuse->soc->soc_attr_group; attr->custom_attr_group = fuse->soc->soc_attr_group;
......
drivers/soc/tegra/fuse/fuse-tegra30.c
View file @ 2a26daee
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/nvmem-consumer.h> #include <linux/nvmem-consumer.h>
#include <linux/nvmem-provider.h>
#include <linux/of_device.h> #include <linux/of_device.h>
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
...@@ -133,6 +134,82 @@ const struct tegra_fuse_soc tegra114_fuse_soc = { ...@@ -133,6 +134,82 @@ const struct tegra_fuse_soc tegra114_fuse_soc = {
#endif #endif
#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
static const struct nvmem_cell_info tegra124_fuse_cells[] = {
{
.name = "tsensor-cpu1",
.offset = 0x084,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-cpu2",
.offset = 0x088,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-cpu0",
.offset = 0x098,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "xusb-pad-calibration",
.offset = 0x0f0,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-cpu3",
.offset = 0x12c,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "sata-calibration",
.offset = 0x124,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-gpu",
.offset = 0x154,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-mem0",
.offset = 0x158,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-mem1",
.offset = 0x15c,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-pllx",
.offset = 0x160,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-common",
.offset = 0x180,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-realignment",
.offset = 0x1fc,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
},
};
static const struct nvmem_cell_lookup tegra124_fuse_lookups[] = { static const struct nvmem_cell_lookup tegra124_fuse_lookups[] = {
{ {
.nvmem_name = "fuse", .nvmem_name = "fuse",
...@@ -209,12 +286,96 @@ const struct tegra_fuse_soc tegra124_fuse_soc = { ...@@ -209,12 +286,96 @@ const struct tegra_fuse_soc tegra124_fuse_soc = {
.info = &tegra124_fuse_info, .info = &tegra124_fuse_info,
.lookups = tegra124_fuse_lookups, .lookups = tegra124_fuse_lookups,
.num_lookups = ARRAY_SIZE(tegra124_fuse_lookups), .num_lookups = ARRAY_SIZE(tegra124_fuse_lookups),
.cells = tegra124_fuse_cells,
.num_cells = ARRAY_SIZE(tegra124_fuse_cells),
.soc_attr_group = &tegra_soc_attr_group, .soc_attr_group = &tegra_soc_attr_group,
.clk_suspend_on = true, .clk_suspend_on = true,
}; };
#endif #endif
#if defined(CONFIG_ARCH_TEGRA_210_SOC) #if defined(CONFIG_ARCH_TEGRA_210_SOC)
static const struct nvmem_cell_info tegra210_fuse_cells[] = {
{
.name = "tsensor-cpu1",
.offset = 0x084,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-cpu2",
.offset = 0x088,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-cpu0",
.offset = 0x098,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "xusb-pad-calibration",
.offset = 0x0f0,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-cpu3",
.offset = 0x12c,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "sata-calibration",
.offset = 0x124,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-gpu",
.offset = 0x154,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-mem0",
.offset = 0x158,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-mem1",
.offset = 0x15c,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-pllx",
.offset = 0x160,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-common",
.offset = 0x180,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "gpu-calibration",
.offset = 0x204,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "xusb-pad-calibration-ext",
.offset = 0x250,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
},
};
static const struct nvmem_cell_lookup tegra210_fuse_lookups[] = { static const struct nvmem_cell_lookup tegra210_fuse_lookups[] = {
{ {
.nvmem_name = "fuse", .nvmem_name = "fuse",
...@@ -295,6 +456,8 @@ const struct tegra_fuse_soc tegra210_fuse_soc = { ...@@ -295,6 +456,8 @@ const struct tegra_fuse_soc tegra210_fuse_soc = {
.speedo_init = tegra210_init_speedo_data, .speedo_init = tegra210_init_speedo_data,
.info = &tegra210_fuse_info, .info = &tegra210_fuse_info,
.lookups = tegra210_fuse_lookups, .lookups = tegra210_fuse_lookups,
.cells = tegra210_fuse_cells,
.num_cells = ARRAY_SIZE(tegra210_fuse_cells),
.num_lookups = ARRAY_SIZE(tegra210_fuse_lookups), .num_lookups = ARRAY_SIZE(tegra210_fuse_lookups),
.soc_attr_group = &tegra_soc_attr_group, .soc_attr_group = &tegra_soc_attr_group,
.clk_suspend_on = false, .clk_suspend_on = false,
...@@ -302,6 +465,22 @@ const struct tegra_fuse_soc tegra210_fuse_soc = { ...@@ -302,6 +465,22 @@ const struct tegra_fuse_soc tegra210_fuse_soc = {
#endif #endif
#if defined(CONFIG_ARCH_TEGRA_186_SOC) #if defined(CONFIG_ARCH_TEGRA_186_SOC)
static const struct nvmem_cell_info tegra186_fuse_cells[] = {
{
.name = "xusb-pad-calibration",
.offset = 0x0f0,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "xusb-pad-calibration-ext",
.offset = 0x250,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
},
};
static const struct nvmem_cell_lookup tegra186_fuse_lookups[] = { static const struct nvmem_cell_lookup tegra186_fuse_lookups[] = {
{ {
.nvmem_name = "fuse", .nvmem_name = "fuse",
...@@ -316,9 +495,17 @@ static const struct nvmem_cell_lookup tegra186_fuse_lookups[] = { ...@@ -316,9 +495,17 @@ static const struct nvmem_cell_lookup tegra186_fuse_lookups[] = {
}, },
}; };
static const struct nvmem_keepout tegra186_fuse_keepouts[] = {
{ .start = 0x01c, .end = 0x0f0 },
{ .start = 0x138, .end = 0x198 },
{ .start = 0x1d8, .end = 0x250 },
{ .start = 0x280, .end = 0x290 },
{ .start = 0x340, .end = 0x344 }
};
static const struct tegra_fuse_info tegra186_fuse_info = { static const struct tegra_fuse_info tegra186_fuse_info = {
.read = tegra30_fuse_read, .read = tegra30_fuse_read,
.size = 0x300, .size = 0x478,
.spare = 0x280, .spare = 0x280,
}; };
...@@ -327,12 +514,50 @@ const struct tegra_fuse_soc tegra186_fuse_soc = { ...@@ -327,12 +514,50 @@ const struct tegra_fuse_soc tegra186_fuse_soc = {
.info = &tegra186_fuse_info, .info = &tegra186_fuse_info,
.lookups = tegra186_fuse_lookups, .lookups = tegra186_fuse_lookups,
.num_lookups = ARRAY_SIZE(tegra186_fuse_lookups), .num_lookups = ARRAY_SIZE(tegra186_fuse_lookups),
.cells = tegra186_fuse_cells,
.num_cells = ARRAY_SIZE(tegra186_fuse_cells),
.keepouts = tegra186_fuse_keepouts,
.num_keepouts = ARRAY_SIZE(tegra186_fuse_keepouts),
.soc_attr_group = &tegra_soc_attr_group, .soc_attr_group = &tegra_soc_attr_group,
.clk_suspend_on = false, .clk_suspend_on = false,
}; };
#endif #endif
#if defined(CONFIG_ARCH_TEGRA_194_SOC) #if defined(CONFIG_ARCH_TEGRA_194_SOC)
static const struct nvmem_cell_info tegra194_fuse_cells[] = {
{
.name = "xusb-pad-calibration",
.offset = 0x0f0,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "gpu-gcplex-config-fuse",
.offset = 0x1c8,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "xusb-pad-calibration-ext",
.offset = 0x250,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "gpu-pdi0",
.offset = 0x300,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "gpu-pdi1",
.offset = 0x304,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
},
};
static const struct nvmem_cell_lookup tegra194_fuse_lookups[] = { static const struct nvmem_cell_lookup tegra194_fuse_lookups[] = {
{ {
.nvmem_name = "fuse", .nvmem_name = "fuse",
...@@ -362,9 +587,18 @@ static const struct nvmem_cell_lookup tegra194_fuse_lookups[] = { ...@@ -362,9 +587,18 @@ static const struct nvmem_cell_lookup tegra194_fuse_lookups[] = {
}, },
}; };
static const struct nvmem_keepout tegra194_fuse_keepouts[] = {
{ .start = 0x01c, .end = 0x0b8 },
{ .start = 0x12c, .end = 0x198 },
{ .start = 0x1a0, .end = 0x1bc },
{ .start = 0x1d8, .end = 0x250 },
{ .start = 0x270, .end = 0x290 },
{ .start = 0x310, .end = 0x45c }
};
static const struct tegra_fuse_info tegra194_fuse_info = { static const struct tegra_fuse_info tegra194_fuse_info = {
.read = tegra30_fuse_read, .read = tegra30_fuse_read,
.size = 0x300, .size = 0x650,
.spare = 0x280, .spare = 0x280,
}; };
...@@ -373,12 +607,32 @@ const struct tegra_fuse_soc tegra194_fuse_soc = { ...@@ -373,12 +607,32 @@ const struct tegra_fuse_soc tegra194_fuse_soc = {
.info = &tegra194_fuse_info, .info = &tegra194_fuse_info,
.lookups = tegra194_fuse_lookups, .lookups = tegra194_fuse_lookups,
.num_lookups = ARRAY_SIZE(tegra194_fuse_lookups), .num_lookups = ARRAY_SIZE(tegra194_fuse_lookups),
.cells = tegra194_fuse_cells,
.num_cells = ARRAY_SIZE(tegra194_fuse_cells),
.keepouts = tegra194_fuse_keepouts,
.num_keepouts = ARRAY_SIZE(tegra194_fuse_keepouts),
.soc_attr_group = &tegra194_soc_attr_group, .soc_attr_group = &tegra194_soc_attr_group,
.clk_suspend_on = false, .clk_suspend_on = false,
}; };
#endif #endif
#if defined(CONFIG_ARCH_TEGRA_234_SOC) #if defined(CONFIG_ARCH_TEGRA_234_SOC)
static const struct nvmem_cell_info tegra234_fuse_cells[] = {
{
.name = "xusb-pad-calibration",
.offset = 0x0f0,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "xusb-pad-calibration-ext",
.offset = 0x250,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
},
};
static const struct nvmem_cell_lookup tegra234_fuse_lookups[] = { static const struct nvmem_cell_lookup tegra234_fuse_lookups[] = {
{ {
.nvmem_name = "fuse", .nvmem_name = "fuse",
...@@ -393,9 +647,23 @@ static const struct nvmem_cell_lookup tegra234_fuse_lookups[] = { ...@@ -393,9 +647,23 @@ static const struct nvmem_cell_lookup tegra234_fuse_lookups[] = {
}, },
}; };
static const struct nvmem_keepout tegra234_fuse_keepouts[] = {
{ .start = 0x01c, .end = 0x0c8 },
{ .start = 0x12c, .end = 0x184 },
{ .start = 0x190, .end = 0x198 },
{ .start = 0x1a0, .end = 0x204 },
{ .start = 0x21c, .end = 0x250 },
{ .start = 0x25c, .end = 0x2f0 },
{ .start = 0x310, .end = 0x3d8 },
{ .start = 0x400, .end = 0x4f0 },
{ .start = 0x4f8, .end = 0x7e8 },
{ .start = 0x8d0, .end = 0x8d8 },
{ .start = 0xacc, .end = 0xf00 }
};
static const struct tegra_fuse_info tegra234_fuse_info = { static const struct tegra_fuse_info tegra234_fuse_info = {
.read = tegra30_fuse_read, .read = tegra30_fuse_read,
.size = 0x300, .size = 0x98c,
.spare = 0x280, .spare = 0x280,
}; };
...@@ -404,6 +672,10 @@ const struct tegra_fuse_soc tegra234_fuse_soc = { ...@@ -404,6 +672,10 @@ const struct tegra_fuse_soc tegra234_fuse_soc = {
.info = &tegra234_fuse_info, .info = &tegra234_fuse_info,
.lookups = tegra234_fuse_lookups, .lookups = tegra234_fuse_lookups,
.num_lookups = ARRAY_SIZE(tegra234_fuse_lookups), .num_lookups = ARRAY_SIZE(tegra234_fuse_lookups),
.cells = tegra234_fuse_cells,
.num_cells = ARRAY_SIZE(tegra234_fuse_cells),
.keepouts = tegra234_fuse_keepouts,
.num_keepouts = ARRAY_SIZE(tegra234_fuse_keepouts),
.soc_attr_group = &tegra194_soc_attr_group, .soc_attr_group = &tegra194_soc_attr_group,
.clk_suspend_on = false, .clk_suspend_on = false,
}; };
......
drivers/soc/tegra/fuse/fuse.h
View file @ 2a26daee
...@@ -32,6 +32,10 @@ struct tegra_fuse_soc { ...@@ -32,6 +32,10 @@ struct tegra_fuse_soc {
const struct nvmem_cell_lookup *lookups; const struct nvmem_cell_lookup *lookups;
unsigned int num_lookups; unsigned int num_lookups;
const struct nvmem_cell_info *cells;
unsigned int num_cells;
const struct nvmem_keepout *keepouts;
unsigned int num_keepouts;
const struct attribute_group *soc_attr_group; const struct attribute_group *soc_attr_group;
......
drivers/soc/tegra/fuse/tegra-apbmisc.c
View file @ 2a26daee
...@@ -156,6 +156,7 @@ void __init tegra_init_revision(void) ...@@ -156,6 +156,7 @@ void __init tegra_init_revision(void)
} }
tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO); tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO);
tegra_sku_info.platform = tegra_get_platform();
} }
void __init tegra_init_apbmisc(void) void __init tegra_init_apbmisc(void)
......
drivers/soc/tegra/pmc.c
View file @ 2a26daee
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/export.h> #include <linux/export.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/iopoll.h> #include <linux/iopoll.h>
#include <linux/irqdomain.h> #include <linux/irqdomain.h>
...@@ -46,6 +47,7 @@ ...@@ -46,6 +47,7 @@
#include <linux/seq_file.h> #include <linux/seq_file.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/spinlock.h> #include <linux/spinlock.h>
#include <linux/syscore_ops.h>
#include <soc/tegra/common.h> #include <soc/tegra/common.h>
#include <soc/tegra/fuse.h> #include <soc/tegra/fuse.h>
...@@ -182,6 +184,9 @@ ...@@ -182,6 +184,9 @@
#define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2)) #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
#define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2)) #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
#define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2)) #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
#define WAKE_AOWAKE_SW_STATUS_W_0 0x49c
#define WAKE_AOWAKE_SW_STATUS(x) (0x4a0 + ((x) << 2))
#define WAKE_LATCH_SW 0x498
#define WAKE_AOWAKE_CTRL 0x4f4 #define WAKE_AOWAKE_CTRL 0x4f4
#define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
...@@ -269,16 +274,14 @@ struct tegra_powergate { ...@@ -269,16 +274,14 @@ struct tegra_powergate {
struct tegra_io_pad_soc { struct tegra_io_pad_soc {
enum tegra_io_pad id; enum tegra_io_pad id;
unsigned int dpd; unsigned int dpd;
unsigned int request;
unsigned int status;
unsigned int voltage; unsigned int voltage;
const char *name; const char *name;
}; };
struct tegra_pmc_regs { struct tegra_pmc_regs {
unsigned int scratch0; unsigned int scratch0;
unsigned int dpd_req;
unsigned int dpd_status;
unsigned int dpd2_req;
unsigned int dpd2_status;
unsigned int rst_status; unsigned int rst_status;
unsigned int rst_source_shift; unsigned int rst_source_shift;
unsigned int rst_source_mask; unsigned int rst_source_mask;
...@@ -369,6 +372,8 @@ struct tegra_pmc_soc { ...@@ -369,6 +372,8 @@ struct tegra_pmc_soc {
*/ */
const struct tegra_wake_event *wake_events; const struct tegra_wake_event *wake_events;
unsigned int num_wake_events; unsigned int num_wake_events;
unsigned int max_wake_events;
unsigned int max_wake_vectors;
const struct pmc_clk_init_data *pmc_clks_data; const struct pmc_clk_init_data *pmc_clks_data;
unsigned int num_pmc_clks; unsigned int num_pmc_clks;
...@@ -409,6 +414,11 @@ struct tegra_pmc_soc { ...@@ -409,6 +414,11 @@ struct tegra_pmc_soc {
* @clk_nb: pclk clock changes handler * @clk_nb: pclk clock changes handler
* @core_domain_state_synced: flag marking the core domain's state as synced * @core_domain_state_synced: flag marking the core domain's state as synced
* @core_domain_registered: flag marking the core domain as registered * @core_domain_registered: flag marking the core domain as registered
* @wake_type_level_map: Bitmap indicating level type for non-dual edge wakes
* @wake_type_dual_edge_map: Bitmap indicating if a wake is dual-edge or not
* @wake_sw_status_map: Bitmap to hold raw status of wakes without mask
* @wake_cntrl_level_map: Bitmap to hold wake levels to be programmed in
* cntrl register associated with each wake during system suspend.
*/ */
struct tegra_pmc { struct tegra_pmc {
struct device *dev; struct device *dev;
...@@ -449,6 +459,12 @@ struct tegra_pmc { ...@@ -449,6 +459,12 @@ struct tegra_pmc {
bool core_domain_state_synced; bool core_domain_state_synced;
bool core_domain_registered; bool core_domain_registered;
unsigned long *wake_type_level_map;
unsigned long *wake_type_dual_edge_map;
unsigned long *wake_sw_status_map;
unsigned long *wake_cntrl_level_map;
struct syscore_ops syscore;
}; };
static struct tegra_pmc *pmc = &(struct tegra_pmc) { static struct tegra_pmc *pmc = &(struct tegra_pmc) {
...@@ -1540,46 +1556,20 @@ tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) ...@@ -1540,46 +1556,20 @@ tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
return NULL; return NULL;
} }
static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc, static int tegra_io_pad_prepare(struct tegra_pmc *pmc,
enum tegra_io_pad id, const struct tegra_io_pad_soc *pad,
unsigned long *request, unsigned long *request,
unsigned long *status, unsigned long *status,
u32 *mask)
{
const struct tegra_io_pad_soc *pad;
pad = tegra_io_pad_find(pmc, id);
if (!pad) {
dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
return -ENOENT;
}
if (pad->dpd == UINT_MAX)
return -ENOTSUPP;
*mask = BIT(pad->dpd % 32);
if (pad->dpd < 32) {
*status = pmc->soc->regs->dpd_status;
*request = pmc->soc->regs->dpd_req;
} else {
*status = pmc->soc->regs->dpd2_status;
*request = pmc->soc->regs->dpd2_req;
}
return 0;
}
static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id,
unsigned long *request, unsigned long *status,
u32 *mask) u32 *mask)
{ {
unsigned long rate, value; unsigned long rate, value;
int err;
err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask); if (pad->dpd == UINT_MAX)
if (err) return -EINVAL;
return err;
*request = pad->request;
*status = pad->status;
*mask = BIT(pad->dpd);
if (pmc->clk) { if (pmc->clk) {
rate = pmc->rate; rate = pmc->rate;
...@@ -1631,13 +1621,20 @@ static void tegra_io_pad_unprepare(struct tegra_pmc *pmc) ...@@ -1631,13 +1621,20 @@ static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
*/ */
int tegra_io_pad_power_enable(enum tegra_io_pad id) int tegra_io_pad_power_enable(enum tegra_io_pad id)
{ {
const struct tegra_io_pad_soc *pad;
unsigned long request, status; unsigned long request, status;
u32 mask; u32 mask;
int err; int err;
pad = tegra_io_pad_find(pmc, id);
if (!pad) {
dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
return -ENOENT;
}
mutex_lock(&pmc->powergates_lock); mutex_lock(&pmc->powergates_lock);
err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask);
if (err < 0) { if (err < 0) {
dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
goto unlock; goto unlock;
...@@ -1667,13 +1664,20 @@ EXPORT_SYMBOL(tegra_io_pad_power_enable); ...@@ -1667,13 +1664,20 @@ EXPORT_SYMBOL(tegra_io_pad_power_enable);
*/ */
int tegra_io_pad_power_disable(enum tegra_io_pad id) int tegra_io_pad_power_disable(enum tegra_io_pad id)
{ {
const struct tegra_io_pad_soc *pad;
unsigned long request, status; unsigned long request, status;
u32 mask; u32 mask;
int err; int err;
pad = tegra_io_pad_find(pmc, id);
if (!pad) {
dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
return -ENOENT;
}
mutex_lock(&pmc->powergates_lock); mutex_lock(&pmc->powergates_lock);
err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask);
if (err < 0) { if (err < 0) {
dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
goto unlock; goto unlock;
...@@ -1697,14 +1701,21 @@ EXPORT_SYMBOL(tegra_io_pad_power_disable); ...@@ -1697,14 +1701,21 @@ EXPORT_SYMBOL(tegra_io_pad_power_disable);
static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id) static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
{ {
unsigned long request, status; const struct tegra_io_pad_soc *pad;
unsigned long status;
u32 mask, value; u32 mask, value;
int err;
err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status, pad = tegra_io_pad_find(pmc, id);
&mask); if (!pad) {
if (err) dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
return err; return -ENOENT;
}
if (pad->dpd == UINT_MAX)
return -EINVAL;
status = pad->status;
mask = BIT(pad->dpd);
value = tegra_pmc_readl(pmc, status); value = tegra_pmc_readl(pmc, status);
...@@ -1930,10 +1941,30 @@ static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) ...@@ -1930,10 +1941,30 @@ static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
return 0; return 0;
} }
static void tegra_pmc_init(struct tegra_pmc *pmc) static int tegra_pmc_init(struct tegra_pmc *pmc)
{ {
if (pmc->soc->max_wake_events > 0) {
pmc->wake_type_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
if (!pmc->wake_type_level_map)
return -ENOMEM;
pmc->wake_type_dual_edge_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
if (!pmc->wake_type_dual_edge_map)
return -ENOMEM;
pmc->wake_sw_status_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
if (!pmc->wake_sw_status_map)
return -ENOMEM;
pmc->wake_cntrl_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
if (!pmc->wake_cntrl_level_map)
return -ENOMEM;
}
if (pmc->soc->init) if (pmc->soc->init)
pmc->soc->init(pmc); pmc->soc->init(pmc);
return 0;
} }
static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
...@@ -2424,15 +2455,21 @@ static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) ...@@ -2424,15 +2455,21 @@ static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type)
case IRQ_TYPE_EDGE_RISING: case IRQ_TYPE_EDGE_RISING:
case IRQ_TYPE_LEVEL_HIGH: case IRQ_TYPE_LEVEL_HIGH:
value |= WAKE_AOWAKE_CNTRL_LEVEL; value |= WAKE_AOWAKE_CNTRL_LEVEL;
set_bit(data->hwirq, pmc->wake_type_level_map);
clear_bit(data->hwirq, pmc->wake_type_dual_edge_map);
break; break;
case IRQ_TYPE_EDGE_FALLING: case IRQ_TYPE_EDGE_FALLING:
case IRQ_TYPE_LEVEL_LOW: case IRQ_TYPE_LEVEL_LOW:
value &= ~WAKE_AOWAKE_CNTRL_LEVEL; value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
clear_bit(data->hwirq, pmc->wake_type_level_map);
clear_bit(data->hwirq, pmc->wake_type_dual_edge_map);
break; break;
case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
value ^= WAKE_AOWAKE_CNTRL_LEVEL; value ^= WAKE_AOWAKE_CNTRL_LEVEL;
clear_bit(data->hwirq, pmc->wake_type_level_map);
set_bit(data->hwirq, pmc->wake_type_dual_edge_map);
break; break;
default: default:
...@@ -2964,7 +3001,11 @@ static int tegra_pmc_probe(struct platform_device *pdev) ...@@ -2964,7 +3001,11 @@ static int tegra_pmc_probe(struct platform_device *pdev)
pmc->dev = &pdev->dev; pmc->dev = &pdev->dev;
tegra_pmc_init(pmc); err = tegra_pmc_init(pmc);
if (err < 0) {
dev_err(&pdev->dev, "failed to initialize PMC: %d\n", err);
return err;
}
tegra_pmc_init_tsense_reset(pmc); tegra_pmc_init_tsense_reset(pmc);
...@@ -3015,6 +3056,156 @@ static int tegra_pmc_probe(struct platform_device *pdev) ...@@ -3015,6 +3056,156 @@ static int tegra_pmc_probe(struct platform_device *pdev)
return err; return err;
} }
/*
* Ensures that sufficient time is passed for a register write to
* serialize into the 32KHz domain.
*/
static void wke_32kwritel(struct tegra_pmc *pmc, u32 value, unsigned int offset)
{
writel(value, pmc->wake + offset);
udelay(130);
}
static void wke_write_wake_level(struct tegra_pmc *pmc, int wake, int level)
{
unsigned int offset = WAKE_AOWAKE_CNTRL(wake);
u32 value;
value = readl(pmc->wake + offset);
if (level)
value |= WAKE_AOWAKE_CNTRL_LEVEL;
else
value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
writel(value, pmc->wake + offset);
}
static void wke_write_wake_levels(struct tegra_pmc *pmc)
{
unsigned int i;
for (i = 0; i < pmc->soc->max_wake_events; i++)
wke_write_wake_level(pmc, i, test_bit(i, pmc->wake_cntrl_level_map));
}
static void wke_clear_sw_wake_status(struct tegra_pmc *pmc)
{
wke_32kwritel(pmc, 1, WAKE_AOWAKE_SW_STATUS_W_0);
}
static void wke_read_sw_wake_status(struct tegra_pmc *pmc)
{
unsigned long status;
unsigned int wake, i;
for (i = 0; i < pmc->soc->max_wake_events; i++)
wke_write_wake_level(pmc, i, 0);
wke_clear_sw_wake_status(pmc);
wke_32kwritel(pmc, 1, WAKE_LATCH_SW);
/*
* WAKE_AOWAKE_SW_STATUS is edge triggered, so in order to
* obtain the current status of the input wake signals, change
* the polarity of the wake level from 0->1 while latching to force
* a positive edge if the sampled signal is '1'.
*/
for (i = 0; i < pmc->soc->max_wake_events; i++)
wke_write_wake_level(pmc, i, 1);
/*
* Wait for the update to be synced into the 32kHz domain,
* and let enough time lapse, so that the wake signals have time to
* be sampled.
*/
udelay(300);
wke_32kwritel(pmc, 0, WAKE_LATCH_SW);
bitmap_zero(pmc->wake_sw_status_map, pmc->soc->max_wake_events);
for (i = 0; i < pmc->soc->max_wake_vectors; i++) {
status = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(i));
for_each_set_bit(wake, &status, 32)
set_bit(wake + (i * 32), pmc->wake_sw_status_map);
}
}
static void wke_clear_wake_status(struct tegra_pmc *pmc)
{
unsigned long status;
unsigned int i, wake;
u32 mask;
for (i = 0; i < pmc->soc->max_wake_vectors; i++) {
mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i));
status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask;
for_each_set_bit(wake, &status, 32)
wke_32kwritel(pmc, 0x1, WAKE_AOWAKE_STATUS_W((i * 32) + wake));
}
}
/* translate sc7 wake sources back into IRQs to catch edge triggered wakeups */
static void tegra186_pmc_process_wake_events(struct tegra_pmc *pmc, unsigned int index,
unsigned long status)
{
unsigned int wake;
dev_dbg(pmc->dev, "Wake[%d:%d] status=%#lx\n", (index * 32) + 31, index * 32, status);
for_each_set_bit(wake, &status, 32) {
irq_hw_number_t hwirq = wake + 32 * index;
struct irq_desc *desc;
unsigned int irq;
irq = irq_find_mapping(pmc->domain, hwirq);
desc = irq_to_desc(irq);
if (!desc || !desc->action || !desc->action->name) {
dev_dbg(pmc->dev, "Resume caused by WAKE%ld, IRQ %d\n", hwirq, irq);
continue;
}
dev_dbg(pmc->dev, "Resume caused by WAKE%ld, %s\n", hwirq, desc->action->name);
generic_handle_irq(irq);
}
}
static void tegra186_pmc_wake_syscore_resume(void)
{
u32 status, mask;
unsigned int i;
for (i = 0; i < pmc->soc->max_wake_vectors; i++) {
mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i));
status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask;
tegra186_pmc_process_wake_events(pmc, i, status);
}
}
static int tegra186_pmc_wake_syscore_suspend(void)
{
wke_read_sw_wake_status(pmc);
/* flip the wakeup trigger for dual-edge triggered pads
* which are currently asserting as wakeups
*/
bitmap_andnot(pmc->wake_cntrl_level_map, pmc->wake_type_dual_edge_map,
pmc->wake_sw_status_map, pmc->soc->max_wake_events);
bitmap_or(pmc->wake_cntrl_level_map, pmc->wake_cntrl_level_map,
pmc->wake_type_level_map, pmc->soc->max_wake_events);
/* Clear PMC Wake Status registers while going to suspend */
wke_clear_wake_status(pmc);
wke_write_wake_levels(pmc);
return 0;
}
#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
static int tegra_pmc_suspend(struct device *dev) static int tegra_pmc_suspend(struct device *dev)
{ {
...@@ -3050,10 +3241,6 @@ static const char * const tegra20_powergates[] = { ...@@ -3050,10 +3241,6 @@ static const char * const tegra20_powergates[] = {
static const struct tegra_pmc_regs tegra20_pmc_regs = { static const struct tegra_pmc_regs tegra20_pmc_regs = {
.scratch0 = 0x50, .scratch0 = 0x50,
.dpd_req = 0x1b8,
.dpd_status = 0x1bc,
.dpd2_req = 0x1c0,
.dpd2_status = 0x1c4,
.rst_status = 0x1b4, .rst_status = 0x1b4,
.rst_source_shift = 0x0, .rst_source_shift = 0x0,
.rst_source_mask = 0x7, .rst_source_mask = 0x7,
...@@ -3297,59 +3484,86 @@ static const u8 tegra124_cpu_powergates[] = { ...@@ -3297,59 +3484,86 @@ static const u8 tegra124_cpu_powergates[] = {
TEGRA_POWERGATE_CPU3, TEGRA_POWERGATE_CPU3,
}; };
#define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \ #define TEGRA_IO_PAD(_id, _dpd, _request, _status, _voltage, _name) \
((struct tegra_io_pad_soc) { \ ((struct tegra_io_pad_soc) { \
.id = (_id), \ .id = (_id), \
.dpd = (_dpd), \ .dpd = (_dpd), \
.voltage = (_voltage), \ .request = (_request), \
.name = (_name), \ .status = (_status), \
.voltage = (_voltage), \
.name = (_name), \
}) })
#define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \ #define TEGRA_IO_PIN_DESC(_id, _name) \
((struct pinctrl_pin_desc) { \ ((struct pinctrl_pin_desc) { \
.number = (_id), \ .number = (_id), \
.name = (_name) \ .name = (_name), \
}) })
#define TEGRA124_IO_PAD_TABLE(_pad) \
/* .id .dpd .voltage .name */ \
_pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
_pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \
_pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \
_pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \
_pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
_pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \
_pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \
_pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
_pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
_pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
_pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
_pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
_pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
_pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \
_pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
_pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
_pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \
_pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
_pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
_pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
_pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
_pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \
_pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \
_pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \
_pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \
_pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
_pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
_pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
_pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
_pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias")
static const struct tegra_io_pad_soc tegra124_io_pads[] = { static const struct tegra_io_pad_soc tegra124_io_pads[] = {
TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD) TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, UINT_MAX, "audio"),
TEGRA_IO_PAD(TEGRA_IO_PAD_BB, 15, 0x1b8, 0x1bc, UINT_MAX, "bb"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, UINT_MAX, "cam"),
TEGRA_IO_PAD(TEGRA_IO_PAD_COMP, 22, 0x1b8, 0x1bc, UINT_MAX, "comp"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"),
TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"),
TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"),
TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"),
TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"),
TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"),
TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"),
TEGRA_IO_PAD(TEGRA_IO_PAD_HV, 6, 0x1c0, 0x1c4, UINT_MAX, "hv"),
TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"),
TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"),
TEGRA_IO_PAD(TEGRA_IO_PAD_NAND, 13, 0x1b8, 0x1bc, UINT_MAX, "nand"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x1c0, 0x1c4, UINT_MAX, "pex-cntrl"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, UINT_MAX, "sdmmc1"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, UINT_MAX, "sdmmc3"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 3, 0x1c0, 0x1c4, UINT_MAX, "sdmmc4"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SYS_DDC, 26, 0x1c0, 0x1c4, UINT_MAX, "sys_ddc"),
TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, UINT_MAX, "uart"),
TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"),
TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"),
TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"),
TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb_bias"),
}; };
static const struct pinctrl_pin_desc tegra124_pin_descs[] = { static const struct pinctrl_pin_desc tegra124_pin_descs[] = {
TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_BB, "bb"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_COMP, "comp"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HV, "hv"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_NAND, "nand"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SYS_DDC, "sys_ddc"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb_bias"),
}; };
static const struct tegra_pmc_soc tegra124_pmc_soc = { static const struct tegra_pmc_soc tegra124_pmc_soc = {
...@@ -3415,53 +3629,86 @@ static const u8 tegra210_cpu_powergates[] = { ...@@ -3415,53 +3629,86 @@ static const u8 tegra210_cpu_powergates[] = {
TEGRA_POWERGATE_CPU3, TEGRA_POWERGATE_CPU3,
}; };
#define TEGRA210_IO_PAD_TABLE(_pad) \
/* .id .dpd .voltage .name */ \
_pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \
_pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \
_pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \
_pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
_pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
_pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \
_pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \
_pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \
_pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \
_pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \
_pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \
_pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \
_pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \
_pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
_pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
_pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
_pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
_pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \
_pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \
_pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \
_pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
_pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
_pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
_pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
_pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
_pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
_pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
_pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \
_pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \
_pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \
_pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \
_pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \
_pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \
_pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
_pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
_pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
_pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \
_pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias")
static const struct tegra_io_pad_soc tegra210_io_pads[] = { static const struct tegra_io_pad_soc tegra210_io_pads[] = {
TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD) TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, 5, "audio"),
TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x1c0, 0x1c4, 18, "audio-hv"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, 10, "cam"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 10, 0x1c0, 0x1c4, UINT_MAX, "csic"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 11, 0x1c0, 0x1c4, UINT_MAX, "csid"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 13, 0x1c0, 0x1c4, UINT_MAX, "csif"),
TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x1b8, 0x1bc, 19, "dbg"),
TEGRA_IO_PAD(TEGRA_IO_PAD_DEBUG_NONAO, 26, 0x1b8, 0x1bc, UINT_MAX, "debug-nonao"),
TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC, 18, 0x1c0, 0x1c4, 20, "dmic"),
TEGRA_IO_PAD(TEGRA_IO_PAD_DP, 19, 0x1c0, 0x1c4, UINT_MAX, "dp"),
TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"),
TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"),
TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"),
TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"),
TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC, 3, 0x1c0, 0x1c4, UINT_MAX, "emmc"),
TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC2, 5, 0x1c0, 0x1c4, UINT_MAX, "emmc2"),
TEGRA_IO_PAD(TEGRA_IO_PAD_GPIO, 27, 0x1b8, 0x1bc, 21, "gpio"),
TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"),
TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"),
TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"),
TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, UINT_MAX, UINT_MAX, 11, "pex-cntrl"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, 12, "sdmmc1"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, 13, "sdmmc3"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 14, 0x1c0, 0x1c4, 22, "spi"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SPI_HV, 15, 0x1c0, 0x1c4, 23, "spi-hv"),
TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, 2, "uart"),
TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"),
TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"),
TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"),
TEGRA_IO_PAD(TEGRA_IO_PAD_USB3, 18, 0x1b8, 0x1bc, UINT_MAX, "usb3"),
TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb-bias"),
}; };
static const struct pinctrl_pin_desc tegra210_pin_descs[] = { static const struct pinctrl_pin_desc tegra210_pin_descs[] = {
TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DEBUG_NONAO, "debug-nonao"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC, "dmic"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DP, "dp"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC, "emmc"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC2, "emmc2"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GPIO, "gpio"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI_HV, "spi-hv"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB3, "usb3"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"),
}; };
static const char * const tegra210_reset_sources[] = { static const char * const tegra210_reset_sources[] = {
...@@ -3511,61 +3758,90 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = { ...@@ -3511,61 +3758,90 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {
.has_usb_sleepwalk = true, .has_usb_sleepwalk = true,
}; };
#define TEGRA186_IO_PAD_TABLE(_pad) \
/* .id .dpd .voltage .name */ \
_pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
_pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
_pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
_pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
_pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
_pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
_pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
_pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
_pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
_pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
_pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
_pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \
_pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
_pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
_pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
_pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
_pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
_pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
_pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
_pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \
_pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
_pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
_pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \
_pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \
_pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \
_pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
_pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
_pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
_pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
_pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
_pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
_pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \
_pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
_pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
_pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
_pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
_pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
_pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
static const struct tegra_io_pad_soc tegra186_io_pads[] = { static const struct tegra_io_pad_soc tegra186_io_pads[] = {
TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD) TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"),
TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x74, 0x78, UINT_MAX, "dsi"),
TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"),
TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x74, 0x78, UINT_MAX, "usb0"),
TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x74, 0x78, UINT_MAX, "usb1"),
TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x74, 0x78, UINT_MAX, "usb2"),
TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x74, 0x78, UINT_MAX, "usb-bias"),
TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"),
TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"),
TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x74, 0x78, UINT_MAX, "hsic"),
TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"),
TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"),
TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC2_HV, 2, 0x7c, 0x80, 5, "sdmmc2-hv"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"),
TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 8, 0x7c, 0x80, UINT_MAX, "dsib"),
TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 9, 0x7c, 0x80, UINT_MAX, "dsic"),
TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 10, 0x7c, 0x80, UINT_MAX, "dsid"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"),
TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"),
TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC_HV, 20, 0x7c, 0x80, 2, "dmic-hv"),
TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"),
TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"),
TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
}; };
static const struct pinctrl_pin_desc tegra186_pin_descs[] = { static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC2_HV, "sdmmc2-hv"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC_HV, "dmic-hv"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
}; };
static const struct tegra_pmc_regs tegra186_pmc_regs = { static const struct tegra_pmc_regs tegra186_pmc_regs = {
.scratch0 = 0x2000, .scratch0 = 0x2000,
.dpd_req = 0x74,
.dpd_status = 0x78,
.dpd2_req = 0x7c,
.dpd2_status = 0x80,
.rst_status = 0x70, .rst_status = 0x70,
.rst_source_shift = 0x2, .rst_source_shift = 0x2,
.rst_source_mask = 0x3c, .rst_source_mask = 0x3c,
...@@ -3573,6 +3849,14 @@ static const struct tegra_pmc_regs tegra186_pmc_regs = { ...@@ -3573,6 +3849,14 @@ static const struct tegra_pmc_regs tegra186_pmc_regs = {
.rst_level_mask = 0x3, .rst_level_mask = 0x3,
}; };
static void tegra186_pmc_init(struct tegra_pmc *pmc)
{
pmc->syscore.suspend = tegra186_pmc_wake_syscore_suspend;
pmc->syscore.resume = tegra186_pmc_wake_syscore_resume;
register_syscore_ops(&pmc->syscore);
}
static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
struct device_node *np, struct device_node *np,
bool invert) bool invert)
...@@ -3652,7 +3936,7 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = { ...@@ -3652,7 +3936,7 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = {
.num_pin_descs = ARRAY_SIZE(tegra186_pin_descs), .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
.pin_descs = tegra186_pin_descs, .pin_descs = tegra186_pin_descs,
.regs = &tegra186_pmc_regs, .regs = &tegra186_pmc_regs,
.init = NULL, .init = tegra186_pmc_init,
.setup_irq_polarity = tegra186_pmc_setup_irq_polarity, .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
.irq_set_wake = tegra186_pmc_irq_set_wake, .irq_set_wake = tegra186_pmc_irq_set_wake,
.irq_set_type = tegra186_pmc_irq_set_type, .irq_set_type = tegra186_pmc_irq_set_type,
...@@ -3662,78 +3946,120 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = { ...@@ -3662,78 +3946,120 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = {
.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
.num_wake_events = ARRAY_SIZE(tegra186_wake_events), .num_wake_events = ARRAY_SIZE(tegra186_wake_events),
.wake_events = tegra186_wake_events, .wake_events = tegra186_wake_events,
.max_wake_events = 96,
.max_wake_vectors = 3,
.pmc_clks_data = NULL, .pmc_clks_data = NULL,
.num_pmc_clks = 0, .num_pmc_clks = 0,
.has_blink_output = false, .has_blink_output = false,
.has_usb_sleepwalk = false, .has_usb_sleepwalk = false,
}; };
#define TEGRA194_IO_PAD_TABLE(_pad) \
/* .id .dpd .voltage .name */ \
_pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
_pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
_pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
_pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
_pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
_pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
_pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
_pad(TEGRA_IO_PAD_EQOS, 8, UINT_MAX, "eqos"), \
_pad(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, UINT_MAX, "pex-clk-2-bias"), \
_pad(TEGRA_IO_PAD_PEX_CLK_2, 10, UINT_MAX, "pex-clk-2"), \
_pad(TEGRA_IO_PAD_DAP3, 11, UINT_MAX, "dap3"), \
_pad(TEGRA_IO_PAD_DAP5, 12, UINT_MAX, "dap5"), \
_pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
_pad(TEGRA_IO_PAD_PWR_CTL, 15, UINT_MAX, "pwr-ctl"), \
_pad(TEGRA_IO_PAD_SOC_GPIO53, 16, UINT_MAX, "soc-gpio53"), \
_pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
_pad(TEGRA_IO_PAD_GP_PWM2, 18, UINT_MAX, "gp-pwm2"), \
_pad(TEGRA_IO_PAD_GP_PWM3, 19, UINT_MAX, "gp-pwm3"), \
_pad(TEGRA_IO_PAD_SOC_GPIO12, 20, UINT_MAX, "soc-gpio12"), \
_pad(TEGRA_IO_PAD_SOC_GPIO13, 21, UINT_MAX, "soc-gpio13"), \
_pad(TEGRA_IO_PAD_SOC_GPIO10, 22, UINT_MAX, "soc-gpio10"), \
_pad(TEGRA_IO_PAD_UART4, 23, UINT_MAX, "uart4"), \
_pad(TEGRA_IO_PAD_UART5, 24, UINT_MAX, "uart5"), \
_pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
_pad(TEGRA_IO_PAD_HDMI_DP3, 26, UINT_MAX, "hdmi-dp3"), \
_pad(TEGRA_IO_PAD_HDMI_DP2, 27, UINT_MAX, "hdmi-dp2"), \
_pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
_pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
_pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
_pad(TEGRA_IO_PAD_PEX_CTL2, 33, UINT_MAX, "pex-ctl2"), \
_pad(TEGRA_IO_PAD_PEX_L0_RST_N, 34, UINT_MAX, "pex-l0-rst"), \
_pad(TEGRA_IO_PAD_PEX_L1_RST_N, 35, UINT_MAX, "pex-l1-rst"), \
_pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
_pad(TEGRA_IO_PAD_PEX_L5_RST_N, 37, UINT_MAX, "pex-l5-rst"), \
_pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
_pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
_pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
_pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
_pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
_pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
_pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
_pad(TEGRA_IO_PAD_CSIG, 50, UINT_MAX, "csig"), \
_pad(TEGRA_IO_PAD_CSIH, 51, UINT_MAX, "csih"), \
_pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
_pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
_pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
_pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
_pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
_pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
static const struct tegra_io_pad_soc tegra194_io_pads[] = { static const struct tegra_io_pad_soc tegra194_io_pads[] = {
TEGRA194_IO_PAD_TABLE(TEGRA_IO_PAD) TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"),
TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"),
TEGRA_IO_PAD(TEGRA_IO_PAD_EQOS, 8, 0x74, 0x78, UINT_MAX, "eqos"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, 0x74, 0x78, UINT_MAX, "pex-clk-2-bias"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2, 10, 0x74, 0x78, UINT_MAX, "pex-clk-2"),
TEGRA_IO_PAD(TEGRA_IO_PAD_DAP3, 11, 0x74, 0x78, UINT_MAX, "dap3"),
TEGRA_IO_PAD(TEGRA_IO_PAD_DAP5, 12, 0x74, 0x78, UINT_MAX, "dap5"),
TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PWR_CTL, 15, 0x74, 0x78, UINT_MAX, "pwr-ctl"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO53, 16, 0x74, 0x78, UINT_MAX, "soc-gpio53"),
TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"),
TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM2, 18, 0x74, 0x78, UINT_MAX, "gp-pwm2"),
TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM3, 19, 0x74, 0x78, UINT_MAX, "gp-pwm3"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO12, 20, 0x74, 0x78, UINT_MAX, "soc-gpio12"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO13, 21, 0x74, 0x78, UINT_MAX, "soc-gpio13"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO10, 22, 0x74, 0x78, UINT_MAX, "soc-gpio10"),
TEGRA_IO_PAD(TEGRA_IO_PAD_UART4, 23, 0x74, 0x78, UINT_MAX, "uart4"),
TEGRA_IO_PAD(TEGRA_IO_PAD_UART5, 24, 0x74, 0x78, UINT_MAX, "uart5"),
TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"),
TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP3, 26, 0x74, 0x78, UINT_MAX, "hdmi-dp3"),
TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP2, 27, 0x74, 0x78, UINT_MAX, "hdmi-dp2"),
TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"),
TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CTL2, 1, 0x7c, 0x80, UINT_MAX, "pex-ctl2"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L0_RST, 2, 0x7c, 0x80, UINT_MAX, "pex-l0-rst"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L1_RST, 3, 0x7c, 0x80, UINT_MAX, "pex-l1-rst"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"),
TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L5_RST, 5, 0x7c, 0x80, UINT_MAX, "pex-l5-rst"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"),
TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 18, 0x7c, 0x80, UINT_MAX, "csig"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 19, 0x7c, 0x80, UINT_MAX, "csih"),
TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"),
TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"),
TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
}; };
static const struct pinctrl_pin_desc tegra194_pin_descs[] = { static const struct pinctrl_pin_desc tegra194_pin_descs[] = {
TEGRA194_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EQOS, "eqos"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2_BIAS, "pex-clk-2-bias"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2, "pex-clk-2"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP3, "dap3"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP5, "dap5"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PWR_CTL, "pwr-ctl"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO53, "soc-gpio53"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM2, "gp-pwm2"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM3, "gp-pwm3"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO12, "soc-gpio12"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO13, "soc-gpio13"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO10, "soc-gpio10"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART4, "uart4"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART5, "uart5"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP3, "hdmi-dp3"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP2, "hdmi-dp2"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CTL2, "pex-ctl2"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L0_RST, "pex-l0-rst"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L1_RST, "pex-l1-rst"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L5_RST, "pex-l5-rst"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
}; };
static const struct tegra_pmc_regs tegra194_pmc_regs = { static const struct tegra_pmc_regs tegra194_pmc_regs = {
.scratch0 = 0x2000, .scratch0 = 0x2000,
.dpd_req = 0x74,
.dpd_status = 0x78,
.dpd2_req = 0x7c,
.dpd2_status = 0x80,
.rst_status = 0x70, .rst_status = 0x70,
.rst_source_shift = 0x2, .rst_source_shift = 0x2,
.rst_source_mask = 0x7c, .rst_source_mask = 0x7c,
...@@ -3794,7 +4120,7 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = { ...@@ -3794,7 +4120,7 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = {
.num_pin_descs = ARRAY_SIZE(tegra194_pin_descs), .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs),
.pin_descs = tegra194_pin_descs, .pin_descs = tegra194_pin_descs,
.regs = &tegra194_pmc_regs, .regs = &tegra194_pmc_regs,
.init = NULL, .init = tegra186_pmc_init,
.setup_irq_polarity = tegra186_pmc_setup_irq_polarity, .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
.irq_set_wake = tegra186_pmc_irq_set_wake, .irq_set_wake = tegra186_pmc_irq_set_wake,
.irq_set_type = tegra186_pmc_irq_set_type, .irq_set_type = tegra186_pmc_irq_set_type,
...@@ -3804,18 +4130,52 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = { ...@@ -3804,18 +4130,52 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = {
.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
.num_wake_events = ARRAY_SIZE(tegra194_wake_events), .num_wake_events = ARRAY_SIZE(tegra194_wake_events),
.wake_events = tegra194_wake_events, .wake_events = tegra194_wake_events,
.max_wake_events = 96,
.max_wake_vectors = 3,
.pmc_clks_data = NULL, .pmc_clks_data = NULL,
.num_pmc_clks = 0, .num_pmc_clks = 0,
.has_blink_output = false, .has_blink_output = false,
.has_usb_sleepwalk = false, .has_usb_sleepwalk = false,
}; };
static const struct tegra_io_pad_soc tegra234_io_pads[] = {
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0xe0c0, 0xe0c4, UINT_MAX, "csia"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0xe0c0, 0xe0c4, UINT_MAX, "csib"),
TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0xe0d0, 0xe0d4, UINT_MAX, "hdmi-dp0"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 2, 0xe0c0, 0xe0c4, UINT_MAX, "csic"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 3, 0xe0c0, 0xe0c4, UINT_MAX, "csid"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 4, 0xe0c0, 0xe0c4, UINT_MAX, "csie"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 5, 0xe0c0, 0xe0c4, UINT_MAX, "csif"),
TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 0, 0xe064, 0xe068, UINT_MAX, "ufs"),
TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 1, 0xe05c, 0xe060, UINT_MAX, "edp"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 0, 0xe054, 0xe058, 4, "sdmmc1-hv"),
TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, UINT_MAX, UINT_MAX, UINT_MAX, 6, "sdmmc3-hv"),
TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 1, "audio-hv"),
TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 6, 0xe0c0, 0xe0c4, UINT_MAX, "csig"),
TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 7, 0xe0c0, 0xe0c4, UINT_MAX, "csih"),
};
static const struct pinctrl_pin_desc tegra234_pin_descs[] = {
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"),
TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"),
};
static const struct tegra_pmc_regs tegra234_pmc_regs = { static const struct tegra_pmc_regs tegra234_pmc_regs = {
.scratch0 = 0x2000, .scratch0 = 0x2000,
.dpd_req = 0,
.dpd_status = 0,
.dpd2_req = 0,
.dpd2_status = 0,
.rst_status = 0x70, .rst_status = 0x70,
.rst_source_shift = 0x2, .rst_source_shift = 0x2,
.rst_source_mask = 0xfc, .rst_source_mask = 0xfc,
...@@ -3880,12 +4240,12 @@ static const struct tegra_pmc_soc tegra234_pmc_soc = { ...@@ -3880,12 +4240,12 @@ static const struct tegra_pmc_soc tegra234_pmc_soc = {
.needs_mbist_war = false, .needs_mbist_war = false,
.has_impl_33v_pwr = true, .has_impl_33v_pwr = true,
.maybe_tz_only = false, .maybe_tz_only = false,
.num_io_pads = 0, .num_io_pads = ARRAY_SIZE(tegra234_io_pads),
.io_pads = NULL, .io_pads = tegra234_io_pads,
.num_pin_descs = 0, .num_pin_descs = ARRAY_SIZE(tegra234_pin_descs),
.pin_descs = NULL, .pin_descs = tegra234_pin_descs,
.regs = &tegra234_pmc_regs, .regs = &tegra234_pmc_regs,
.init = NULL, .init = tegra186_pmc_init,
.setup_irq_polarity = tegra186_pmc_setup_irq_polarity, .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
.irq_set_wake = tegra186_pmc_irq_set_wake, .irq_set_wake = tegra186_pmc_irq_set_wake,
.irq_set_type = tegra186_pmc_irq_set_type, .irq_set_type = tegra186_pmc_irq_set_type,
...@@ -3895,6 +4255,8 @@ static const struct tegra_pmc_soc tegra234_pmc_soc = { ...@@ -3895,6 +4255,8 @@ static const struct tegra_pmc_soc tegra234_pmc_soc = {
.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
.num_wake_events = ARRAY_SIZE(tegra234_wake_events), .num_wake_events = ARRAY_SIZE(tegra234_wake_events),
.wake_events = tegra234_wake_events, .wake_events = tegra234_wake_events,
.max_wake_events = 96,
.max_wake_vectors = 3,
.pmc_clks_data = NULL, .pmc_clks_data = NULL,
.num_pmc_clks = 0, .num_pmc_clks = 0,
.has_blink_output = false, .has_blink_output = false,
......
include/soc/tegra/fuse.h
View file @ 2a26daee
...@@ -34,6 +34,20 @@ enum tegra_revision { ...@@ -34,6 +34,20 @@ enum tegra_revision {
TEGRA_REVISION_MAX, TEGRA_REVISION_MAX,
}; };
enum tegra_platform {
TEGRA_PLATFORM_SILICON = 0,
TEGRA_PLATFORM_QT,
TEGRA_PLATFORM_SYSTEM_FPGA,
TEGRA_PLATFORM_UNIT_FPGA,
TEGRA_PLATFORM_ASIM_QT,
TEGRA_PLATFORM_ASIM_LINSIM,
TEGRA_PLATFORM_DSIM_ASIM_LINSIM,
TEGRA_PLATFORM_VERIFICATION_SIMULATION,
TEGRA_PLATFORM_VDK,
TEGRA_PLATFORM_VSP,
TEGRA_PLATFORM_MAX,
};
struct tegra_sku_info { struct tegra_sku_info {
int sku_id; int sku_id;
int cpu_process_id; int cpu_process_id;
...@@ -47,6 +61,7 @@ struct tegra_sku_info { ...@@ -47,6 +61,7 @@ struct tegra_sku_info {
int gpu_speedo_id; int gpu_speedo_id;
int gpu_speedo_value; int gpu_speedo_value;
enum tegra_revision revision; enum tegra_revision revision;
enum tegra_platform platform;
}; };
#ifdef CONFIG_ARCH_TEGRA #ifdef CONFIG_ARCH_TEGRA
......
include/soc/tegra/ivc.h
View file @ 2a26daee
...@@ -4,6 +4,7 @@ ...@@ -4,6 +4,7 @@
*/ */
#ifndef __TEGRA_IVC_H #ifndef __TEGRA_IVC_H
#define __TEGRA_IVC_H
#include <linux/device.h> #include <linux/device.h>
#include <linux/dma-mapping.h> #include <linux/dma-mapping.h>
......
include/soc/tegra/pmc.h
View file @ 2a26daee
...@@ -118,9 +118,9 @@ enum tegra_io_pad { ...@@ -118,9 +118,9 @@ enum tegra_io_pad {
TEGRA_IO_PAD_PEX_CLK_2, TEGRA_IO_PAD_PEX_CLK_2,
TEGRA_IO_PAD_PEX_CNTRL, TEGRA_IO_PAD_PEX_CNTRL,
TEGRA_IO_PAD_PEX_CTL2, TEGRA_IO_PAD_PEX_CTL2,
TEGRA_IO_PAD_PEX_L0_RST_N, TEGRA_IO_PAD_PEX_L0_RST,
TEGRA_IO_PAD_PEX_L1_RST_N, TEGRA_IO_PAD_PEX_L1_RST,
TEGRA_IO_PAD_PEX_L5_RST_N, TEGRA_IO_PAD_PEX_L5_RST,
TEGRA_IO_PAD_PWR_CTL, TEGRA_IO_PAD_PWR_CTL,
TEGRA_IO_PAD_SDMMC1, TEGRA_IO_PAD_SDMMC1,
TEGRA_IO_PAD_SDMMC1_HV, TEGRA_IO_PAD_SDMMC1_HV,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7