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Commit 30d38542 authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm 

* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (85 commits)
  [ARM] pxa: add base support for PXA930 Handheld Platform (aka SAAR)
  [ARM] pxa: add base support for PXA930 Evaluation Board (aka TavorEVB)
  [ARM] pxa: add base support for PXA930 (aka Tavor-P)
  [ARM] Update mach-types
  [ARM] pxa: make littleton to use the new smc91x platform data
  [ARM] pxa: make zylonite to use the new smc91x platform data
  [ARM] pxa: make mainstone to use the new smc91x platform data
  [ARM] pxa: make lubbock to use new smc91x platform data
  [NET] smc91x: prepare SMC_USE_PXA_DMA to be specified in platform data
  [NET] smc91x: prepare for SMC_IO_SHIFT to be a platform configurable variable
  [NET] smc91x: add SMC91X_NOWAIT flag to platform data
  [NET] smc91x: favor the use of SMC91X_USE_* instead of SMC_CAN_USE_*
  [NET] smc91x: remove "irq_flags" from "struct smc91x_platdata"
  [ARM] 5146/1: pxa2xx: convert all boards to call pxa2xx_transceiver_mode helper
  Support for LCD on e740 e750 e400 and e800 e-series PDAs
  E-series UDC support
  PXA UDC - allow use of inverted GPIO for pullup
  Add e350 support
  Fix broken e-series build
  E-series GPIO / IRQ definitions.
  ...
parents 20b7997e 044e5f45
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MAINTAINERS
View file @ 30d38542
......@@ -480,11 +480,28 @@ M: kernel@wantstofly.org
L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
S: Maintained
ARM/COMPULAB CM-X270/EM-X270 MACHINE SUPPORT
P: Mike Rapoport
M: mike@compulab.co.il
L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
S: Maintained
ARM/CORGI MACHINE SUPPORT
P: Richard Purdie
M: rpurdie@rpsys.net
S: Maintained
ARM/EZX SMARTPHONES (A780, A910, A1200, E680, ROKR E2 and ROKR E6)
P: Daniel Ribeiro
M: drwyrm@gmail.com
P: Stefan Schmidt
M: stefan@openezx.org
P: Harald Welte
M: laforge@openezx.org
L: openezx-devel@lists.openezx.org (subscribers-only)
W: http://www.openezx.org/
S: Maintained
ARM/GLOMATION GESBC9312SX MACHINE SUPPORT
P: Lennert Buytenhek
M: kernel@wantstofly.org
......@@ -572,10 +589,18 @@ L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
S: Maintained
ARM/TOSA MACHINE SUPPORT
P: Dmitry Baryshkov
M: dbaryshkov@gmail.com
P: Dirk Opfer
M: dirk@opfer-online.de
S: Maintained
ARM/PALMTX SUPPORT
P: Marek Vasut
M: marek.vasut@gmail.com
W: http://hackndev.com
S: Maintained
ARM/PLEB SUPPORT
P: Peter Chubb
M: pleb@gelato.unsw.edu.au
......
arch/arm/common/sa1111.c
View file @ 30d38542
......@@ -627,7 +627,7 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq)
if (!sachip)
return -ENOMEM;
sachip->clk = clk_get(me, "GPIO27_CLK");
sachip->clk = clk_get(me, "SA1111_CLK");
if (!sachip->clk) {
ret = PTR_ERR(sachip->clk);
goto err_free;
......
arch/arm/configs/ezx_defconfig 0 → 100644
View file @ 30d38542
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.26-rc3
# Mon Jul 7 17:52:21 2008
#
CONFIG_ARM=y
CONFIG_HAVE_PWM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_MMU=y
# CONFIG_NO_IOPORT is not set
CONFIG_GENERIC_HARDIRQS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_SUPPORTS_AOUT=y
CONFIG_ZONE_DMA=y
CONFIG_ARCH_MTD_XIP=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_LOCK_KERNEL=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION="-ezxdev"
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_AUDIT is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CGROUPS is not set
CONFIG_GROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
# CONFIG_RT_GROUP_SCHED is not set
CONFIG_USER_SCHED=y
# CONFIG_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
# CONFIG_BLK_DEV_INITRD is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
# CONFIG_COMPAT_BRK is not set
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
# CONFIG_HAVE_DMA_ATTRS is not set
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_AS is not set
CONFIG_IOSCHED_DEADLINE=y
# CONFIG_IOSCHED_CFQ is not set
# CONFIG_DEFAULT_AS is not set
CONFIG_DEFAULT_DEADLINE=y
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="deadline"
CONFIG_CLASSIC_RCU=y
#
# System Type
#
# CONFIG_ARCH_AAEC2000 is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IXP23XX is not set
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_ORION5X is not set
# CONFIG_ARCH_PNX4008 is not set
CONFIG_ARCH_PXA=y
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
# CONFIG_ARCH_MSM7X00A is not set
#
# Intel PXA2xx/PXA3xx Implementations
#
# CONFIG_ARCH_GUMSTIX is not set
# CONFIG_ARCH_LUBBOCK is not set
# CONFIG_MACH_LOGICPD_PXA270 is not set
# CONFIG_MACH_MAINSTONE is not set
# CONFIG_ARCH_PXA_IDP is not set
# CONFIG_PXA_SHARPSL is not set
# CONFIG_ARCH_PXA_ESERIES is not set
# CONFIG_MACH_TRIZEPS4 is not set
# CONFIG_MACH_EM_X270 is not set
# CONFIG_MACH_COLIBRI is not set
# CONFIG_MACH_ZYLONITE is not set
# CONFIG_MACH_LITTLETON is not set
# CONFIG_MACH_ARMCORE is not set
# CONFIG_MACH_MAGICIAN is not set
# CONFIG_MACH_PCM027 is not set
CONFIG_PXA_EZX=y
CONFIG_MACH_EZX_A780=y
CONFIG_MACH_EZX_E680=y
CONFIG_MACH_EZX_A1200=y
CONFIG_MACH_EZX_A910=y
CONFIG_MACH_EZX_E6=y
CONFIG_MACH_EZX_E2=y
CONFIG_PXA27x=y
CONFIG_PXA_SSP=y
CONFIG_PXA_PWM=y
#
# Boot options
#
#
# Power management
#
#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_XSCALE=y
CONFIG_CPU_32v5=y
CONFIG_CPU_ABRT_EV5T=y
CONFIG_CPU_PABRT_NOIFAR=y
CONFIG_CPU_CACHE_VIVT=y
CONFIG_CPU_TLB_V4WBI=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
#
# Processor Features
#
CONFIG_ARM_THUMB=y
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_OUTER_CACHE is not set
CONFIG_IWMMXT=y
CONFIG_XSCALE_PMU=y
#
# Bus support
#
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set
#
# Kernel Features
#
CONFIG_TICK_ONESHOT=y
# CONFIG_NO_HZ is not set
CONFIG_HIGH_RES_TIMERS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_PREEMPT=y
CONFIG_HZ=100
CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y
# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4096
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
CONFIG_ALIGNMENT_TRAP=y
#
# Boot options
#
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=tty1 root=/dev/mmcblk0p2 rootfstype=ext2 rootdelay=1 ip=192.168.0.202:192.168.0.200:192.168.0.200:255.255.255.0 debug"
# CONFIG_XIP_KERNEL is not set
CONFIG_KEXEC=y
CONFIG_ATAGS_PROC=y
#
# CPU Frequency scaling
#
# CONFIG_CPU_FREQ is not set
#
# Floating point emulation
#
#
# At least one emulation must be selected
#
CONFIG_FPE_NWFPE=y
# CONFIG_FPE_NWFPE_XP is not set
# CONFIG_FPE_FASTFPE is not set
#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
CONFIG_BINFMT_AOUT=m
CONFIG_BINFMT_MISC=m
#
# Power management options
#
CONFIG_PM=y
# CONFIG_PM_DEBUG is not set
CONFIG_PM_SLEEP=y
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
CONFIG_APM_EMULATION=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
#
# Networking
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_MMAP=y
CONFIG_UNIX=y
CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_XFRM_STATISTICS is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
CONFIG_INET_TUNNEL=m
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IP_VS is not set
CONFIG_IPV6=m
# CONFIG_IPV6_PRIVACY is not set
# CONFIG_IPV6_ROUTER_PREF is not set
# CONFIG_IPV6_OPTIMISTIC_DAD is not set
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
CONFIG_INET6_IPCOMP=m
CONFIG_IPV6_MIP6=m
CONFIG_INET6_XFRM_TUNNEL=m
CONFIG_INET6_TUNNEL=m
CONFIG_INET6_XFRM_MODE_TRANSPORT=m
CONFIG_INET6_XFRM_MODE_TUNNEL=m
CONFIG_INET6_XFRM_MODE_BEET=m
# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
CONFIG_IPV6_SIT=m
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=m
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
# CONFIG_IPV6_MROUTE is not set
# CONFIG_NETWORK_SECMARK is not set
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_DEBUG is not set
CONFIG_NETFILTER_ADVANCED=y
CONFIG_BRIDGE_NETFILTER=y
#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_NETLINK=m
CONFIG_NETFILTER_NETLINK_QUEUE=m
CONFIG_NETFILTER_NETLINK_LOG=m
CONFIG_NF_CONNTRACK=m
CONFIG_NF_CT_ACCT=y
CONFIG_NF_CONNTRACK_MARK=y
CONFIG_NF_CONNTRACK_EVENTS=y
# CONFIG_NF_CT_PROTO_DCCP is not set
CONFIG_NF_CT_PROTO_GRE=m
CONFIG_NF_CT_PROTO_SCTP=m
CONFIG_NF_CT_PROTO_UDPLITE=m
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_NETBIOS_NS=m
CONFIG_NF_CONNTRACK_PPTP=m
CONFIG_NF_CONNTRACK_SANE=m
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CONNTRACK_TFTP=m
CONFIG_NF_CT_NETLINK=m
CONFIG_NETFILTER_XTABLES=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
CONFIG_NETFILTER_XT_TARGET_MARK=m
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_DCCP=m
CONFIG_NETFILTER_XT_MATCH_DSCP=m
CONFIG_NETFILTER_XT_MATCH_ESP=m
CONFIG_NETFILTER_XT_MATCH_HELPER=m
# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
CONFIG_NETFILTER_XT_MATCH_MAC=m
CONFIG_NETFILTER_XT_MATCH_MARK=m
# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
CONFIG_NETFILTER_XT_MATCH_POLICY=m
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
CONFIG_NETFILTER_XT_MATCH_QUOTA=m
# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
CONFIG_NETFILTER_XT_MATCH_REALM=m
CONFIG_NETFILTER_XT_MATCH_SCTP=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
CONFIG_NETFILTER_XT_MATCH_STRING=m
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
CONFIG_NETFILTER_XT_MATCH_TIME=m
CONFIG_NETFILTER_XT_MATCH_U32=m
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
#
# IP: Netfilter Configuration
#
CONFIG_NF_CONNTRACK_IPV4=m
CONFIG_NF_CONNTRACK_PROC_COMPAT=y
CONFIG_IP_NF_QUEUE=m
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_RECENT=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_AH=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_MATCH_ADDRTYPE=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_LOG=m
CONFIG_IP_NF_TARGET_ULOG=m
CONFIG_NF_NAT=m
CONFIG_NF_NAT_NEEDED=y
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_REDIRECT=m
CONFIG_IP_NF_TARGET_NETMAP=m
CONFIG_NF_NAT_SNMP_BASIC=m
CONFIG_NF_NAT_PROTO_GRE=m
CONFIG_NF_NAT_PROTO_UDPLITE=m
CONFIG_NF_NAT_PROTO_SCTP=m
CONFIG_NF_NAT_FTP=m
CONFIG_NF_NAT_IRC=m
CONFIG_NF_NAT_TFTP=m
CONFIG_NF_NAT_AMANDA=m
CONFIG_NF_NAT_PPTP=m
CONFIG_NF_NAT_H323=m
CONFIG_NF_NAT_SIP=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_TARGET_CLUSTERIP=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
#
# IPv6: Netfilter Configuration
#
CONFIG_NF_CONNTRACK_IPV6=m
CONFIG_IP6_NF_QUEUE=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_MATCH_OPTS=m
CONFIG_IP6_NF_MATCH_FRAG=m
CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_AH=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_EUI64=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_LOG=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_RAW=m
#
# Bridge: Netfilter Configuration
#
# CONFIG_BRIDGE_NF_EBTABLES is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
CONFIG_BRIDGE=m
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
CONFIG_LLC=m
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_NET_SCHED is not set
CONFIG_NET_CLS_ROUTE=y
CONFIG_NET_SCH_FIFO=y
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_IRDA is not set
CONFIG_BT=y
CONFIG_BT_L2CAP=m
CONFIG_BT_SCO=y
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=m
#
# Bluetooth device drivers
#
# CONFIG_BT_HCIUSB is not set
# CONFIG_BT_HCIBTUSB is not set
# CONFIG_BT_HCIBTSDIO is not set
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
# CONFIG_BT_HCIUART_BCSP is not set
# CONFIG_BT_HCIUART_LL is not set
# CONFIG_BT_HCIBCM203X is not set
# CONFIG_BT_HCIBPA10X is not set
# CONFIG_BT_HCIBFUSB is not set
# CONFIG_BT_HCIVHCI is not set
# CONFIG_AF_RXRPC is not set
CONFIG_FIB_RULES=y
#
# Wireless
#
CONFIG_CFG80211=m
CONFIG_NL80211=y
CONFIG_WIRELESS_EXT=y
CONFIG_MAC80211=m
#
# Rate control algorithm selection
#
CONFIG_MAC80211_RC_DEFAULT_PID=y
# CONFIG_MAC80211_RC_DEFAULT_NONE is not set
#
# Selecting 'y' for an algorithm will
#
#
# build the algorithm into mac80211.
#
CONFIG_MAC80211_RC_DEFAULT="pid"
CONFIG_MAC80211_RC_PID=y
# CONFIG_MAC80211_MESH is not set
CONFIG_MAC80211_LEDS=y
# CONFIG_MAC80211_DEBUG_PACKET_ALIGNMENT is not set
# CONFIG_MAC80211_DEBUG is not set
CONFIG_IEEE80211=m
# CONFIG_IEEE80211_DEBUG is not set
CONFIG_IEEE80211_CRYPT_WEP=m
CONFIG_IEEE80211_CRYPT_CCMP=m
CONFIG_IEEE80211_CRYPT_TKIP=m
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=m
# CONFIG_SYS_HYPERVISOR is not set
CONFIG_CONNECTOR=m
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
# CONFIG_MTD_AFS_PARTS is not set
# CONFIG_MTD_AR7_PARTS is not set
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
# CONFIG_MTD_BLKDEVS is not set
# CONFIG_MTD_BLOCK is not set
# CONFIG_MTD_BLOCK_RO is not set
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_NOSWAP=y
# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
CONFIG_MTD_CFI_GEOMETRY=y
# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
CONFIG_MTD_MAP_BANK_WIDTH_2=y
# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
# CONFIG_MTD_CFI_I2 is not set
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_OTP is not set
CONFIG_MTD_CFI_INTELEXT=y
# CONFIG_MTD_CFI_AMDSTD is not set
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
CONFIG_MTD_XIP=y
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_START=0x0
CONFIG_MTD_PHYSMAP_LEN=0x0
CONFIG_MTD_PHYSMAP_BANKWIDTH=2
# CONFIG_MTD_PXA2XX is not set
# CONFIG_MTD_ARM_INTEGRATOR is not set
# CONFIG_MTD_SHARP_SL is not set
# CONFIG_MTD_PLATRAM is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_DATAFLASH is not set
# CONFIG_MTD_M25P80 is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
# CONFIG_MTD_NAND is not set
# CONFIG_MTD_ONENAND is not set
#
# UBI - Unsorted block images
#
# CONFIG_MTD_UBI is not set
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_CRYPTOLOOP=m
CONFIG_BLK_DEV_NBD=m
# CONFIG_BLK_DEV_UB is not set
CONFIG_BLK_DEV_RAM=m
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_BLK_DEV_XIP is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_MISC_DEVICES=y
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
CONFIG_NETDEVICES=y
# CONFIG_NETDEVICES_MULTIQUEUE is not set
CONFIG_DUMMY=y
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set
# CONFIG_NET_ETHERNET is not set
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
#
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
# CONFIG_IWLWIFI_LEDS is not set
#
# USB Network Adapters
#
# CONFIG_USB_CATC is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_USBNET is not set
# CONFIG_WAN is not set
CONFIG_PPP=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPP_FILTER=y
CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_BSDCOMP=m
# CONFIG_PPP_MPPE is not set
# CONFIG_PPPOE is not set
# CONFIG_PPPOL2TP is not set
# CONFIG_SLIP is not set
CONFIG_SLHC=m
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_ISDN is not set
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set
# CONFIG_INPUT_APMPOWER is not set
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
CONFIG_KEYBOARD_PXA27x=y
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_ADS7846 is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
# CONFIG_TOUCHSCREEN_MK712 is not set
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_UCB1400 is not set
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
CONFIG_TOUCHSCREEN_PCAP=y
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_ATI_REMOTE is not set
# CONFIG_INPUT_ATI_REMOTE2 is not set
# CONFIG_INPUT_KEYSPAN_REMOTE is not set
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
CONFIG_INPUT_UINPUT=y
#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
CONFIG_DEVKMEM=y
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_PXA=y
CONFIG_SERIAL_PXA_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=8
# CONFIG_IPMI_HANDLER is not set
CONFIG_HW_RANDOM=y
# CONFIG_NVRAM is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
#
# I2C Hardware Bus support
#
# CONFIG_I2C_GPIO is not set
CONFIG_I2C_PXA=y
# CONFIG_I2C_PXA_SLAVE is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_TINY_USB is not set
# CONFIG_I2C_PCA_PLATFORM is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_DS1682 is not set
# CONFIG_SENSORS_EEPROM is not set
# CONFIG_SENSORS_PCF8574 is not set
# CONFIG_PCF8575 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_TPS65010 is not set
# CONFIG_SENSORS_MAX6875 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
CONFIG_SPI=y
CONFIG_SPI_MASTER=y
#
# SPI Master Controller Drivers
#
# CONFIG_SPI_BITBANG is not set
CONFIG_SPI_PXA2XX=m
#
# SPI Protocol Masters
#
# CONFIG_SPI_AT25 is not set
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set
CONFIG_HAVE_GPIO_LIB=y
#
# GPIO Support
#
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
#
# SPI GPIO expanders:
#
# CONFIG_GPIO_MCP23S08 is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
# CONFIG_WATCHDOG is not set
#
# Sonics Silicon Backplane
#
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_ASIC3 is not set
# CONFIG_HTC_EGPIO is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_MFD_TC6393XB is not set
CONFIG_EZX_PCAP=y
#
# Multimedia devices
#
#
# Multimedia core support
#
CONFIG_VIDEO_DEV=m
CONFIG_VIDEO_V4L2_COMMON=m
CONFIG_VIDEO_ALLOW_V4L1=y
CONFIG_VIDEO_V4L1_COMPAT=y
# CONFIG_DVB_CORE is not set
CONFIG_VIDEO_MEDIA=m
#
# Multimedia drivers
#
# CONFIG_MEDIA_ATTACH is not set
CONFIG_MEDIA_TUNER=m
# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
CONFIG_MEDIA_TUNER_SIMPLE=m
CONFIG_MEDIA_TUNER_TDA8290=m
CONFIG_MEDIA_TUNER_TDA9887=m
CONFIG_MEDIA_TUNER_TEA5761=m
CONFIG_MEDIA_TUNER_TEA5767=m
CONFIG_MEDIA_TUNER_MT20XX=m
CONFIG_MEDIA_TUNER_XC2028=m
CONFIG_MEDIA_TUNER_XC5000=m
CONFIG_VIDEO_V4L2=m
CONFIG_VIDEO_V4L1=m
CONFIG_VIDEO_CAPTURE_DRIVERS=y
# CONFIG_VIDEO_ADV_DEBUG is not set
CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
# CONFIG_VIDEO_VIVI is not set
# CONFIG_VIDEO_CPIA is not set
# CONFIG_VIDEO_CPIA2 is not set
# CONFIG_VIDEO_SAA5246A is not set
# CONFIG_VIDEO_SAA5249 is not set
# CONFIG_TUNER_3036 is not set
# CONFIG_V4L_USB_DRIVERS is not set
# CONFIG_SOC_CAMERA is not set
# CONFIG_VIDEO_PXA27x is not set
CONFIG_RADIO_ADAPTERS=y
# CONFIG_USB_DSBR is not set
# CONFIG_USB_SI470X is not set
# CONFIG_DAB is not set
#
# Graphics support
#
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB_DDC is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
# CONFIG_FB_SYS_FILLRECT is not set
# CONFIG_FB_SYS_COPYAREA is not set
# CONFIG_FB_SYS_IMAGEBLIT is not set
# CONFIG_FB_FOREIGN_ENDIAN is not set
# CONFIG_FB_SYS_FOPS is not set
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set
#
# Frame buffer hardware drivers
#
# CONFIG_FB_UVESA is not set
# CONFIG_FB_S1D13XXX is not set
CONFIG_FB_PXA=y
# CONFIG_FB_PXA_SMARTPANEL is not set
CONFIG_FB_PXA_PARAMETERS=y
# CONFIG_FB_MBX is not set
# CONFIG_FB_AM200EPD is not set
# CONFIG_FB_VIRTUAL is not set
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_CORGI is not set
CONFIG_BACKLIGHT_PWM=y
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
CONFIG_FONTS=y
# CONFIG_FONT_8x8 is not set
# CONFIG_FONT_8x16 is not set
# CONFIG_FONT_6x11 is not set
# CONFIG_FONT_7x14 is not set
# CONFIG_FONT_PEARL_8x8 is not set
# CONFIG_FONT_ACORN_8x8 is not set
CONFIG_FONT_MINI_4x6=y
# CONFIG_FONT_SUN8x16 is not set
# CONFIG_FONT_SUN12x22 is not set
# CONFIG_FONT_10x18 is not set
# CONFIG_LOGO is not set
#
# Sound
#
CONFIG_SOUND=y
#
# Advanced Linux Sound Architecture
#
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
# CONFIG_SND_SEQUENCER is not set
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
CONFIG_SND_PCM_OSS_PLUGINS=y
# CONFIG_SND_DYNAMIC_MINORS is not set
CONFIG_SND_SUPPORT_OLD_API=y
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_DEBUG is not set
#
# Generic devices
#
# CONFIG_SND_DUMMY is not set
# CONFIG_SND_MTPAV is not set
# CONFIG_SND_SERIAL_U16550 is not set
# CONFIG_SND_MPU401 is not set
#
# ALSA ARM devices
#
# CONFIG_SND_PXA2XX_AC97 is not set
#
# SPI devices
#
#
# USB devices
#
# CONFIG_SND_USB_AUDIO is not set
# CONFIG_SND_USB_CAIAQ is not set
#
# System on Chip audio support
#
CONFIG_SND_SOC=y
CONFIG_SND_PXA2XX_SOC=y
#
# ALSA SoC audio for Freescale SOCs
#
#
# SoC Audio for the Texas Instruments OMAP
#
#
# Open Sound System
#
# CONFIG_SOUND_PRIME is not set
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
# CONFIG_HID_DEBUG is not set
# CONFIG_HIDRAW is not set
#
# USB Input Devices
#
# CONFIG_USB_HID is not set
#
# USB HID Boot Protocol drivers
#
# CONFIG_USB_KBD is not set
# CONFIG_USB_MOUSE is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
# CONFIG_USB_ARCH_HAS_EHCI is not set
CONFIG_USB=y
# CONFIG_USB_DEBUG is not set
# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
#
# Miscellaneous USB options
#
# CONFIG_USB_DEVICEFS is not set
# CONFIG_USB_DEVICE_CLASS is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_SUSPEND is not set
# CONFIG_USB_OTG is not set
# CONFIG_USB_OTG_WHITELIST is not set
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_ISP1760_HCD is not set
CONFIG_USB_OHCI_HCD=y
# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
#
# USB Device Class drivers
#
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
#
# may also be needed; see USB_STORAGE Help for more information
#
# CONFIG_USB_LIBUSUAL is not set
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MON is not set
#
# USB port drivers
#
# CONFIG_USB_SERIAL is not set
#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_AUERSWALD is not set
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_BERRY_CHARGE is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_PHIDGET is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG_FILES is not set
CONFIG_USB_GADGET_SELECTED=y
# CONFIG_USB_GADGET_AMD5536UDC is not set
# CONFIG_USB_GADGET_ATMEL_USBA is not set
# CONFIG_USB_GADGET_FSL_USB2 is not set
# CONFIG_USB_GADGET_NET2280 is not set
# CONFIG_USB_GADGET_PXA25X is not set
# CONFIG_USB_GADGET_M66592 is not set
CONFIG_USB_GADGET_PXA27X=y
CONFIG_USB_PXA27X=y
# CONFIG_USB_GADGET_GOKU is not set
# CONFIG_USB_GADGET_LH7A40X is not set
# CONFIG_USB_GADGET_OMAP is not set
# CONFIG_USB_GADGET_S3C2410 is not set
# CONFIG_USB_GADGET_AT91 is not set
# CONFIG_USB_GADGET_DUMMY_HCD is not set
# CONFIG_USB_GADGET_DUALSPEED is not set
# CONFIG_USB_ZERO is not set
CONFIG_USB_ETH=y
# CONFIG_USB_ETH_RNDIS is not set
# CONFIG_USB_GADGETFS is not set
# CONFIG_USB_FILE_STORAGE is not set
# CONFIG_USB_G_SERIAL is not set
# CONFIG_USB_MIDI_GADGET is not set
# CONFIG_USB_G_PRINTER is not set
CONFIG_MMC=y
# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_UNSAFE_RESUME=y
#
# MMC/SD Card Drivers
#
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_BOUNCE=y
CONFIG_SDIO_UART=y
#
# MMC/SD Host Controller Drivers
#
CONFIG_MMC_PXA=y
# CONFIG_MMC_SPI is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
#
# LED drivers
#
# CONFIG_LEDS_GPIO is not set
#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set
#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_S35390A is not set
#
# SPI RTC drivers
#
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_CMOS is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_SA1100=m
# CONFIG_UIO is not set
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
CONFIG_EXT3_FS=m
CONFIG_EXT3_FS_XATTR=y
# CONFIG_EXT3_FS_POSIX_ACL is not set
# CONFIG_EXT3_FS_SECURITY is not set
# CONFIG_EXT4DEV_FS is not set
CONFIG_JBD=m
CONFIG_FS_MBCACHE=y
CONFIG_REISERFS_FS=m
# CONFIG_REISERFS_CHECK is not set
# CONFIG_REISERFS_PROC_INFO is not set
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_REISERFS_FS_SECURITY=y
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_XFS_FS=m
# CONFIG_XFS_QUOTA is not set
# CONFIG_XFS_POSIX_ACL is not set
# CONFIG_XFS_RT is not set
# CONFIG_XFS_DEBUG is not set
# CONFIG_OCFS2_FS is not set
CONFIG_DNOTIFY=y
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
CONFIG_AUTOFS_FS=y
CONFIG_AUTOFS4_FS=y
CONFIG_FUSE_FS=m
#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=m
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS2_FS is not set
CONFIG_CRAMFS=m
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
# CONFIG_NFS_V4 is not set
CONFIG_NFSD=m
CONFIG_NFSD_V2_ACL=y
CONFIG_NFSD_V3=y
CONFIG_NFSD_V3_ACL=y
# CONFIG_NFSD_V4 is not set
# CONFIG_ROOT_NFS is not set
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_EXPORTFS=m
CONFIG_NFS_ACL_SUPPORT=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_BIND34 is not set
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
CONFIG_SMB_FS=m
# CONFIG_SMB_NLS_DEFAULT is not set
CONFIG_CIFS=m
CONFIG_CIFS_STATS=y
# CONFIG_CIFS_STATS2 is not set
CONFIG_CIFS_WEAK_PW_HASH=y
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
# CONFIG_CIFS_DEBUG2 is not set
# CONFIG_CIFS_EXPERIMENTAL is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=m
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_UTF8=m
# CONFIG_DLM is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_WARN_DEPRECATED=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_FRAME_WARN=1024
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_FRAME_POINTER=y
# CONFIG_SAMPLES is not set
# CONFIG_DEBUG_USER is not set
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
CONFIG_CRYPTO=y
#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=m
CONFIG_CRYPTO_AEAD=m
CONFIG_CRYPTO_BLKCIPHER=m
CONFIG_CRYPTO_HASH=m
CONFIG_CRYPTO_MANAGER=m
CONFIG_CRYPTO_GF128MUL=m
CONFIG_CRYPTO_NULL=m
CONFIG_CRYPTO_CRYPTD=m
CONFIG_CRYPTO_AUTHENC=m
CONFIG_CRYPTO_TEST=m
#
# Authenticated Encryption with Associated Data
#
# CONFIG_CRYPTO_CCM is not set
# CONFIG_CRYPTO_GCM is not set
# CONFIG_CRYPTO_SEQIV is not set
#
# Block modes
#
CONFIG_CRYPTO_CBC=m
# CONFIG_CRYPTO_CTR is not set
# CONFIG_CRYPTO_CTS is not set
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_LRW=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XTS=m
#
# Hash modes
#
CONFIG_CRYPTO_HMAC=m
CONFIG_CRYPTO_XCBC=m
#
# Digest
#
CONFIG_CRYPTO_CRC32C=m
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MD5=m
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_SHA1=m
CONFIG_CRYPTO_SHA256=m
CONFIG_CRYPTO_SHA512=m
CONFIG_CRYPTO_TGR192=m
# CONFIG_CRYPTO_WP512 is not set
#
# Ciphers
#
CONFIG_CRYPTO_AES=m
# CONFIG_CRYPTO_ANUBIS is not set
CONFIG_CRYPTO_ARC4=m
CONFIG_CRYPTO_BLOWFISH=m
# CONFIG_CRYPTO_CAMELLIA is not set
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_DES=m
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_KHAZAD=m
# CONFIG_CRYPTO_SALSA20 is not set
CONFIG_CRYPTO_SEED=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_TWOFISH_COMMON=m
#
# Compression
#
CONFIG_CRYPTO_DEFLATE=m
# CONFIG_CRYPTO_LZO is not set
CONFIG_CRYPTO_HW=y
#
# Library routines
#
CONFIG_BITREVERSE=y
# CONFIG_GENERIC_FIND_FIRST_BIT is not set
# CONFIG_GENERIC_FIND_NEXT_BIT is not set
CONFIG_CRC_CCITT=m
CONFIG_CRC16=m
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
CONFIG_LIBCRC32C=m
CONFIG_ZLIB_INFLATE=m
CONFIG_ZLIB_DEFLATE=m
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
arch/arm/mach-pxa/Kconfig
View file @ 30d38542
......@@ -16,18 +16,24 @@ config CPU_PXA310
config CPU_PXA320
bool "PXA320 (codename Monahans-P)"
config CPU_PXA930
bool "PXA930 (codename Tavor-P)"
endmenu
endif
menu "Select target boards"
config ARCH_GUMSTIX
bool "Gumstix XScale boards"
help
Say Y here if you intend to run this kernel on a
Gumstix Full Function Minature Computer.
config MACH_GUMSTIX_F
bool "Basix, Connex, ws-200ax, ws-400ax systems"
depends on ARCH_GUMSTIX
select PXA25x
config ARCH_LUBBOCK
bool "Intel DBPXA250 Development Platform"
select PXA25x
......@@ -58,6 +64,57 @@ config PXA_SHARPSL
SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa)
handheld computer.
config MACH_POODLE
bool "Enable Sharp SL-5600 (Poodle) Support"
depends on PXA_SHARPSL
select PXA25x
select SHARP_LOCOMO
select PXA_SSP
config MACH_CORGI
bool "Enable Sharp SL-C700 (Corgi) Support"
depends on PXA_SHARPSL
select PXA25x
select PXA_SHARP_C7xx
config MACH_SHEPHERD
bool "Enable Sharp SL-C750 (Shepherd) Support"
depends on PXA_SHARPSL
select PXA25x
select PXA_SHARP_C7xx
config MACH_HUSKY
bool "Enable Sharp SL-C760 (Husky) Support"
depends on PXA_SHARPSL
select PXA25x
select PXA_SHARP_C7xx
config MACH_AKITA
bool "Enable Sharp SL-1000 (Akita) Support"
depends on PXA_SHARPSL
select PXA27x
select PXA_SHARP_Cxx00
select MACH_SPITZ
select I2C
select I2C_PXA
config MACH_SPITZ
bool "Enable Sharp Zaurus SL-3000 (Spitz) Support"
depends on PXA_SHARPSL
select PXA27x
select PXA_SHARP_Cxx00
config MACH_BORZOI
bool "Enable Sharp Zaurus SL-3100 (Borzoi) Support"
depends on PXA_SHARPSL
select PXA27x
select PXA_SHARP_Cxx00
config MACH_TOSA
bool "Enable Sharp SL-6000x (Tosa) Support"
depends on PXA_SHARPSL
select PXA25x
config ARCH_PXA_ESERIES
bool "PXA based Toshiba e-series PDAs"
select PXA25x
......@@ -70,10 +127,19 @@ config MACH_E330
Say Y here if you intend to run this kernel on a Toshiba
e330 family PDA.
config MACH_E350
bool "Toshiba e350"
default y
depends on ARCH_PXA_ESERIES
help
Say Y here if you intend to run this kernel on a Toshiba
e350 family PDA.
config MACH_E740
bool "Toshiba e740"
default y
depends on ARCH_PXA_ESERIES
select FB_W100
help
Say Y here if you intend to run this kernel on a Toshiba
e740 family PDA.
......@@ -82,6 +148,7 @@ config MACH_E750
bool "Toshiba e750"
default y
depends on ARCH_PXA_ESERIES
select FB_W100
help
Say Y here if you intend to run this kernel on a Toshiba
e750 family PDA.
......@@ -98,6 +165,7 @@ config MACH_E800
bool "Toshiba e800"
default y
depends on ARCH_PXA_ESERIES
select FB_W100
help
Say Y here if you intend to run this kernel on a Toshiba
e800 family PDA.
......@@ -106,6 +174,10 @@ config MACH_TRIZEPS4
bool "Keith und Koep Trizeps4 DIMM-Module"
select PXA27x
config MACH_TRIZEPS4_CONXS
bool "ConXS Eval Board"
depends on MACH_TRIZEPS4
config MACH_EM_X270
bool "CompuLab EM-x270 platform"
select PXA27x
......@@ -115,7 +187,7 @@ config MACH_COLIBRI
select PXA27x
config MACH_ZYLONITE
bool "PXA3xx Development Platform"
bool "PXA3xx Development Platform (aka Zylonite)"
select PXA3xx
select HAVE_PWM
......@@ -124,6 +196,16 @@ config MACH_LITTLETON
select PXA3xx
select PXA_SSP
config MACH_TAVOREVB
bool "PXA930 Evaluation Board (aka TavorEVB)"
select PXA3xx
select PXA930
config MACH_SAAR
bool "PXA930 Handheld Platform (aka SAAR)"
select PXA3xx
select PXA930
config MACH_ARMCORE
bool "CompuLab CM-X270 modules"
select PXA27x
......@@ -131,7 +213,6 @@ config MACH_ARMCORE
config MACH_MAGICIAN
bool "Enable HTC Magician Support"
depends on ARCH_PXA
select PXA27x
select IWMMXT
......@@ -139,18 +220,26 @@ config MACH_PCM027
bool "Phytec phyCORE-PXA270 CPU module (PCM-027)"
select PXA27x
select IWMMXT
select PXA_SSP
endmenu
config ARCH_PXA_PALM
bool "PXA based Palm PDAs"
select HAVE_PWM
choice
prompt "Used baseboard"
depends on MACH_PCM027
config MACH_PALMTX
bool "Palm T|X"
default y
depends on ARCH_PXA_PALM
select PXA27x
select IWMMXT
help
Say Y here if you intend to run this kernel on a Palm T|X
handheld computer.
config MACH_PCM990_BASEBOARD
bool "PHYTEC PCM-990 development board"
select HAVE_PWM
endchoice
depends on MACH_PCM027
choice
prompt "display on pcm990"
......@@ -167,88 +256,45 @@ config PCM990_DISPLAY_NONE
endchoice
if ARCH_GUMSTIX
choice
prompt "Select target Gumstix board"
config MACH_GUMSTIX_F
bool "Basix, Connex, ws-200ax, ws-400ax systems"
select PXA25x
endchoice
endif
config PXA_EZX
bool "Motorola EZX Platform"
select PXA27x
select IWMMXT
select HAVE_PWM
if MACH_TRIZEPS4
config MACH_EZX_A780
bool "Motorola EZX A780"
default y
depends on PXA_EZX
choice
prompt "Select base board for Trizeps 4 module"
config MACH_EZX_E680
bool "Motorola EZX E680"
default y
depends on PXA_EZX
config MACH_TRIZEPS4_CONXS
bool "ConXS Eval Board"
config MACH_EZX_A1200
bool "Motorola EZX A1200"
default y
depends on PXA_EZX
config MACH_TRIZEPS4_ANY
bool "another Board"
config MACH_EZX_A910
bool "Motorola EZX A910"
default y
depends on PXA_EZX
endchoice
config MACH_EZX_E6
bool "Motorola EZX E6"
default y
depends on PXA_EZX
endif
config MACH_EZX_E2
bool "Motorola EZX E2"
default y
depends on PXA_EZX
endmenu
config MACH_POODLE
bool "Enable Sharp SL-5600 (Poodle) Support"
depends on PXA_SHARPSL
select PXA25x
select SHARP_LOCOMO
select PXA_SSP
config MACH_CORGI
bool "Enable Sharp SL-C700 (Corgi) Support"
depends on PXA_SHARPSL
select PXA25x
select PXA_SHARP_C7xx
config MACH_SHEPHERD
bool "Enable Sharp SL-C750 (Shepherd) Support"
depends on PXA_SHARPSL
select PXA25x
select PXA_SHARP_C7xx
config MACH_HUSKY
bool "Enable Sharp SL-C760 (Husky) Support"
depends on PXA_SHARPSL
select PXA25x
select PXA_SHARP_C7xx
config MACH_AKITA
bool "Enable Sharp SL-1000 (Akita) Support"
depends on PXA_SHARPSL
select PXA27x
select PXA_SHARP_Cxx00
select MACH_SPITZ
select I2C
select I2C_PXA
config MACH_SPITZ
bool "Enable Sharp Zaurus SL-3000 (Spitz) Support"
depends on PXA_SHARPSL
select PXA27x
select PXA_SHARP_Cxx00
config MACH_BORZOI
bool "Enable Sharp Zaurus SL-3100 (Borzoi) Support"
depends on PXA_SHARPSL
select PXA27x
select PXA_SHARP_Cxx00
config MACH_TOSA
bool "Enable Sharp SL-6000x (Tosa) Support"
depends on PXA_SHARPSL
select PXA25x
config PXA25x
bool
help
......@@ -288,4 +334,13 @@ config PXA_PWM
default BACKLIGHT_PWM
help
Enable support for PXA2xx/PXA3xx PWM controllers
config TOSA_BT
tristate "Control the state of built-in bluetooth chip on Sharp SL-6000"
depends on MACH_TOSA
select RFKILL
help
This is a simple driver that is able to control
the state of built in bluetooth chip on tosa.
endif
arch/arm/mach-pxa/Makefile
View file @ 30d38542
......@@ -4,7 +4,7 @@
# Common support (must be linked before board specific support)
obj-y += clock.o devices.o generic.o irq.o dma.o \
time.o gpio.o
time.o gpio.o reset.o
obj-$(CONFIG_PM) += pm.o sleep.o standby.o
obj-$(CONFIG_CPU_FREQ) += cpu-pxa.o
......@@ -18,6 +18,7 @@ obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa2xx.o pxa27x.o
obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o
obj-$(CONFIG_CPU_PXA300) += pxa300.o
obj-$(CONFIG_CPU_PXA320) += pxa320.o
obj-$(CONFIG_CPU_PXA930) += pxa930.o
# Specific board support
obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o
......@@ -36,7 +37,12 @@ obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o
obj-$(CONFIG_MACH_TOSA) += tosa.o
obj-$(CONFIG_MACH_EM_X270) += em-x270.o
obj-$(CONFIG_MACH_MAGICIAN) += magician.o
obj-$(CONFIG_ARCH_PXA_ESERIES) += eseries.o
obj-$(CONFIG_ARCH_PXA_ESERIES) += eseries.o eseries_udc.o
obj-$(CONFIG_MACH_E740) += e740_lcd.o
obj-$(CONFIG_MACH_E750) += e750_lcd.o
obj-$(CONFIG_MACH_E400) += e400_lcd.o
obj-$(CONFIG_MACH_E800) += e800_lcd.o
obj-$(CONFIG_MACH_PALMTX) += palmtx.o
ifeq ($(CONFIG_MACH_ZYLONITE),y)
obj-y += zylonite.o
......@@ -44,8 +50,11 @@ ifeq ($(CONFIG_MACH_ZYLONITE),y)
obj-$(CONFIG_CPU_PXA320) += zylonite_pxa320.o
endif
obj-$(CONFIG_MACH_LITTLETON) += littleton.o
obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o
obj-$(CONFIG_MACH_SAAR) += saar.o
obj-$(CONFIG_MACH_ARMCORE) += cm-x270.o
obj-$(CONFIG_PXA_EZX) += ezx.o
# Support for blinky lights
led-y := leds.o
......@@ -59,3 +68,5 @@ obj-$(CONFIG_LEDS) += $(led-y)
ifeq ($(CONFIG_PCI),y)
obj-$(CONFIG_MACH_ARMCORE) += cm-x270-pci.o
endif
obj-$(CONFIG_TOSA_BT) += tosa-bt.o
arch/arm/mach-pxa/clock.c
View file @ 30d38542
......@@ -101,21 +101,6 @@ unsigned long clk_get_rate(struct clk *clk)
EXPORT_SYMBOL(clk_get_rate);
static void clk_gpio27_enable(struct clk *clk)
{
pxa_gpio_mode(GPIO11_3_6MHz_MD);
}
static void clk_gpio27_disable(struct clk *clk)
{
}
static const struct clkops clk_gpio27_ops = {
.enable = clk_gpio27_enable,
.disable = clk_gpio27_disable,
};
void clk_cken_enable(struct clk *clk)
{
CKEN |= 1 << clk->cken;
......@@ -131,14 +116,6 @@ const struct clkops clk_cken_ops = {
.disable = clk_cken_disable,
};
static struct clk common_clks[] = {
{
.name = "GPIO27_CLK",
.ops = &clk_gpio27_ops,
.rate = 3686400,
},
};
void clks_register(struct clk *clks, size_t num)
{
int i;
......@@ -148,10 +125,3 @@ void clks_register(struct clk *clks, size_t num)
list_add(&clks[i].node, &clocks);
mutex_unlock(&clocks_mutex);
}
static int __init clk_init(void)
{
clks_register(common_clks, ARRAY_SIZE(common_clks));
return 0;
}
arch_initcall(clk_init);
arch/arm/mach-pxa/clock.h
View file @ 30d38542
......@@ -47,9 +47,42 @@ struct clk {
.other = _other, \
}
#define INIT_CLK(_name, _ops, _rate, _delay, _dev) \
{ \
.name = _name, \
.dev = _dev, \
.ops = _ops, \
.rate = _rate, \
.delay = _delay, \
}
extern const struct clkops clk_cken_ops;
void clk_cken_enable(struct clk *clk);
void clk_cken_disable(struct clk *clk);
#ifdef CONFIG_PXA3xx
#define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \
{ \
.name = _name, \
.dev = _dev, \
.ops = &clk_pxa3xx_cken_ops, \
.rate = _rate, \
.cken = CKEN_##_cken, \
.delay = _delay, \
}
#define PXA3xx_CK(_name, _cken, _ops, _dev) \
{ \
.name = _name, \
.dev = _dev, \
.ops = _ops, \
.cken = CKEN_##_cken, \
}
extern const struct clkops clk_pxa3xx_cken_ops;
extern void clk_pxa3xx_cken_enable(struct clk *);
extern void clk_pxa3xx_cken_disable(struct clk *);
#endif
void clks_register(struct clk *clks, size_t num);
arch/arm/mach-pxa/cm-x270-pci.c
View file @ 30d38542
......@@ -5,7 +5,7 @@
*
* Bits taken from various places.
*
* Copyright (C) 2007 Compulab, Ltd.
* Copyright (C) 2007, 2008 Compulab, Ltd.
* Mike Rapoport <mike@compulab.co.il>
*
* This program is free software; you can redistribute it and/or modify
......@@ -19,16 +19,16 @@
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <asm/mach/pci.h>
#include <asm/arch/cm-x270.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-gpio.h>
#include <asm/mach-types.h>
#include <asm/hardware/it8152.h>
unsigned long it8152_base_address = CMX270_IT8152_VIRT;
unsigned long it8152_base_address;
static int cmx270_it8152_irq_gpio;
/*
* Only first 64MB of memory can be accessed via PCI.
......@@ -42,7 +42,7 @@ void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size,
unsigned int sz = SZ_64M >> PAGE_SHIFT;
if (machine_is_armcore()) {
pr_info("Adjusting zones for CM-x270\n");
pr_info("Adjusting zones for CM-X270\n");
/*
* Only adjust if > 64M on current system
......@@ -60,19 +60,20 @@ void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size,
static void cmx270_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
{
/* clear our parent irq */
GEDR(GPIO_IT8152_IRQ) = GPIO_bit(GPIO_IT8152_IRQ);
GEDR(cmx270_it8152_irq_gpio) = GPIO_bit(cmx270_it8152_irq_gpio);
it8152_irq_demux(irq, desc);
}
void __cmx270_pci_init_irq(void)
void __cmx270_pci_init_irq(int irq_gpio)
{
it8152_init_irq();
pxa_gpio_mode(IRQ_TO_GPIO(GPIO_IT8152_IRQ));
set_irq_type(IRQ_GPIO(GPIO_IT8152_IRQ), IRQT_RISING);
set_irq_chained_handler(IRQ_GPIO(GPIO_IT8152_IRQ),
cmx270_it8152_irq_demux);
cmx270_it8152_irq_gpio = irq_gpio;
set_irq_type(gpio_to_irq(irq_gpio), IRQT_RISING);
set_irq_chained_handler(gpio_to_irq(irq_gpio), cmx270_it8152_irq_demux);
}
#ifdef CONFIG_PM
......@@ -115,8 +116,8 @@ static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
/*
Here comes the ugly part. The routing is baseboard specific,
but defining a platform for each possible base of CM-x270 is
unrealistic. Here we keep mapping for ATXBase and SB-x270.
but defining a platform for each possible base of CM-X270 is
unrealistic. Here we keep mapping for ATXBase and SB-X270.
*/
/* ATXBASE PCI slot */
if (slot == 7)
......
arch/arm/mach-pxa/cm-x270-pci.h
View file @ 30d38542
extern void __cmx270_pci_init_irq(void);
extern void __cmx270_pci_init_irq(int irq_gpio);
extern void __cmx270_pci_suspend(void);
extern void __cmx270_pci_resume(void);
#ifdef CONFIG_PCI
#define cmx270_pci_init_irq __cmx270_pci_init_irq
#define cmx270_pci_suspend __cmx270_pci_suspend
#define cmx270_pci_resume __cmx270_pci_resume
#define cmx270_pci_init_irq(x) __cmx270_pci_init_irq(x)
#define cmx270_pci_suspend(x) __cmx270_pci_suspend(x)
#define cmx270_pci_resume(x) __cmx270_pci_resume(x)
#else
#define cmx270_pci_init_irq() do {} while (0)
#define cmx270_pci_suspend() do {} while (0)
#define cmx270_pci_resume() do {} while (0)
#define cmx270_pci_init_irq(x) do {} while (0)
#define cmx270_pci_suspend(x) do {} while (0)
#define cmx270_pci_resume(x) do {} while (0)
#endif
arch/arm/mach-pxa/cm-x270.c
View file @ 30d38542
/*
* linux/arch/arm/mach-pxa/cm-x270.c
*
* Copyright (C) 2007 CompuLab, Ltd.
* Copyright (C) 2007, 2008 CompuLab, Ltd.
* Mike Rapoport <mike@compulab.co.il>
*
* This program is free software; you can redistribute it and/or modify
......@@ -9,44 +9,156 @@
* published by the Free Software Foundation.
*/
#include <linux/types.h>
#include <linux/pm.h>
#include <linux/fb.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/sysdev.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/dm9000.h>
#include <linux/rtc-v3020.h>
#include <linux/serial_8250.h>
#include <video/mbxfb.h>
#include <linux/leds.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/mfp-pxa27x.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/audio.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/ohci.h>
#include <asm/arch/mmc.h>
#include <asm/arch/bitfield.h>
#include <asm/arch/cm-x270.h>
#include <asm/hardware/it8152.h>
#include "generic.h"
#include "cm-x270-pci.h"
/* virtual addresses for statically mapped regions */
#define CMX270_VIRT_BASE (0xe8000000)
#define CMX270_IT8152_VIRT (CMX270_VIRT_BASE)
#define RTC_PHYS_BASE (PXA_CS1_PHYS + (5 << 22))
#define DM9000_PHYS_BASE (PXA_CS1_PHYS + (6 << 22))
static struct resource cmx270_dm9k_resource[] = {
/* GPIO IRQ usage */
#define GPIO10_ETHIRQ (10)
#define GPIO22_IT8152_IRQ (22)
#define GPIO83_MMC_IRQ (83)
#define GPIO95_GFXIRQ (95)
#define CMX270_ETHIRQ IRQ_GPIO(GPIO10_ETHIRQ)
#define CMX270_IT8152_IRQ IRQ_GPIO(GPIO22_IT8152_IRQ)
#define CMX270_MMC_IRQ IRQ_GPIO(GPIO83_MMC_IRQ)
#define CMX270_GFXIRQ IRQ_GPIO(GPIO95_GFXIRQ)
/* MMC power enable */
#define GPIO105_MMC_POWER (105)
static unsigned long cmx270_pin_config[] = {
/* AC'97 */
GPIO28_AC97_BITCLK,
GPIO29_AC97_SDATA_IN_0,
GPIO30_AC97_SDATA_OUT,
GPIO31_AC97_SYNC,
GPIO98_AC97_SYSCLK,
GPIO113_AC97_nRESET,
/* BTUART */
GPIO42_BTUART_RXD,
GPIO43_BTUART_TXD,
GPIO44_BTUART_CTS,
GPIO45_BTUART_RTS,
/* STUART */
GPIO46_STUART_RXD,
GPIO47_STUART_TXD,
/* MCI controller */
GPIO32_MMC_CLK,
GPIO112_MMC_CMD,
GPIO92_MMC_DAT_0,
GPIO109_MMC_DAT_1,
GPIO110_MMC_DAT_2,
GPIO111_MMC_DAT_3,
/* LCD */
GPIO58_LCD_LDD_0,
GPIO59_LCD_LDD_1,
GPIO60_LCD_LDD_2,
GPIO61_LCD_LDD_3,
GPIO62_LCD_LDD_4,
GPIO63_LCD_LDD_5,
GPIO64_LCD_LDD_6,
GPIO65_LCD_LDD_7,
GPIO66_LCD_LDD_8,
GPIO67_LCD_LDD_9,
GPIO68_LCD_LDD_10,
GPIO69_LCD_LDD_11,
GPIO70_LCD_LDD_12,
GPIO71_LCD_LDD_13,
GPIO72_LCD_LDD_14,
GPIO73_LCD_LDD_15,
GPIO74_LCD_FCLK,
GPIO75_LCD_LCLK,
GPIO76_LCD_PCLK,
GPIO77_LCD_BIAS,
/* I2C */
GPIO117_I2C_SCL,
GPIO118_I2C_SDA,
/* SSP1 */
GPIO23_SSP1_SCLK,
GPIO24_SSP1_SFRM,
GPIO25_SSP1_TXD,
GPIO26_SSP1_RXD,
/* SSP2 */
GPIO19_SSP2_SCLK,
GPIO14_SSP2_SFRM,
GPIO87_SSP2_TXD,
GPIO88_SSP2_RXD,
/* PC Card */
GPIO48_nPOE,
GPIO49_nPWE,
GPIO50_nPIOR,
GPIO51_nPIOW,
GPIO85_nPCE_1,
GPIO54_nPCE_2,
GPIO55_nPREG,
GPIO56_nPWAIT,
GPIO57_nIOIS16,
/* SDRAM and local bus */
GPIO15_nCS_1,
GPIO78_nCS_2,
GPIO79_nCS_3,
GPIO80_nCS_4,
GPIO33_nCS_5,
GPIO49_nPWE,
GPIO18_RDY,
/* GPIO */
GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH,
GPIO105_GPIO | MFP_LPM_DRIVE_HIGH, /* MMC/SD power */
GPIO53_GPIO, /* PC card reset */
/* NAND controls */
GPIO11_GPIO | MFP_LPM_DRIVE_HIGH, /* NAND CE# */
GPIO89_GPIO, /* NAND Ready/Busy */
/* interrupts */
GPIO10_GPIO, /* DM9000 interrupt */
GPIO83_GPIO, /* MMC card detect */
};
#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
static struct resource cmx270_dm9000_resource[] = {
[0] = {
.start = DM9000_PHYS_BASE,
.end = DM9000_PHYS_BASE + 4,
......@@ -64,31 +176,45 @@ static struct resource cmx270_dm9k_resource[] = {
}
};
/* for the moment we limit ourselves to 32bit IO until some
* better IO routines can be written and tested
*/
static struct dm9000_plat_data cmx270_dm9k_platdata = {
static struct dm9000_plat_data cmx270_dm9000_platdata = {
.flags = DM9000_PLATF_32BITONLY,
};
/* Ethernet device */
static struct platform_device cmx270_device_dm9k = {
static struct platform_device cmx270_dm9000_device = {
.name = "dm9000",
.id = 0,
.num_resources = ARRAY_SIZE(cmx270_dm9k_resource),
.resource = cmx270_dm9k_resource,
.num_resources = ARRAY_SIZE(cmx270_dm9000_resource),
.resource = cmx270_dm9000_resource,
.dev = {
.platform_data = &cmx270_dm9k_platdata,
.platform_data = &cmx270_dm9000_platdata,
}
};
/* touchscreen controller */
static void __init cmx270_init_dm9000(void)
{
platform_device_register(&cmx270_dm9000_device);
}
#else
static inline void cmx270_init_dm9000(void) {}
#endif
/* UCB1400 touchscreen controller */
#if defined(CONFIG_TOUCHSCREEN_UCB1400) || defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE)
static struct platform_device cmx270_ts_device = {
.name = "ucb1400_ts",
.id = -1,
};
/* RTC */
static void __init cmx270_init_touchscreen(void)
{
platform_device_register(&cmx270_ts_device);
}
#else
static inline void cmx270_init_touchscreen(void) {}
#endif
/* V3020 RTC */
#if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE)
static struct resource cmx270_v3020_resource[] = {
[0] = {
.start = RTC_PHYS_BASE,
......@@ -111,28 +237,67 @@ static struct platform_device cmx270_rtc_device = {
}
};
/*
* CM-X270 LEDs
*/
static void __init cmx270_init_rtc(void)
{
platform_device_register(&cmx270_rtc_device);
}
#else
static inline void cmx270_init_rtc(void) {}
#endif
/* CM-X270 LEDs */
#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
static struct gpio_led cmx270_leds[] = {
[0] = {
.name = "cm-x270:red",
.default_trigger = "nand-disk",
.gpio = 93,
.active_low = 1,
},
[1] = {
.name = "cm-x270:green",
.default_trigger = "heartbeat",
.gpio = 94,
.active_low = 1,
},
};
static struct gpio_led_platform_data cmx270_gpio_led_pdata = {
.num_leds = ARRAY_SIZE(cmx270_leds),
.leds = cmx270_leds,
};
static struct platform_device cmx270_led_device = {
.name = "cm-x270-led",
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &cmx270_gpio_led_pdata,
},
};
static void __init cmx270_init_leds(void)
{
platform_device_register(&cmx270_led_device);
}
#else
static inline void cmx270_init_leds(void) {}
#endif
/* 2700G graphics */
#if defined(CONFIG_FB_MBX) || defined(CONFIG_FB_MBX_MODULE)
static u64 fb_dma_mask = ~(u64)0;
static struct resource cmx270_2700G_resource[] = {
/* frame buffer memory including ODFB and External SDRAM */
[0] = {
.start = MARATHON_PHYS,
.end = MARATHON_PHYS + 0x02000000,
.start = PXA_CS2_PHYS,
.end = PXA_CS2_PHYS + 0x01ffffff,
.flags = IORESOURCE_MEM,
},
/* Marathon registers */
[1] = {
.start = MARATHON_PHYS + 0x03fe0000,
.end = MARATHON_PHYS + 0x03ffffff,
.start = PXA_CS2_PHYS + 0x03fe0000,
.end = PXA_CS2_PHYS + 0x03ffffff,
.flags = IORESOURCE_MEM,
},
};
......@@ -200,43 +365,15 @@ static struct platform_device cmx270_2700G = {
.id = -1,
};
static u64 ata_dma_mask = ~(u64)0;
static struct platform_device cmx270_ata = {
.name = "pata_cm_x270",
.id = -1,
.dev = {
.dma_mask = &ata_dma_mask,
.coherent_dma_mask = 0xffffffff,
},
};
/* platform devices */
static struct platform_device *platform_devices[] __initdata = {
&cmx270_device_dm9k,
&cmx270_rtc_device,
&cmx270_2700G,
&cmx270_led_device,
&cmx270_ts_device,
&cmx270_ata,
};
/* Map PCI companion and IDE/General Purpose CS statically */
static struct map_desc cmx270_io_desc[] __initdata = {
[0] = { /* IDE/general purpose space */
.virtual = CMX270_IDE104_VIRT,
.pfn = __phys_to_pfn(CMX270_IDE104_PHYS),
.length = SZ_64M - SZ_8M,
.type = MT_DEVICE
},
[1] = { /* PCI bridge */
.virtual = CMX270_IT8152_VIRT,
.pfn = __phys_to_pfn(CMX270_IT8152_PHYS),
.length = SZ_64M,
.type = MT_DEVICE
},
};
static void __init cmx270_init_2700G(void)
{
platform_device_register(&cmx270_2700G);
}
#else
static inline void cmx270_init_2700G(void) {}
#endif
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
/*
Display definitions
keep these for backwards compatibility, although symbolic names (as
......@@ -446,7 +583,16 @@ static int __init cmx270_set_display(char *str)
*/
__setup("monitor=", cmx270_set_display);
static void __init cmx270_init_display(void)
{
set_pxa_fb_info(cmx270_display);
}
#else
static inline void cmx270_init_display(void) {}
#endif
/* PXA27x OHCI controller setup */
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
static int cmx270_ohci_init(struct device *dev)
{
/* Set the Power Control Polarity Low */
......@@ -461,35 +607,37 @@ static struct pxaohci_platform_data cmx270_ohci_platform_data = {
.init = cmx270_ohci_init,
};
static void __init cmx270_init_ohci(void)
{
pxa_set_ohci_info(&cmx270_ohci_platform_data);
}
#else
static inline void cmx270_init_ohci(void) {}
#endif
#if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE)
static int cmx270_mci_init(struct device *dev,
irq_handler_t cmx270_detect_int,
void *data)
{
int err;
/*
* setup GPIO for PXA27x MMC controller
*/
pxa_gpio_mode(GPIO32_MMCCLK_MD);
pxa_gpio_mode(GPIO112_MMCCMD_MD);
pxa_gpio_mode(GPIO92_MMCDAT0_MD);
pxa_gpio_mode(GPIO109_MMCDAT1_MD);
pxa_gpio_mode(GPIO110_MMCDAT2_MD);
pxa_gpio_mode(GPIO111_MMCDAT3_MD);
/* SB-X270 uses GPIO105 as SD power enable */
pxa_gpio_mode(105 | GPIO_OUT);
err = gpio_request(GPIO105_MMC_POWER, "MMC/SD power");
if (err) {
dev_warn(dev, "power gpio unavailable\n");
return err;
}
/* card detect IRQ on GPIO 83 */
pxa_gpio_mode(IRQ_TO_GPIO(CMX270_MMC_IRQ));
gpio_direction_output(GPIO105_MMC_POWER, 0);
err = request_irq(CMX270_MMC_IRQ, cmx270_detect_int,
IRQF_DISABLED | IRQF_TRIGGER_FALLING,
"MMC card detect", data);
if (err)
printk(KERN_ERR "cmx270_mci_init: MMC/SD: can't"
" request MMC card detect IRQ\n");
if (err) {
gpio_free(GPIO105_MMC_POWER);
dev_err(dev, "cmx270_mci_init: MMC/SD: can't"
" request MMC card detect IRQ\n");
}
return err;
}
......@@ -499,17 +647,18 @@ static void cmx270_mci_setpower(struct device *dev, unsigned int vdd)
struct pxamci_platform_data *p_d = dev->platform_data;
if ((1 << vdd) & p_d->ocr_mask) {
printk(KERN_DEBUG "%s: on\n", __func__);
GPCR(105) = GPIO_bit(105);
dev_dbg(dev, "power on\n");
gpio_set_value(GPIO105_MMC_POWER, 0);
} else {
GPSR(105) = GPIO_bit(105);
printk(KERN_DEBUG "%s: off\n", __func__);
gpio_set_value(GPIO105_MMC_POWER, 1);
dev_dbg(dev, "power off\n");
}
}
static void cmx270_mci_exit(struct device *dev, void *data)
{
free_irq(CMX270_MMC_IRQ, data);
gpio_free(GPIO105_MMC_POWER);
}
static struct pxamci_platform_data cmx270_mci_platform_data = {
......@@ -519,6 +668,14 @@ static struct pxamci_platform_data cmx270_mci_platform_data = {
.exit = cmx270_mci_exit,
};
static void __init cmx270_init_mmc(void)
{
pxa_set_mci_info(&cmx270_mci_platform_data);
}
#else
static inline void cmx270_init_mmc(void) {}
#endif
#ifdef CONFIG_PM
static unsigned long sleep_save_msc[10];
......@@ -580,53 +737,63 @@ static int __init cmx270_pm_init(void)
static int __init cmx270_pm_init(void) { return 0; }
#endif
static void __init cmx270_init(void)
#if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE)
static void __init cmx270_init_ac97(void)
{
cmx270_pm_init();
set_pxa_fb_info(cmx270_display);
/* register CM-X270 platform devices */
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
pxa_set_ac97_info(NULL);
}
#else
static inline void cmx270_init_ac97(void) {}
#endif
/* set MCI and OHCI platform parameters */
pxa_set_mci_info(&cmx270_mci_platform_data);
pxa_set_ohci_info(&cmx270_ohci_platform_data);
/* This enables the STUART */
pxa_gpio_mode(GPIO46_STRXD_MD);
pxa_gpio_mode(GPIO47_STTXD_MD);
static void __init cmx270_init(void)
{
cmx270_pm_init();
/* This enables the BTUART */
pxa_gpio_mode(GPIO42_BTRXD_MD);
pxa_gpio_mode(GPIO43_BTTXD_MD);
pxa_gpio_mode(GPIO44_BTCTS_MD);
pxa_gpio_mode(GPIO45_BTRTS_MD);
pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx270_pin_config));
cmx270_init_dm9000();
cmx270_init_rtc();
cmx270_init_display();
cmx270_init_mmc();
cmx270_init_ohci();
cmx270_init_ac97();
cmx270_init_touchscreen();
cmx270_init_leds();
cmx270_init_2700G();
}
static void __init cmx270_init_irq(void)
{
pxa27x_init_irq();
cmx270_pci_init_irq(GPIO22_IT8152_IRQ);
}
cmx270_pci_init_irq();
#ifdef CONFIG_PCI
/* Map PCI companion statically */
static struct map_desc cmx270_io_desc[] __initdata = {
[0] = { /* PCI bridge */
.virtual = CMX270_IT8152_VIRT,
.pfn = __phys_to_pfn(PXA_CS4_PHYS),
.length = SZ_64M,
.type = MT_DEVICE
},
};
/* Setup interrupt for dm9000 */
pxa_gpio_mode(IRQ_TO_GPIO(CMX270_ETHIRQ));
set_irq_type(CMX270_ETHIRQ, IRQT_RISING);
static void __init cmx270_map_io(void)
{
pxa_map_io();
iotable_init(cmx270_io_desc, ARRAY_SIZE(cmx270_io_desc));
/* Setup interrupt for 2700G */
pxa_gpio_mode(IRQ_TO_GPIO(CMX270_GFXIRQ));
set_irq_type(CMX270_GFXIRQ, IRQT_FALLING);
it8152_base_address = CMX270_IT8152_VIRT;
}
#else
static void __init cmx270_map_io(void)
{
pxa_map_io();
iotable_init(cmx270_io_desc, ARRAY_SIZE(cmx270_io_desc));
}
#endif
MACHINE_START(ARMCORE, "Compulab CM-x270")
.boot_params = 0xa0000100,
......
arch/arm/mach-pxa/corgi.c
View file @ 30d38542
......@@ -465,6 +465,7 @@ static void corgi_irda_transceiver_mode(struct device *dev, int mode)
GPSR(CORGI_GPIO_IR_ON) = GPIO_bit(CORGI_GPIO_IR_ON);
else
GPCR(CORGI_GPIO_IR_ON) = GPIO_bit(CORGI_GPIO_IR_ON);
pxa2xx_transceiver_mode(dev, mode);
}
static struct pxaficp_platform_data corgi_ficp_platform_data = {
......
arch/arm/mach-pxa/devices.c
View file @ 30d38542
......@@ -13,8 +13,10 @@
#include <asm/arch/mfp-pxa27x.h>
#include <asm/arch/ohci.h>
#include <asm/arch/pxa27x_keypad.h>
#include <asm/arch/pxa2xx_spi.h>
#include <asm/arch/camera.h>
#include <asm/arch/audio.h>
#include <asm/arch/pxa3xx_nand.h>
#include "devices.h"
#include "generic.h"
......@@ -830,4 +832,63 @@ void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
pxa_register_device(&pxa3xx_device_mci3, info);
}
static struct resource pxa3xx_resources_nand[] = {
[0] = {
.start = 0x43100000,
.end = 0x43100053,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_NAND,
.end = IRQ_NAND,
.flags = IORESOURCE_IRQ,
},
[2] = {
/* DRCMR for Data DMA */
.start = 97,
.end = 97,
.flags = IORESOURCE_DMA,
},
[3] = {
/* DRCMR for Command DMA */
.start = 99,
.end = 99,
.flags = IORESOURCE_DMA,
},
};
static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
struct platform_device pxa3xx_device_nand = {
.name = "pxa3xx-nand",
.id = -1,
.dev = {
.dma_mask = &pxa3xx_nand_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
.resource = pxa3xx_resources_nand,
};
void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
{
pxa_register_device(&pxa3xx_device_nand, info);
}
#endif /* CONFIG_PXA3xx */
/* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
* See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
{
struct platform_device *pd;
pd = platform_device_alloc("pxa2xx-spi", id);
if (pd == NULL) {
printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
id);
return;
}
pd->dev.platform_data = info;
platform_device_add(pd);
}
arch/arm/mach-pxa/devices.h
View file @ 30d38542
......@@ -31,4 +31,6 @@ extern struct platform_device pxa25x_device_pwm1;
extern struct platform_device pxa27x_device_pwm0;
extern struct platform_device pxa27x_device_pwm1;
extern struct platform_device pxa3xx_device_nand;
void __init pxa_register_device(struct platform_device *dev, void *data);
arch/arm/mach-pxa/e400_lcd.c 0 → 100644
View file @ 30d38542
/*
* e400_lcd.c
*
* (c) 2005 Ian Molton <spyro@f2s.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <asm/mach-types.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxafb.h>
static struct pxafb_mode_info e400_pxafb_mode_info = {
.pixclock = 140703,
.xres = 240,
.yres = 320,
.bpp = 16,
.hsync_len = 4,
.left_margin = 28,
.right_margin = 8,
.vsync_len = 3,
.upper_margin = 5,
.lower_margin = 6,
.sync = 0,
};
static struct pxafb_mach_info e400_pxafb_mach_info = {
.modes = &e400_pxafb_mode_info,
.num_modes = 1,
.lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
.lccr3 = 0,
.pxafb_backlight_power = NULL,
};
static int __init e400_lcd_init(void)
{
if (!machine_is_e400())
return -ENODEV;
set_pxa_fb_info(&e400_pxafb_mach_info);
return 0;
}
module_init(e400_lcd_init);
MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
MODULE_DESCRIPTION("e400 lcd driver");
MODULE_LICENSE("GPLv2");
arch/arm/mach-pxa/e740_lcd.c 0 → 100644
View file @ 30d38542
/* e740_lcd.c
*
* This file contains the definitions for the LCD timings and functions
* to control the LCD power / frontlighting via the w100fb driver.
*
* (c) 2005 Ian Molton <spyro@f2s.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/fb.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <asm/mach-types.h>
#include <video/w100fb.h>
/*
**potential** shutdown routine - to be investigated
devmem2 0x0c010528 w 0xff3fff00
devmem2 0x0c010190 w 0x7FFF8000
devmem2 0x0c0101b0 w 0x00FF0000
devmem2 0x0c01008c w 0x00000000
devmem2 0x0c010080 w 0x000000bf
devmem2 0x0c010098 w 0x00000015
devmem2 0x0c010088 w 0x4b000204
devmem2 0x0c010098 w 0x0000001d
*/
static struct w100_gen_regs e740_lcd_regs = {
.lcd_format = 0x00008023,
.lcdd_cntl1 = 0x0f000000,
.lcdd_cntl2 = 0x0003ffff,
.genlcd_cntl1 = 0x00ffff03,
.genlcd_cntl2 = 0x003c0f03,
.genlcd_cntl3 = 0x000143aa,
};
static struct w100_mode e740_lcd_mode = {
.xres = 240,
.yres = 320,
.left_margin = 20,
.right_margin = 28,
.upper_margin = 9,
.lower_margin = 8,
.crtc_ss = 0x80140013,
.crtc_ls = 0x81150110,
.crtc_gs = 0x80050005,
.crtc_vpos_gs = 0x000a0009,
.crtc_rev = 0x0040010a,
.crtc_dclk = 0xa906000a,
.crtc_gclk = 0x80050108,
.crtc_goe = 0x80050108,
.pll_freq = 57,
.pixclk_divider = 4,
.pixclk_divider_rotated = 4,
.pixclk_src = CLK_SRC_XTAL,
.sysclk_divider = 1,
.sysclk_src = CLK_SRC_PLL,
.crtc_ps1_active = 0x41060010,
};
static struct w100_gpio_regs e740_w100_gpio_info = {
.init_data1 = 0x21002103,
.gpio_dir1 = 0xffffdeff,
.gpio_oe1 = 0x03c00643,
.init_data2 = 0x003f003f,
.gpio_dir2 = 0xffffffff,
.gpio_oe2 = 0x000000ff,
};
static struct w100fb_mach_info e740_fb_info = {
.modelist = &e740_lcd_mode,
.num_modes = 1,
.regs = &e740_lcd_regs,
.gpio = &e740_w100_gpio_info,
.xtal_freq = 14318000,
.xtal_dbl = 1,
};
static struct resource e740_fb_resources[] = {
[0] = {
.start = 0x0c000000,
.end = 0x0cffffff,
.flags = IORESOURCE_MEM,
},
};
/* ----------------------- device declarations -------------------------- */
static struct platform_device e740_fb_device = {
.name = "w100fb",
.id = -1,
.dev = {
.platform_data = &e740_fb_info,
},
.num_resources = ARRAY_SIZE(e740_fb_resources),
.resource = e740_fb_resources,
};
static int e740_lcd_init(void)
{
int ret;
if (!machine_is_e740())
return -ENODEV;
return platform_device_register(&e740_fb_device);
}
module_init(e740_lcd_init);
MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
MODULE_DESCRIPTION("e740 lcd driver");
MODULE_LICENSE("GPLv2");
arch/arm/mach-pxa/e750_lcd.c 0 → 100644
View file @ 30d38542
/* e750_lcd.c
*
* This file contains the definitions for the LCD timings and functions
* to control the LCD power / frontlighting via the w100fb driver.
*
* (c) 2005 Ian Molton <spyro@f2s.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/fb.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <asm/mach-types.h>
#include <video/w100fb.h>
static struct w100_gen_regs e750_lcd_regs = {
.lcd_format = 0x00008003,
.lcdd_cntl1 = 0x00000000,
.lcdd_cntl2 = 0x0003ffff,
.genlcd_cntl1 = 0x00fff003,
.genlcd_cntl2 = 0x003c0f03,
.genlcd_cntl3 = 0x000143aa,
};
static struct w100_mode e750_lcd_mode = {
.xres = 240,
.yres = 320,
.left_margin = 21,
.right_margin = 22,
.upper_margin = 5,
.lower_margin = 4,
.crtc_ss = 0x80150014,
.crtc_ls = 0x8014000d,
.crtc_gs = 0xc1000005,
.crtc_vpos_gs = 0x00020147,
.crtc_rev = 0x0040010a,
.crtc_dclk = 0xa1700030,
.crtc_gclk = 0x80cc0015,
.crtc_goe = 0x80cc0015,
.crtc_ps1_active = 0x61060017,
.pll_freq = 57,
.pixclk_divider = 4,
.pixclk_divider_rotated = 4,
.pixclk_src = CLK_SRC_XTAL,
.sysclk_divider = 1,
.sysclk_src = CLK_SRC_PLL,
};
static struct w100_gpio_regs e750_w100_gpio_info = {
.init_data1 = 0x01192f1b,
.gpio_dir1 = 0xd5ffdeff,
.gpio_oe1 = 0x000020bf,
.init_data2 = 0x010f010f,
.gpio_dir2 = 0xffffffff,
.gpio_oe2 = 0x000001cf,
};
static struct w100fb_mach_info e750_fb_info = {
.modelist = &e750_lcd_mode,
.num_modes = 1,
.regs = &e750_lcd_regs,
.gpio = &e750_w100_gpio_info,
.xtal_freq = 14318000,
.xtal_dbl = 1,
};
static struct resource e750_fb_resources[] = {
[0] = {
.start = 0x0c000000,
.end = 0x0cffffff,
.flags = IORESOURCE_MEM,
},
};
/* ----------------------- device declarations -------------------------- */
static struct platform_device e750_fb_device = {
.name = "w100fb",
.id = -1,
.dev = {
.platform_data = &e750_fb_info,
},
.num_resources = ARRAY_SIZE(e750_fb_resources),
.resource = e750_fb_resources,
};
static int e750_lcd_init(void)
{
if (!machine_is_e750())
return -ENODEV;
return platform_device_register(&e750_fb_device);
}
module_init(e750_lcd_init);
MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
MODULE_DESCRIPTION("e750 lcd driver");
MODULE_LICENSE("GPLv2");
arch/arm/mach-pxa/e800_lcd.c 0 → 100644
View file @ 30d38542
/* e800_lcd.c
*
* This file contains the definitions for the LCD timings and functions
* to control the LCD power / frontlighting via the w100fb driver.
*
* (c) 2005 Ian Molton <spyro@f2s.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/fb.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <asm/mach-types.h>
#include <video/w100fb.h>
static struct w100_gen_regs e800_lcd_regs = {
.lcd_format = 0x00008003,
.lcdd_cntl1 = 0x02a00000,
.lcdd_cntl2 = 0x0003ffff,
.genlcd_cntl1 = 0x000ff2a3,
.genlcd_cntl2 = 0x000002a3,
.genlcd_cntl3 = 0x000102aa,
};
static struct w100_mode e800_lcd_mode[2] = {
[0] = {
.xres = 480,
.yres = 640,
.left_margin = 52,
.right_margin = 148,
.upper_margin = 2,
.lower_margin = 6,
.crtc_ss = 0x80350034,
.crtc_ls = 0x802b0026,
.crtc_gs = 0x80160016,
.crtc_vpos_gs = 0x00020003,
.crtc_rev = 0x0040001d,
.crtc_dclk = 0xe0000000,
.crtc_gclk = 0x82a50049,
.crtc_goe = 0x80ee001c,
.crtc_ps1_active = 0x00000000,
.pll_freq = 128,
.pixclk_divider = 4,
.pixclk_divider_rotated = 6,
.pixclk_src = CLK_SRC_PLL,
.sysclk_divider = 0,
.sysclk_src = CLK_SRC_PLL,
},
[1] = {
.xres = 240,
.yres = 320,
.left_margin = 15,
.right_margin = 88,
.upper_margin = 0,
.lower_margin = 7,
.crtc_ss = 0xd010000f,
.crtc_ls = 0x80070003,
.crtc_gs = 0x80000000,
.crtc_vpos_gs = 0x01460147,
.crtc_rev = 0x00400003,
.crtc_dclk = 0xa1700030,
.crtc_gclk = 0x814b0008,
.crtc_goe = 0x80cc0015,
.crtc_ps1_active = 0x00000000,
.pll_freq = 100,
.pixclk_divider = 6, /* Wince uses 14 which gives a 7MHz pclk. */
.pixclk_divider_rotated = 6, /* we want a 14MHz one (much nicer to look at) */
.pixclk_src = CLK_SRC_PLL,
.sysclk_divider = 0,
.sysclk_src = CLK_SRC_PLL,
}
};
static struct w100_gpio_regs e800_w100_gpio_info = {
.init_data1 = 0xc13fc019,
.gpio_dir1 = 0x3e40df7f,
.gpio_oe1 = 0x003c3000,
.init_data2 = 0x00000000,
.gpio_dir2 = 0x00000000,
.gpio_oe2 = 0x00000000,
};
static struct w100_mem_info e800_w100_mem_info = {
.ext_cntl = 0x09640011,
.sdram_mode_reg = 0x00600021,
.ext_timing_cntl = 0x10001545,
.io_cntl = 0x7ddd7333,
.size = 0x1fffff,
};
static void e800_tg_change(struct w100fb_par *par)
{
unsigned long tmp;
tmp = w100fb_gpio_read(W100_GPIO_PORT_A);
if (par->mode->xres == 480)
tmp |= 0x100;
else
tmp &= ~0x100;
w100fb_gpio_write(W100_GPIO_PORT_A, tmp);
}
static struct w100_tg_info e800_tg_info = {
.change = e800_tg_change,
};
static struct w100fb_mach_info e800_fb_info = {
.modelist = e800_lcd_mode,
.num_modes = 2,
.regs = &e800_lcd_regs,
.gpio = &e800_w100_gpio_info,
.mem = &e800_w100_mem_info,
.tg = &e800_tg_info,
.xtal_freq = 16000000,
};
static struct resource e800_fb_resources[] = {
[0] = {
.start = 0x0c000000,
.end = 0x0cffffff,
.flags = IORESOURCE_MEM,
},
};
/* ----------------------- device declarations -------------------------- */
static struct platform_device e800_fb_device = {
.name = "w100fb",
.id = -1,
.dev = {
.platform_data = &e800_fb_info,
},
.num_resources = ARRAY_SIZE(e800_fb_resources),
.resource = e800_fb_resources,
};
static int e800_lcd_init(void)
{
if (!machine_is_e800())
return -ENODEV;
return platform_device_register(&e800_fb_device);
}
module_init(e800_lcd_init);
MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
MODULE_DESCRIPTION("e800 lcd driver");
MODULE_LICENSE("GPLv2");
arch/arm/mach-pxa/em-x270.c
View file @ 30d38542
/*
* Support for CompuLab EM-x270 platform
* Support for CompuLab EM-X270 platform
*
* Copyright (C) 2007 CompuLab, Ltd.
* Copyright (C) 2007, 2008 CompuLab, Ltd.
* Author: Mike Rapoport <mike@compulab.co.il>
*
* This program is free software; you can redistribute it and/or modify
......@@ -14,31 +14,159 @@
#include <linux/dm9000.h>
#include <linux/rtc-v3020.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <linux/gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/arch/mfp-pxa27x.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/pxa27x-udc.h>
#include <asm/arch/audio.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/ohci.h>
#include <asm/arch/mmc.h>
#include <asm/arch/bitfield.h>
#include <asm/arch/pxa27x_keypad.h>
#include "generic.h"
/* GPIO IRQ usage */
#define EM_X270_MMC_PD (105)
#define EM_X270_ETHIRQ IRQ_GPIO(41)
#define EM_X270_MMC_IRQ IRQ_GPIO(13)
#define GPIO41_ETHIRQ (41)
#define GPIO13_MMC_CD (13)
#define EM_X270_ETHIRQ IRQ_GPIO(GPIO41_ETHIRQ)
#define EM_X270_MMC_CD IRQ_GPIO(GPIO13_MMC_CD)
/* NAND control GPIOs */
#define GPIO11_NAND_CS (11)
#define GPIO56_NAND_RB (56)
static unsigned long em_x270_pin_config[] = {
/* AC'97 */
GPIO28_AC97_BITCLK,
GPIO29_AC97_SDATA_IN_0,
GPIO30_AC97_SDATA_OUT,
GPIO31_AC97_SYNC,
GPIO98_AC97_SYSCLK,
GPIO113_AC97_nRESET,
/* BTUART */
GPIO42_BTUART_RXD,
GPIO43_BTUART_TXD,
GPIO44_BTUART_CTS,
GPIO45_BTUART_RTS,
/* STUART */
GPIO46_STUART_RXD,
GPIO47_STUART_TXD,
/* MCI controller */
GPIO32_MMC_CLK,
GPIO112_MMC_CMD,
GPIO92_MMC_DAT_0,
GPIO109_MMC_DAT_1,
GPIO110_MMC_DAT_2,
GPIO111_MMC_DAT_3,
/* LCD */
GPIO58_LCD_LDD_0,
GPIO59_LCD_LDD_1,
GPIO60_LCD_LDD_2,
GPIO61_LCD_LDD_3,
GPIO62_LCD_LDD_4,
GPIO63_LCD_LDD_5,
GPIO64_LCD_LDD_6,
GPIO65_LCD_LDD_7,
GPIO66_LCD_LDD_8,
GPIO67_LCD_LDD_9,
GPIO68_LCD_LDD_10,
GPIO69_LCD_LDD_11,
GPIO70_LCD_LDD_12,
GPIO71_LCD_LDD_13,
GPIO72_LCD_LDD_14,
GPIO73_LCD_LDD_15,
GPIO74_LCD_FCLK,
GPIO75_LCD_LCLK,
GPIO76_LCD_PCLK,
GPIO77_LCD_BIAS,
/* QCI */
GPIO84_CIF_FV,
GPIO25_CIF_LV,
GPIO53_CIF_MCLK,
GPIO54_CIF_PCLK,
GPIO81_CIF_DD_0,
GPIO55_CIF_DD_1,
GPIO51_CIF_DD_2,
GPIO50_CIF_DD_3,
GPIO52_CIF_DD_4,
GPIO48_CIF_DD_5,
GPIO17_CIF_DD_6,
GPIO12_CIF_DD_7,
/* I2C */
GPIO117_I2C_SCL,
GPIO118_I2C_SDA,
/* Keypad */
GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
GPIO34_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH,
GPIO39_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH,
GPIO99_KP_MKIN_5 | WAKEUP_ON_LEVEL_HIGH,
GPIO91_KP_MKIN_6 | WAKEUP_ON_LEVEL_HIGH,
GPIO36_KP_MKIN_7 | WAKEUP_ON_LEVEL_HIGH,
GPIO103_KP_MKOUT_0,
GPIO104_KP_MKOUT_1,
GPIO105_KP_MKOUT_2,
GPIO106_KP_MKOUT_3,
GPIO107_KP_MKOUT_4,
GPIO108_KP_MKOUT_5,
GPIO96_KP_MKOUT_6,
GPIO22_KP_MKOUT_7,
/* SSP1 */
GPIO26_SSP1_RXD,
GPIO23_SSP1_SCLK,
GPIO24_SSP1_SFRM,
GPIO57_SSP1_TXD,
/* SSP2 */
GPIO19_SSP2_SCLK,
GPIO14_SSP2_SFRM,
GPIO89_SSP2_TXD,
GPIO88_SSP2_RXD,
/* SDRAM and local bus */
GPIO15_nCS_1,
GPIO78_nCS_2,
GPIO79_nCS_3,
GPIO80_nCS_4,
GPIO49_nPWE,
GPIO18_RDY,
/* GPIO */
GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
/* power controls */
GPIO20_GPIO | MFP_LPM_DRIVE_LOW, /* GPRS_PWEN */
GPIO115_GPIO | MFP_LPM_DRIVE_LOW, /* WLAN_PWEN */
/* NAND controls */
GPIO11_GPIO | MFP_LPM_DRIVE_HIGH, /* NAND CE# */
GPIO56_GPIO, /* NAND Ready/Busy */
/* interrupts */
GPIO13_GPIO, /* MMC card detect */
GPIO41_GPIO, /* DM9000 interrupt */
};
static struct resource em_x270_dm9k_resource[] = {
#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
static struct resource em_x270_dm9000_resource[] = {
[0] = {
.start = PXA_CS2_PHYS,
.end = PXA_CS2_PHYS + 3,
......@@ -56,32 +184,30 @@ static struct resource em_x270_dm9k_resource[] = {
}
};
/* for the moment we limit ourselves to 32bit IO until some
* better IO routines can be written and tested
*/
static struct dm9000_plat_data em_x270_dm9k_platdata = {
static struct dm9000_plat_data em_x270_dm9000_platdata = {
.flags = DM9000_PLATF_32BITONLY,
};
/* Ethernet device */
static struct platform_device em_x270_dm9k = {
static struct platform_device em_x270_dm9000 = {
.name = "dm9000",
.id = 0,
.num_resources = ARRAY_SIZE(em_x270_dm9k_resource),
.resource = em_x270_dm9k_resource,
.num_resources = ARRAY_SIZE(em_x270_dm9000_resource),
.resource = em_x270_dm9000_resource,
.dev = {
.platform_data = &em_x270_dm9k_platdata,
.platform_data = &em_x270_dm9000_platdata,
}
};
/* WM9712 touchscreen controller. Hopefully the driver will make it to
* the mainstream sometime */
static struct platform_device em_x270_ts = {
.name = "wm97xx-ts",
.id = -1,
};
static void __init em_x270_init_dm9000(void)
{
platform_device_register(&em_x270_dm9000);
}
#else
static inline void em_x270_init_dm9000(void) {}
#endif
/* RTC */
/* V3020 RTC */
#if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE)
static struct resource em_x270_v3020_resource[] = {
[0] = {
.start = PXA_CS4_PHYS,
......@@ -104,20 +230,26 @@ static struct platform_device em_x270_rtc = {
}
};
/* NAND flash */
#define GPIO_NAND_CS (11)
#define GPIO_NAND_RB (56)
static void __init em_x270_init_rtc(void)
{
platform_device_register(&em_x270_rtc);
}
#else
static inline void em_x270_init_rtc(void) {}
#endif
/* NAND flash */
#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
static inline void nand_cs_on(void)
{
GPCR(GPIO_NAND_CS) = GPIO_bit(GPIO_NAND_CS);
gpio_set_value(GPIO11_NAND_CS, 0);
}
static void nand_cs_off(void)
{
dsb();
GPSR(GPIO_NAND_CS) = GPIO_bit(GPIO_NAND_CS);
gpio_set_value(GPIO11_NAND_CS, 1);
}
/* hardware specific access to control-lines */
......@@ -157,7 +289,7 @@ static int em_x270_nand_device_ready(struct mtd_info *mtd)
{
dsb();
return GPLR(GPIO_NAND_RB) & GPIO_bit(GPIO_NAND_RB);
return gpio_get_value(GPIO56_NAND_RB);
}
static struct mtd_partition em_x270_partition_info[] = {
......@@ -210,16 +342,35 @@ static struct platform_device em_x270_nand = {
}
};
/* platform devices */
static struct platform_device *platform_devices[] __initdata = {
&em_x270_dm9k,
&em_x270_ts,
&em_x270_rtc,
&em_x270_nand,
};
static void __init em_x270_init_nand(void)
{
int err;
err = gpio_request(GPIO11_NAND_CS, "NAND CS");
if (err) {
pr_warning("EM-X270: failed to request NAND CS gpio\n");
return;
}
gpio_direction_output(GPIO11_NAND_CS, 1);
err = gpio_request(GPIO56_NAND_RB, "NAND R/B");
if (err) {
pr_warning("EM-X270: failed to request NAND R/B gpio\n");
gpio_free(GPIO11_NAND_CS);
return;
}
gpio_direction_input(GPIO56_NAND_RB);
platform_device_register(&em_x270_nand);
}
#else
static inline void em_x270_init_nand(void) {}
#endif
/* PXA27x OHCI controller setup */
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
static int em_x270_ohci_init(struct device *dev)
{
/* Set the Power Control Polarity Low */
......@@ -237,27 +388,23 @@ static struct pxaohci_platform_data em_x270_ohci_platform_data = {
.init = em_x270_ohci_init,
};
static void __init em_x270_init_ohci(void)
{
pxa_set_ohci_info(&em_x270_ohci_platform_data);
}
#else
static inline void em_x270_init_ohci(void) {}
#endif
/* MCI controller setup */
#if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE)
static int em_x270_mci_init(struct device *dev,
irq_handler_t em_x270_detect_int,
void *data)
{
int err;
/* setup GPIO for PXA27x MMC controller */
pxa_gpio_mode(GPIO32_MMCCLK_MD);
pxa_gpio_mode(GPIO112_MMCCMD_MD);
pxa_gpio_mode(GPIO92_MMCDAT0_MD);
pxa_gpio_mode(GPIO109_MMCDAT1_MD);
pxa_gpio_mode(GPIO110_MMCDAT2_MD);
pxa_gpio_mode(GPIO111_MMCDAT3_MD);
/* EM-X270 uses GPIO13 as SD power enable */
pxa_gpio_mode(EM_X270_MMC_PD | GPIO_OUT);
err = request_irq(EM_X270_MMC_IRQ, em_x270_detect_int,
IRQF_DISABLED | IRQF_TRIGGER_FALLING,
"MMC card detect", data);
int err = request_irq(EM_X270_MMC_CD, em_x270_detect_int,
IRQF_DISABLED | IRQF_TRIGGER_FALLING,
"MMC card detect", data);
if (err) {
printk(KERN_ERR "%s: can't request MMC card detect IRQ: %d\n",
__func__, err);
......@@ -279,7 +426,8 @@ static void em_x270_mci_setpower(struct device *dev, unsigned int vdd)
static void em_x270_mci_exit(struct device *dev, void *data)
{
free_irq(EM_X270_MMC_IRQ, data);
int irq = gpio_to_irq(GPIO13_MMC_CD);
free_irq(irq, data);
}
static struct pxamci_platform_data em_x270_mci_platform_data = {
......@@ -289,7 +437,16 @@ static struct pxamci_platform_data em_x270_mci_platform_data = {
.exit = em_x270_mci_exit,
};
static void __init em_x270_init_mmc(void)
{
pxa_set_mci_info(&em_x270_mci_platform_data);
}
#else
static inline void em_x270_init_mmc(void) {}
#endif
/* LCD 480x640 */
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
static struct pxafb_mode_info em_x270_lcd_mode = {
.pixclock = 50000,
.bpp = 16,
......@@ -307,40 +464,96 @@ static struct pxafb_mode_info em_x270_lcd_mode = {
static struct pxafb_mach_info em_x270_lcd = {
.modes = &em_x270_lcd_mode,
.num_modes = 1,
.cmap_inverse = 0,
.cmap_static = 0,
.lccr0 = LCCR0_PAS,
.lccr3 = LCCR3_PixClkDiv(0x01) | LCCR3_Acb(0xff),
.lcd_conn = LCD_COLOR_TFT_16BPP,
};
static void __init em_x270_init(void)
static void __init em_x270_init_lcd(void)
{
/* setup LCD */
set_pxa_fb_info(&em_x270_lcd);
}
#else
static inline void em_x270_init_lcd(void) {}
#endif
/* register EM-X270 platform devices */
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
#if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE)
static void __init em_x270_init_ac97(void)
{
pxa_set_ac97_info(NULL);
}
#else
static inline void em_x270_init_ac97(void) {}
#endif
#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
static unsigned int em_x270_matrix_keys[] = {
KEY(0, 0, KEY_A), KEY(1, 0, KEY_UP), KEY(2, 1, KEY_B),
KEY(0, 2, KEY_LEFT), KEY(1, 1, KEY_ENTER), KEY(2, 0, KEY_RIGHT),
KEY(0, 1, KEY_C), KEY(1, 2, KEY_DOWN), KEY(2, 2, KEY_D),
};
/* set MCI and OHCI platform parameters */
pxa_set_mci_info(&em_x270_mci_platform_data);
pxa_set_ohci_info(&em_x270_ohci_platform_data);
struct pxa27x_keypad_platform_data em_x270_keypad_info = {
/* code map for the matrix keys */
.matrix_key_rows = 3,
.matrix_key_cols = 3,
.matrix_key_map = em_x270_matrix_keys,
.matrix_key_map_size = ARRAY_SIZE(em_x270_matrix_keys),
};
static void __init em_x270_init_keypad(void)
{
pxa_set_keypad_info(&em_x270_keypad_info);
}
#else
static inline void em_x270_init_keypad(void) {}
#endif
/* setup STUART GPIOs */
pxa_gpio_mode(GPIO46_STRXD_MD);
pxa_gpio_mode(GPIO47_STTXD_MD);
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
static struct gpio_keys_button gpio_keys_button[] = {
[0] = {
.desc = "sleep/wakeup",
.code = KEY_SUSPEND,
.type = EV_PWR,
.gpio = 1,
.wakeup = 1,
},
};
/* setup BTUART GPIOs */
pxa_gpio_mode(GPIO42_BTRXD_MD);
pxa_gpio_mode(GPIO43_BTTXD_MD);
pxa_gpio_mode(GPIO44_BTCTS_MD);
pxa_gpio_mode(GPIO45_BTRTS_MD);
static struct gpio_keys_platform_data em_x270_gpio_keys_data = {
.buttons = gpio_keys_button,
.nbuttons = 1,
};
/* Setup interrupt for dm9000 */
set_irq_type(EM_X270_ETHIRQ, IRQT_RISING);
static struct platform_device em_x270_gpio_keys = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &em_x270_gpio_keys_data,
},
};
static void __init em_x270_init_gpio_keys(void)
{
platform_device_register(&em_x270_gpio_keys);
}
#else
static inline void em_x270_init_gpio_keys(void) {}
#endif
static void __init em_x270_init(void)
{
pxa2xx_mfp_config(ARRAY_AND_SIZE(em_x270_pin_config));
em_x270_init_dm9000();
em_x270_init_rtc();
em_x270_init_nand();
em_x270_init_lcd();
em_x270_init_mmc();
em_x270_init_ohci();
em_x270_init_keypad();
em_x270_init_gpio_keys();
em_x270_init_ac97();
}
MACHINE_START(EM_X270, "Compulab EM-x270")
MACHINE_START(EM_X270, "Compulab EM-X270")
.boot_params = 0xa0000100,
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
......
arch/arm/mach-pxa/eseries.c
View file @ 30d38542
......@@ -17,7 +17,7 @@
#include <asm/arch/hardware.h>
#include <asm/mach-types.h>
#include <generic.h>
#include "generic.h"
/* Only e800 has 128MB RAM */
static void __init eseries_fixup(struct machine_desc *desc,
......@@ -47,6 +47,19 @@ MACHINE_START(E330, "Toshiba e330")
MACHINE_END
#endif
#ifdef CONFIG_MACH_E350
MACHINE_START(E350, "Toshiba e350")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
.timer = &pxa_timer,
MACHINE_END
#endif
#ifdef CONFIG_MACH_E740
MACHINE_START(E740, "Toshiba e740")
/* Maintainer: Ian Molton (spyro@f2s.com) */
......
arch/arm/mach-pxa/eseries_udc.c 0 → 100644
View file @ 30d38542
/*
* UDC functions for the Toshiba e-series PDAs
*
* Copyright (c) Ian Molton 2003
*
* This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <asm/arch/udc.h>
#include <asm/arch/eseries-gpio.h>
#include <asm/arch/hardware.h>
#include <asm/arch/pxa-regs.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/domain.h>
/* local PXA generic code */
#include "generic.h"
static struct pxa2xx_udc_mach_info e7xx_udc_mach_info = {
.gpio_vbus = GPIO_E7XX_USB_DISC,
.gpio_pullup = GPIO_E7XX_USB_PULLUP,
.gpio_pullup_inverted = 1
};
static struct pxa2xx_udc_mach_info e800_udc_mach_info = {
.gpio_vbus = GPIO_E800_USB_DISC,
.gpio_pullup = GPIO_E800_USB_PULLUP,
.gpio_pullup_inverted = 1
};
static int __init eseries_udc_init(void)
{
if (machine_is_e330() || machine_is_e350() ||
machine_is_e740() || machine_is_e750() ||
machine_is_e400())
pxa_set_udc_info(&e7xx_udc_mach_info);
else if (machine_is_e800())
pxa_set_udc_info(&e800_udc_mach_info);
return 0;
}
module_init(eseries_udc_init);
MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
MODULE_DESCRIPTION("eseries UDC support");
MODULE_LICENSE("GPLv2");
arch/arm/mach-pxa/ezx.c 0 → 100644
View file @ 30d38542
/*
* ezx.c - Common code for the EZX platform.
*
* Copyright (C) 2005-2006 Harald Welte <laforge@openezx.org>,
* 2007-2008 Daniel Ribeiro <drwyrm@gmail.com>,
* 2007-2008 Stefan Schmidt <stefan@datenfreihafen.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/pwm_backlight.h>
#include <asm/setup.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/ohci.h>
#include <asm/arch/i2c.h>
#include <asm/arch/mfp-pxa27x.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include "devices.h"
#include "generic.h"
static struct platform_pwm_backlight_data ezx_backlight_data = {
.pwm_id = 0,
.max_brightness = 1023,
.dft_brightness = 1023,
.pwm_period_ns = 78770,
};
static struct platform_device ezx_backlight_device = {
.name = "pwm-backlight",
.dev = {
.parent = &pxa27x_device_pwm0.dev,
.platform_data = &ezx_backlight_data,
},
};
static struct pxafb_mode_info mode_ezx_old = {
.pixclock = 150000,
.xres = 240,
.yres = 320,
.bpp = 16,
.hsync_len = 10,
.left_margin = 20,
.right_margin = 10,
.vsync_len = 2,
.upper_margin = 3,
.lower_margin = 2,
.sync = 0,
};
static struct pxafb_mach_info ezx_fb_info_1 = {
.modes = &mode_ezx_old,
.num_modes = 1,
.lcd_conn = LCD_COLOR_TFT_16BPP,
};
static struct pxafb_mode_info mode_72r89803y01 = {
.pixclock = 192308,
.xres = 240,
.yres = 320,
.bpp = 32,
.depth = 18,
.hsync_len = 10,
.left_margin = 20,
.right_margin = 10,
.vsync_len = 2,
.upper_margin = 3,
.lower_margin = 2,
.sync = 0,
};
static struct pxafb_mach_info ezx_fb_info_2 = {
.modes = &mode_72r89803y01,
.num_modes = 1,
.lcd_conn = LCD_COLOR_TFT_18BPP,
};
static struct platform_device *devices[] __initdata = {
&ezx_backlight_device,
};
static unsigned long ezx_pin_config[] __initdata = {
/* PWM backlight */
GPIO16_PWM0_OUT,
/* BTUART */
GPIO42_BTUART_RXD,
GPIO43_BTUART_TXD,
GPIO44_BTUART_CTS,
GPIO45_BTUART_RTS,
/* STUART */
GPIO46_STUART_RXD,
GPIO47_STUART_TXD,
/* For A780 support (connected with Neptune GSM chip) */
GPIO30_USB_P3_2, /* ICL_TXENB */
GPIO31_USB_P3_6, /* ICL_VPOUT */
GPIO90_USB_P3_5, /* ICL_VPIN */
GPIO91_USB_P3_1, /* ICL_XRXD */
GPIO56_USB_P3_4, /* ICL_VMOUT */
GPIO113_USB_P3_3, /* /ICL_VMIN */
};
static void __init ezx_init(void)
{
pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config));
pxa_set_i2c_info(NULL);
if (machine_is_ezx_a780() || machine_is_ezx_e680())
set_pxa_fb_info(&ezx_fb_info_1);
else
set_pxa_fb_info(&ezx_fb_info_2);
platform_add_devices(devices, ARRAY_SIZE(devices));
}
static void __init ezx_fixup(struct machine_desc *desc, struct tag *tags,
char **cmdline, struct meminfo *mi)
{
/* We have two ram chips. First one with 32MB at 0xA0000000 and a second
* 16MB one at 0xAC000000
*/
mi->nr_banks = 2;
mi->bank[0].start = 0xa0000000;
mi->bank[0].node = 0;
mi->bank[0].size = (32*1024*1024);
mi->bank[1].start = 0xac000000;
mi->bank[1].node = 1;
mi->bank[1].size = (16*1024*1024);
}
#ifdef CONFIG_MACH_EZX_A780
MACHINE_START(EZX_A780, "Motorola EZX A780")
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.fixup = ezx_fixup,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa27x_init_irq,
.timer = &pxa_timer,
.init_machine = &ezx_init,
MACHINE_END
#endif
#ifdef CONFIG_MACH_EZX_E680
MACHINE_START(EZX_E680, "Motorola EZX E680")
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.fixup = ezx_fixup,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa27x_init_irq,
.timer = &pxa_timer,
.init_machine = &ezx_init,
MACHINE_END
#endif
#ifdef CONFIG_MACH_EZX_A1200
MACHINE_START(EZX_A1200, "Motorola EZX A1200")
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.fixup = ezx_fixup,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa27x_init_irq,
.timer = &pxa_timer,
.init_machine = &ezx_init,
MACHINE_END
#endif
#ifdef CONFIG_MACH_EZX_A910
MACHINE_START(EZX_A910, "Motorola EZX A910")
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.fixup = ezx_fixup,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa27x_init_irq,
.timer = &pxa_timer,
.init_machine = &ezx_init,
MACHINE_END
#endif
#ifdef CONFIG_MACH_EZX_E6
MACHINE_START(EZX_E6, "Motorola EZX E6")
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.fixup = ezx_fixup,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa27x_init_irq,
.timer = &pxa_timer,
.init_machine = &ezx_init,
MACHINE_END
#endif
#ifdef CONFIG_MACH_EZX_E2
MACHINE_START(EZX_E2, "Motorola EZX E2")
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.fixup = ezx_fixup,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa27x_init_irq,
.timer = &pxa_timer,
.init_machine = &ezx_init,
MACHINE_END
#endif
arch/arm/mach-pxa/littleton.c
View file @ 30d38542
......@@ -20,6 +20,7 @@
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/smc91x.h>
#include <asm/types.h>
#include <asm/setup.h>
......@@ -38,6 +39,7 @@
#include <asm/arch/pxafb.h>
#include <asm/arch/ssp.h>
#include <asm/arch/pxa27x_keypad.h>
#include <asm/arch/pxa3xx_nand.h>
#include <asm/arch/littleton.h>
#include "generic.h"
......@@ -101,18 +103,26 @@ static struct resource smc91x_resources[] = {
[1] = {
.start = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)),
.end = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)),
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
}
};
static struct smc91x_platdata littleton_smc91x_info = {
.flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT |
SMC91X_NOWAIT | SMC91X_USE_DMA,
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
.dev = {
.platform_data = &littleton_smc91x_info,
},
};
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULES)
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
/* use bit 30, 31 as the indicator of command parameter number */
#define CMD0(x) ((0x00000000) | ((x) << 9))
#define CMD1(x, x1) ((0x40000000) | ((x) << 9) | 0x100 | (x1))
......@@ -311,9 +321,9 @@ static void littleton_init_lcd(void)
}
#else
static inline void littleton_init_lcd(void) {};
#endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULES */
#endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULE */
#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULES)
#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
static unsigned int littleton_matrix_key_map[] = {
/* KEY(row, col, key_code) */
KEY(1, 3, KEY_0), KEY(0, 0, KEY_1), KEY(1, 0, KEY_2), KEY(2, 0, KEY_3),
......@@ -361,6 +371,57 @@ static void __init littleton_init_keypad(void)
static inline void littleton_init_keypad(void) {}
#endif
#if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE)
static struct mtd_partition littleton_nand_partitions[] = {
[0] = {
.name = "Bootloader",
.offset = 0,
.size = 0x060000,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
[1] = {
.name = "Kernel",
.offset = 0x060000,
.size = 0x200000,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
[2] = {
.name = "Filesystem",
.offset = 0x0260000,
.size = 0x3000000, /* 48M - rootfs */
},
[3] = {
.name = "MassStorage",
.offset = 0x3260000,
.size = 0x3d40000,
},
[4] = {
.name = "BBT",
.offset = 0x6FA0000,
.size = 0x80000,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
/* NOTE: we reserve some blocks at the end of the NAND flash for
* bad block management, and the max number of relocation blocks
* differs on different platforms. Please take care with it when
* defining the partition table.
*/
};
static struct pxa3xx_nand_platform_data littleton_nand_info = {
.enable_arbiter = 1,
.parts = littleton_nand_partitions,
.nr_parts = ARRAY_SIZE(littleton_nand_partitions),
};
static void __init littleton_init_nand(void)
{
pxa3xx_set_nand_info(&littleton_nand_info);
}
#else
static inline void littleton_init_nand(void) {}
#endif /* CONFIG_MTD_NAND_PXA3xx || CONFIG_MTD_NAND_PXA3xx_MODULE */
static void __init littleton_init(void)
{
/* initialize MFP configurations */
......@@ -374,6 +435,7 @@ static void __init littleton_init(void)
littleton_init_lcd();
littleton_init_keypad();
littleton_init_nand();
}
MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)")
......
arch/arm/mach-pxa/lubbock.c
View file @ 30d38542
......@@ -21,6 +21,7 @@
#include <linux/interrupt.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/smc91x.h>
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
......@@ -226,14 +227,6 @@ static struct pxa2xx_spi_master pxa_ssp_master_info = {
.num_chipselect = 0,
};
static struct platform_device pxa_ssp = {
.name = "pxa2xx-spi",
.id = 1,
.dev = {
.platform_data = &pxa_ssp_master_info,
},
};
static int lubbock_ads7846_pendown_state(void)
{
/* TS_BUSY is bit 8 in LUB_MISC_RD, but pendown is irq-only */
......@@ -292,11 +285,18 @@ static struct resource smc91x_resources[] = {
},
};
static struct smc91x_platdata lubbock_smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_2,
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = -1,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
.dev = {
.platform_data = &lubbock_smc91x_info,
},
};
static struct resource flash_resources[] = {
......@@ -367,7 +367,6 @@ static struct platform_device *devices[] __initdata = {
&smc91x_device,
&lubbock_flash_device[0],
&lubbock_flash_device[1],
&pxa_ssp,
};
static struct pxafb_mode_info sharp_lm8v31_mode = {
......@@ -471,6 +470,7 @@ static void lubbock_irda_transceiver_mode(struct device *dev, int mode)
} else if (mode & IR_FIRMODE) {
LUB_MISC_WR |= 1 << 4;
}
pxa2xx_transceiver_mode(dev, mode);
local_irq_restore(flags);
}
......@@ -501,6 +501,7 @@ static void __init lubbock_init(void)
lubbock_flash_data[flashboot].name = "boot-rom";
(void) platform_add_devices(devices, ARRAY_SIZE(devices));
pxa2xx_set_spi_info(1, &pxa_ssp_master_info);
spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
}
......
arch/arm/mach-pxa/magician.c
View file @ 30d38542
......@@ -17,17 +17,15 @@
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/mfd/htc-egpio.h>
#include <linux/mfd/htc-pasic3.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/physmap.h>
#include <linux/pda_power.h>
#include <linux/pwm_backlight.h>
#include <asm/gpio.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
......@@ -44,7 +42,7 @@
#include "devices.h"
#include "generic.h"
static unsigned long magician_pin_config[] = {
static unsigned long magician_pin_config[] __initdata = {
/* SDRAM and Static Memory I/O Signals */
GPIO20_nSDCS_2,
......@@ -134,6 +132,7 @@ static unsigned long magician_pin_config[] = {
static void magician_irda_transceiver_mode(struct device *dev, int mode)
{
gpio_set_value(GPIO83_MAGICIAN_nIR_EN, mode & IR_OFF);
pxa2xx_transceiver_mode(dev, mode);
}
static struct pxaficp_platform_data magician_ficp_info = {
......@@ -399,6 +398,7 @@ static struct platform_pwm_backlight_data backlight_data = {
static struct platform_device backlight = {
.name = "pwm-backlight",
.id = -1,
.dev = {
.parent = &pxa27x_device_pwm0.dev,
.platform_data = &backlight_data,
......@@ -511,6 +511,37 @@ static struct platform_device pasic3 = {
* External power
*/
static int power_supply_init(struct device *dev)
{
int ret;
ret = gpio_request(EGPIO_MAGICIAN_CABLE_STATE_AC, "CABLE_STATE_AC");
if (ret)
goto err_cs_ac;
ret = gpio_request(EGPIO_MAGICIAN_CABLE_STATE_USB, "CABLE_STATE_USB");
if (ret)
goto err_cs_usb;
ret = gpio_request(EGPIO_MAGICIAN_CHARGE_EN, "CHARGE_EN");
if (ret)
goto err_chg_en;
ret = gpio_request(GPIO30_MAGICIAN_nCHARGE_EN, "nCHARGE_EN");
if (!ret)
ret = gpio_direction_output(GPIO30_MAGICIAN_nCHARGE_EN, 0);
if (ret)
goto err_nchg_en;
return 0;
err_nchg_en:
gpio_free(EGPIO_MAGICIAN_CHARGE_EN);
err_chg_en:
gpio_free(EGPIO_MAGICIAN_CABLE_STATE_USB);
err_cs_usb:
gpio_free(EGPIO_MAGICIAN_CABLE_STATE_AC);
err_cs_ac:
return ret;
}
static int magician_is_ac_online(void)
{
return gpio_get_value(EGPIO_MAGICIAN_CABLE_STATE_AC);
......@@ -527,14 +558,24 @@ static void magician_set_charge(int flags)
gpio_set_value(EGPIO_MAGICIAN_CHARGE_EN, flags);
}
static void power_supply_exit(struct device *dev)
{
gpio_free(GPIO30_MAGICIAN_nCHARGE_EN);
gpio_free(EGPIO_MAGICIAN_CHARGE_EN);
gpio_free(EGPIO_MAGICIAN_CABLE_STATE_USB);
gpio_free(EGPIO_MAGICIAN_CABLE_STATE_AC);
}
static char *magician_supplicants[] = {
"ds2760-battery.0", "backup-battery"
};
static struct pda_power_pdata power_supply_info = {
.init = power_supply_init,
.is_ac_online = magician_is_ac_online,
.is_usb_online = magician_is_usb_online,
.set_charge = magician_set_charge,
.exit = power_supply_exit,
.supplied_to = magician_supplicants,
.num_supplicants = ARRAY_SIZE(magician_supplicants),
};
......
arch/arm/mach-pxa/mainstone.c
View file @ 30d38542
......@@ -26,6 +26,7 @@
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <linux/pwm_backlight.h>
#include <linux/smc91x.h>
#include <asm/types.h>
#include <asm/setup.h>
......@@ -110,9 +111,9 @@ static unsigned long mainstone_pin_config[] = {
GPIO45_AC97_SYSCLK,
/* Keypad */
GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH,
GPIO94_KP_DKIN_1 | WAKEUP_ON_LEVEL_HIGH,
GPIO95_KP_DKIN_2 | WAKEUP_ON_LEVEL_HIGH,
GPIO93_KP_DKIN_0,
GPIO94_KP_DKIN_1,
GPIO95_KP_DKIN_2,
GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
......@@ -240,11 +241,19 @@ static struct resource smc91x_resources[] = {
}
};
static struct smc91x_platdata mainstone_smc91x_info = {
.flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT |
SMC91X_NOWAIT | SMC91X_USE_DMA,
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
.dev = {
.platform_data = &mainstone_smc91x_info,
},
};
static int mst_audio_startup(struct snd_pcm_substream *substream, void *priv)
......@@ -455,6 +464,7 @@ static void mainstone_irda_transceiver_mode(struct device *dev, int mode)
} else if (mode & IR_FIRMODE) {
MST_MSCWR1 |= MST_MSCWR1_IRDA_FIR;
}
pxa2xx_transceiver_mode(dev, mode);
if (mode & IR_OFF) {
MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_OFF;
} else {
......@@ -513,7 +523,7 @@ static struct pxaohci_platform_data mainstone_ohci_platform_data = {
.init = mainstone_ohci_init,
};
#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULES)
#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
static unsigned int mainstone_matrix_keys[] = {
KEY(0, 0, KEY_A), KEY(1, 0, KEY_B), KEY(2, 0, KEY_C),
KEY(3, 0, KEY_D), KEY(4, 0, KEY_E), KEY(5, 0, KEY_F),
......
arch/arm/mach-pxa/mfp-pxa2xx.c
View file @ 30d38542
......@@ -39,6 +39,28 @@ struct gpio_desc {
static struct gpio_desc gpio_desc[MFP_PIN_GPIO127 + 1];
static int __mfp_config_lpm(unsigned gpio, unsigned long lpm)
{
unsigned mask = GPIO_bit(gpio);
/* low power state */
switch (lpm) {
case MFP_LPM_DRIVE_HIGH:
PGSR(gpio) |= mask;
break;
case MFP_LPM_DRIVE_LOW:
PGSR(gpio) &= ~mask;
break;
case MFP_LPM_INPUT:
break;
default:
pr_warning("%s: invalid low power state for GPIO%d\n",
__func__, gpio);
return -EINVAL;
}
return 0;
}
static int __mfp_config_gpio(unsigned gpio, unsigned long c)
{
unsigned long gafr, mask = GPIO_bit(gpio);
......@@ -57,21 +79,8 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c)
else
GPDR(gpio) &= ~mask;
/* low power state */
switch (c & MFP_LPM_STATE_MASK) {
case MFP_LPM_DRIVE_HIGH:
PGSR(gpio) |= mask;
break;
case MFP_LPM_DRIVE_LOW:
PGSR(gpio) &= ~mask;
break;
case MFP_LPM_INPUT:
break;
default:
pr_warning("%s: invalid low power state for GPIO%d\n",
__func__, gpio);
if (__mfp_config_lpm(gpio, c & MFP_LPM_STATE_MASK))
return -EINVAL;
}
/* give early warning if MFP_LPM_CAN_WAKEUP is set on the
* configurations of those pins not able to wakeup
......@@ -91,6 +100,18 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c)
return 0;
}
static inline int __mfp_validate(int mfp)
{
int gpio = mfp_to_gpio(mfp);
if ((mfp > MFP_PIN_GPIO127) || !gpio_desc[gpio].valid) {
pr_warning("%s: GPIO%d is invalid pin\n", __func__, gpio);
return -1;
}
return gpio;
}
void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num)
{
unsigned long flags;
......@@ -99,13 +120,9 @@ void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num)
for (i = 0, c = mfp_cfgs; i < num; i++, c++) {
gpio = mfp_to_gpio(MFP_PIN(*c));
if (!gpio_desc[gpio].valid) {
pr_warning("%s: GPIO%d is invalid pin\n",
__func__, gpio);
gpio = __mfp_validate(MFP_PIN(*c));
if (gpio < 0)
continue;
}
local_irq_save(flags);
......@@ -116,6 +133,20 @@ void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num)
}
}
void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm)
{
unsigned long flags;
int gpio;
gpio = __mfp_validate(mfp);
if (gpio < 0)
return;
local_irq_save(flags);
__mfp_config_lpm(gpio, lpm);
local_irq_restore(flags);
}
int gpio_set_wake(unsigned int gpio, unsigned int on)
{
struct gpio_desc *d;
......
arch/arm/mach-pxa/palmtx.c 0 → 100644
View file @ 30d38542
/*
* Hardware definitions for PalmTX
*
* Author: Marek Vasut <marek.vasut@gmail.com>
*
* Based on work of:
* Alex Osborne <ato@meshy.org>
* Cristiano P. <cristianop@users.sourceforge.net>
* Jan Herman <2hp@seznam.cz>
* Michal Hrusecky
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* (find more info at www.hackndev.com)
*
*/
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/pda_power.h>
#include <linux/pwm_backlight.h>
#include <linux/gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/arch/audio.h>
#include <asm/arch/palmtx.h>
#include <asm/arch/mmc.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/mfp-pxa27x.h>
#include <asm/arch/irda.h>
#include <asm/arch/pxa27x_keypad.h>
#include <asm/arch/udc.h>
#include "generic.h"
#include "devices.h"
/******************************************************************************
* Pin configuration
******************************************************************************/
static unsigned long palmtx_pin_config[] __initdata = {
/* MMC */
GPIO32_MMC_CLK,
GPIO92_MMC_DAT_0,
GPIO109_MMC_DAT_1,
GPIO110_MMC_DAT_2,
GPIO111_MMC_DAT_3,
GPIO112_MMC_CMD,
/* AC97 */
GPIO28_AC97_BITCLK,
GPIO29_AC97_SDATA_IN_0,
GPIO30_AC97_SDATA_OUT,
GPIO31_AC97_SYNC,
/* IrDA */
GPIO46_FICP_RXD,
GPIO47_FICP_TXD,
/* PWM */
GPIO16_PWM0_OUT,
/* USB */
GPIO13_GPIO,
/* PCMCIA */
GPIO48_nPOE,
GPIO49_nPWE,
GPIO50_nPIOR,
GPIO51_nPIOW,
GPIO85_nPCE_1,
GPIO54_nPCE_2,
GPIO79_PSKTSEL,
GPIO55_nPREG,
GPIO56_nPWAIT,
GPIO57_nIOIS16,
};
/******************************************************************************
* SD/MMC card controller
******************************************************************************/
static int palmtx_mci_init(struct device *dev, irq_handler_t palmtx_detect_int,
void *data)
{
int err = 0;
/* Setup an interrupt for detecting card insert/remove events */
err = request_irq(IRQ_GPIO_PALMTX_SD_DETECT_N, palmtx_detect_int,
IRQF_DISABLED | IRQF_SAMPLE_RANDOM |
IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
"SD/MMC card detect", data);
if (err) {
printk(KERN_ERR "%s: cannot request SD/MMC card detect IRQ\n",
__func__);
return err;
}
err = gpio_request(GPIO_NR_PALMTX_SD_POWER, "SD_POWER");
if (err)
goto pwr_err;
err = gpio_request(GPIO_NR_PALMTX_SD_READONLY, "SD_READONLY");
if (err)
goto ro_err;
printk(KERN_DEBUG "%s: irq registered\n", __func__);
return 0;
ro_err:
gpio_free(GPIO_NR_PALMTX_SD_POWER);
pwr_err:
free_irq(IRQ_GPIO_PALMTX_SD_DETECT_N, data);
return err;
}
static void palmtx_mci_exit(struct device *dev, void *data)
{
gpio_free(GPIO_NR_PALMTX_SD_READONLY);
gpio_free(GPIO_NR_PALMTX_SD_POWER);
free_irq(IRQ_GPIO_PALMTX_SD_DETECT_N, data);
}
static void palmtx_mci_power(struct device *dev, unsigned int vdd)
{
struct pxamci_platform_data *p_d = dev->platform_data;
gpio_set_value(GPIO_NR_PALMTX_SD_POWER, p_d->ocr_mask & (1 << vdd));
}
static int palmtx_mci_get_ro(struct device *dev)
{
return gpio_get_value(GPIO_NR_PALMTX_SD_READONLY);
}
static struct pxamci_platform_data palmtx_mci_platform_data = {
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
.setpower = palmtx_mci_power,
.get_ro = palmtx_mci_get_ro,
.init = palmtx_mci_init,
.exit = palmtx_mci_exit,
};
/******************************************************************************
* GPIO keyboard
******************************************************************************/
static unsigned int palmtx_matrix_keys[] = {
KEY(0, 0, KEY_POWER),
KEY(0, 1, KEY_F1),
KEY(0, 2, KEY_ENTER),
KEY(1, 0, KEY_F2),
KEY(1, 1, KEY_F3),
KEY(1, 2, KEY_F4),
KEY(2, 0, KEY_UP),
KEY(2, 2, KEY_DOWN),
KEY(3, 0, KEY_RIGHT),
KEY(3, 2, KEY_LEFT),
};
static struct pxa27x_keypad_platform_data palmtx_keypad_platform_data = {
.matrix_key_rows = 4,
.matrix_key_cols = 3,
.matrix_key_map = palmtx_matrix_keys,
.matrix_key_map_size = ARRAY_SIZE(palmtx_matrix_keys),
.debounce_interval = 30,
};
/******************************************************************************
* GPIO keys
******************************************************************************/
static struct gpio_keys_button palmtx_pxa_buttons[] = {
{KEY_F8, GPIO_NR_PALMTX_HOTSYNC_BUTTON_N, 1, "HotSync Button" },
};
static struct gpio_keys_platform_data palmtx_pxa_keys_data = {
.buttons = palmtx_pxa_buttons,
.nbuttons = ARRAY_SIZE(palmtx_pxa_buttons),
};
static struct platform_device palmtx_pxa_keys = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &palmtx_pxa_keys_data,
},
};
/******************************************************************************
* Backlight
******************************************************************************/
static int palmtx_backlight_init(struct device *dev)
{
int ret;
ret = gpio_request(GPIO_NR_PALMTX_BL_POWER, "BL POWER");
if (ret)
goto err;
ret = gpio_request(GPIO_NR_PALMTX_LCD_POWER, "LCD POWER");
if (ret)
goto err2;
return 0;
err2:
gpio_free(GPIO_NR_PALMTX_BL_POWER);
err:
return ret;
}
static int palmtx_backlight_notify(int brightness)
{
gpio_set_value(GPIO_NR_PALMTX_BL_POWER, brightness);
gpio_set_value(GPIO_NR_PALMTX_LCD_POWER, brightness);
return brightness;
}
static void palmtx_backlight_exit(struct device *dev)
{
gpio_free(GPIO_NR_PALMTX_BL_POWER);
gpio_free(GPIO_NR_PALMTX_LCD_POWER);
}
static struct platform_pwm_backlight_data palmtx_backlight_data = {
.pwm_id = 0,
.max_brightness = PALMTX_MAX_INTENSITY,
.dft_brightness = PALMTX_MAX_INTENSITY,
.pwm_period_ns = PALMTX_PERIOD_NS,
.init = palmtx_backlight_init,
.notify = palmtx_backlight_notify,
.exit = palmtx_backlight_exit,
};
static struct platform_device palmtx_backlight = {
.name = "pwm-backlight",
.dev = {
.parent = &pxa27x_device_pwm0.dev,
.platform_data = &palmtx_backlight_data,
},
};
/******************************************************************************
* IrDA
******************************************************************************/
static void palmtx_irda_transceiver_mode(struct device *dev, int mode)
{
gpio_set_value(GPIO_NR_PALMTX_IR_DISABLE, mode & IR_OFF);
pxa2xx_transceiver_mode(dev, mode);
}
static struct pxaficp_platform_data palmtx_ficp_platform_data = {
.transceiver_cap = IR_SIRMODE | IR_FIRMODE | IR_OFF,
.transceiver_mode = palmtx_irda_transceiver_mode,
};
/******************************************************************************
* UDC
******************************************************************************/
static void palmtx_udc_command(int cmd)
{
gpio_set_value(GPIO_NR_PALMTX_USB_POWER, !cmd);
udelay(50);
gpio_set_value(GPIO_NR_PALMTX_USB_PULLUP, !cmd);
}
static struct pxa2xx_udc_mach_info palmtx_udc_info __initdata = {
.gpio_vbus = GPIO_NR_PALMTX_USB_DETECT_N,
.gpio_vbus_inverted = 1,
.udc_command = palmtx_udc_command,
};
/******************************************************************************
* Power supply
******************************************************************************/
static int power_supply_init(struct device *dev)
{
int ret;
ret = gpio_request(GPIO_NR_PALMTX_POWER_DETECT, "CABLE_STATE_AC");
if (ret)
goto err_cs_ac;
ret = gpio_request(GPIO_NR_PALMTX_USB_DETECT_N, "CABLE_STATE_USB");
if (ret)
goto err_cs_usb;
return 0;
err_cs_usb:
gpio_free(GPIO_NR_PALMTX_POWER_DETECT);
err_cs_ac:
return ret;
}
static int palmtx_is_ac_online(void)
{
return gpio_get_value(GPIO_NR_PALMTX_POWER_DETECT);
}
static int palmtx_is_usb_online(void)
{
return !gpio_get_value(GPIO_NR_PALMTX_USB_DETECT_N);
}
static void power_supply_exit(struct device *dev)
{
gpio_free(GPIO_NR_PALMTX_USB_DETECT_N);
gpio_free(GPIO_NR_PALMTX_POWER_DETECT);
}
static char *palmtx_supplicants[] = {
"main-battery",
};
static struct pda_power_pdata power_supply_info = {
.init = power_supply_init,
.is_ac_online = palmtx_is_ac_online,
.is_usb_online = palmtx_is_usb_online,
.exit = power_supply_exit,
.supplied_to = palmtx_supplicants,
.num_supplicants = ARRAY_SIZE(palmtx_supplicants),
};
static struct platform_device power_supply = {
.name = "pda-power",
.id = -1,
.dev = {
.platform_data = &power_supply_info,
},
};
/******************************************************************************
* Framebuffer
******************************************************************************/
static struct pxafb_mode_info palmtx_lcd_modes[] = {
{
.pixclock = 57692,
.xres = 320,
.yres = 480,
.bpp = 16,
.left_margin = 32,
.right_margin = 1,
.upper_margin = 7,
.lower_margin = 1,
.hsync_len = 4,
.vsync_len = 1,
},
};
static struct pxafb_mach_info palmtx_lcd_screen = {
.modes = palmtx_lcd_modes,
.num_modes = ARRAY_SIZE(palmtx_lcd_modes),
.lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
};
/******************************************************************************
* Machine init
******************************************************************************/
static struct platform_device *devices[] __initdata = {
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
&palmtx_pxa_keys,
#endif
&palmtx_backlight,
&power_supply,
};
static struct map_desc palmtx_io_desc[] __initdata = {
{
.virtual = PALMTX_PCMCIA_VIRT,
.pfn = __phys_to_pfn(PALMTX_PCMCIA_PHYS),
.length = PALMTX_PCMCIA_SIZE,
.type = MT_DEVICE
},
};
static void __init palmtx_map_io(void)
{
pxa_map_io();
iotable_init(palmtx_io_desc, ARRAY_SIZE(palmtx_io_desc));
}
static void __init palmtx_init(void)
{
pxa2xx_mfp_config(ARRAY_AND_SIZE(palmtx_pin_config));
set_pxa_fb_info(&palmtx_lcd_screen);
pxa_set_mci_info(&palmtx_mci_platform_data);
pxa_set_udc_info(&palmtx_udc_info);
pxa_set_ac97_info(NULL);
pxa_set_ficp_info(&palmtx_ficp_platform_data);
pxa_set_keypad_info(&palmtx_keypad_platform_data);
platform_add_devices(devices, ARRAY_SIZE(devices));
}
MACHINE_START(PALMTX, "Palm T|X")
.phys_io = PALMTX_PHYS_IO_START,
.io_pg_offst = io_p2v(0x40000000),
.boot_params = 0xa0000100,
.map_io = palmtx_map_io,
.init_irq = pxa27x_init_irq,
.timer = &pxa_timer,
.init_machine = palmtx_init
MACHINE_END
arch/arm/mach-pxa/pcm027.c
View file @ 30d38542
......@@ -24,7 +24,9 @@
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/spi/spi.h>
#include <linux/spi/max7301.h>
#include <linux/leds.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/arch/hardware.h>
......@@ -108,6 +110,32 @@ static struct platform_device smc91x_device = {
.resource = smc91x_resources,
};
/*
* SPI host and devices
*/
static struct pxa2xx_spi_master pxa_ssp_master_info = {
.num_chipselect = 1,
};
static struct max7301_platform_data max7301_info = {
.base = -1,
};
/* bus_num must match id in pxa2xx_set_spi_info() call */
static struct spi_board_info spi_board_info[] __initdata = {
{
.modalias = "max7301",
.platform_data = &max7301_info,
.max_speed_hz = 13000000,
.bus_num = 1,
.chip_select = 0,
.mode = SPI_MODE_0,
},
};
/*
* NOR flash
*/
static struct physmap_flash_data pcm027_flash_data = {
.width = 4,
};
......@@ -190,6 +218,9 @@ static void __init pcm027_init(void)
#ifdef CONFIG_MACH_PCM990_BASEBOARD
pcm990_baseboard_init();
#endif
pxa2xx_set_spi_info(1, &pxa_ssp_master_info);
spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
}
static void __init pcm027_map_io(void)
......
arch/arm/mach-pxa/pcm990-baseboard.c
View file @ 30d38542
......@@ -33,14 +33,30 @@
#include <asm/arch/camera.h>
#include <asm/mach/map.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/audio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/ohci.h>
#include <asm/arch/pcm990_baseboard.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/mfp-pxa27x.h>
#include "devices.h"
#include "generic.h"
static unsigned long pcm990_pin_config[] __initdata = {
/* MMC */
GPIO32_MMC_CLK,
GPIO112_MMC_CMD,
GPIO92_MMC_DAT_0,
GPIO109_MMC_DAT_1,
GPIO110_MMC_DAT_2,
GPIO111_MMC_DAT_3,
/* USB */
GPIO88_USBH1_PWR,
GPIO89_USBH1_PEN,
/* PWM0 */
GPIO16_PWM0_OUT,
};
/*
* pcm990_lcd_power - control power supply to the LCD
......@@ -277,16 +293,6 @@ static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int,
{
int err;
/*
* enable GPIO for PXA27x MMC controller
*/
pxa_gpio_mode(GPIO32_MMCCLK_MD);
pxa_gpio_mode(GPIO112_MMCCMD_MD);
pxa_gpio_mode(GPIO92_MMCDAT0_MD);
pxa_gpio_mode(GPIO109_MMCDAT1_MD);
pxa_gpio_mode(GPIO110_MMCDAT2_MD);
pxa_gpio_mode(GPIO111_MMCDAT3_MD);
err = request_irq(PCM027_MMCDET_IRQ, mci_detect_int, IRQF_DISABLED,
"MMC card detect", data);
if (err)
......@@ -333,8 +339,6 @@ static struct pxamci_platform_data pcm990_mci_platform_data = {
*/
static int pcm990_ohci_init(struct device *dev)
{
pxa_gpio_mode(PCM990_USB_OVERCURRENT);
pxa_gpio_mode(PCM990_USB_PWR_EN);
/*
* disable USB port 2 and 3
* power sense is active low
......@@ -361,23 +365,27 @@ static struct pxaohci_platform_data pcm990_ohci_platform_data = {
* PXA27x Camera specific stuff
*/
#if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE)
static unsigned long pcm990_camera_pin_config[] = {
/* CIF */
GPIO98_CIF_DD_0,
GPIO105_CIF_DD_1,
GPIO104_CIF_DD_2,
GPIO103_CIF_DD_3,
GPIO95_CIF_DD_4,
GPIO94_CIF_DD_5,
GPIO93_CIF_DD_6,
GPIO108_CIF_DD_7,
GPIO107_CIF_DD_8,
GPIO106_CIF_DD_9,
GPIO42_CIF_MCLK,
GPIO45_CIF_PCLK,
GPIO43_CIF_FV,
GPIO44_CIF_LV,
};
static int pcm990_pxacamera_init(struct device *dev)
{
pxa_gpio_mode(GPIO98_CIF_DD_0_MD);
pxa_gpio_mode(GPIO105_CIF_DD_1_MD);
pxa_gpio_mode(GPIO104_CIF_DD_2_MD);
pxa_gpio_mode(GPIO103_CIF_DD_3_MD);
pxa_gpio_mode(GPIO95_CIF_DD_4_MD);
pxa_gpio_mode(GPIO94_CIF_DD_5_MD);
pxa_gpio_mode(GPIO93_CIF_DD_6_MD);
pxa_gpio_mode(GPIO108_CIF_DD_7_MD);
pxa_gpio_mode(GPIO107_CIF_DD_8_MD);
pxa_gpio_mode(GPIO106_CIF_DD_9_MD);
pxa_gpio_mode(GPIO42_CIF_MCLK_MD);
pxa_gpio_mode(GPIO45_CIF_PCLK_MD);
pxa_gpio_mode(GPIO43_CIF_FV_MD);
pxa_gpio_mode(GPIO44_CIF_LV_MD);
pxa2xx_mfp_config(ARRAY_AND_SIZE(pcm990_camera_pin_config));
return 0;
}
......@@ -449,8 +457,10 @@ static struct map_desc pcm990_io_desc[] __initdata = {
*/
void __init pcm990_baseboard_init(void)
{
pxa2xx_mfp_config(ARRAY_AND_SIZE(pcm990_pin_config));
/* register CPLD access */
iotable_init(pcm990_io_desc, ARRAY_SIZE(pcm990_io_desc));
iotable_init(ARRAY_AND_SIZE(pcm990_io_desc));
/* register CPLD's IRQ controller */
pcm990_init_irq();
......@@ -458,7 +468,6 @@ void __init pcm990_baseboard_init(void)
#ifndef CONFIG_PCM990_DISPLAY_NONE
set_pxa_fb_info(&pcm990_fbinfo);
#endif
pxa_gpio_mode(GPIO16_PWM0_MD);
platform_device_register(&pcm990_backlight_device);
/* MMC */
......@@ -473,9 +482,8 @@ void __init pcm990_baseboard_init(void)
#if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE)
pxa_set_camera_info(&pcm990_pxacamera_platform_data);
i2c_register_board_info(0, pcm990_i2c_devices,
ARRAY_SIZE(pcm990_i2c_devices));
i2c_register_board_info(0, ARRAY_AND_SIZE(pcm990_i2c_devices));
#endif
printk(KERN_INFO"PCM-990 Evaluation baseboard initialized\n");
printk(KERN_INFO "PCM-990 Evaluation baseboard initialized\n");
}
arch/arm/mach-pxa/poodle.c
View file @ 30d38542
......@@ -267,6 +267,7 @@ static void poodle_irda_transceiver_mode(struct device *dev, int mode)
} else {
GPCR(POODLE_GPIO_IR_ON) = GPIO_bit(POODLE_GPIO_IR_ON);
}
pxa2xx_transceiver_mode(dev, mode);
}
static struct pxaficp_platform_data poodle_ficp_platform_data = {
......
arch/arm/mach-pxa/pxa25x.c
View file @ 30d38542
......@@ -109,6 +109,52 @@ static const struct clkops clk_pxa25x_lcd_ops = {
.getrate = clk_pxa25x_lcd_getrate,
};
static unsigned long gpio12_config_32k[] = {
GPIO12_32KHz,
};
static unsigned long gpio12_config_gpio[] = {
GPIO12_GPIO,
};
static void clk_gpio12_enable(struct clk *clk)
{
pxa2xx_mfp_config(gpio12_config_32k, 1);
}
static void clk_gpio12_disable(struct clk *clk)
{
pxa2xx_mfp_config(gpio12_config_gpio, 1);
}
static const struct clkops clk_pxa25x_gpio12_ops = {
.enable = clk_gpio12_enable,
.disable = clk_gpio12_disable,
};
static unsigned long gpio11_config_3m6[] = {
GPIO11_3_6MHz,
};
static unsigned long gpio11_config_gpio[] = {
GPIO11_GPIO,
};
static void clk_gpio11_enable(struct clk *clk)
{
pxa2xx_mfp_config(gpio11_config_3m6, 1);
}
static void clk_gpio11_disable(struct clk *clk)
{
pxa2xx_mfp_config(gpio11_config_gpio, 1);
}
static const struct clkops clk_pxa25x_gpio11_ops = {
.enable = clk_gpio11_enable,
.disable = clk_gpio11_disable,
};
/*
* 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
* 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
......@@ -128,6 +174,8 @@ static struct clk pxa25x_clks[] = {
INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL),
INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa25x_device_udc.dev),
INIT_CLK("GPIO11_CLK", &clk_pxa25x_gpio11_ops, 3686400, 0, NULL),
INIT_CLK("GPIO12_CLK", &clk_pxa25x_gpio12_ops, 32768, 0, NULL),
INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),
......@@ -145,7 +193,10 @@ static struct clk pxa25x_clks[] = {
INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
};
static struct clk gpio7_clk = INIT_CKOTHER("GPIO7_CK", &pxa25x_clks[4], NULL);
static struct clk pxa2xx_clk_aliases[] = {
INIT_CKOTHER("GPIO7_CLK", &pxa25x_clks[4], NULL),
INIT_CKOTHER("SA1111_CLK", &pxa25x_clks[5], NULL),
};
#ifdef CONFIG_PM
......@@ -293,7 +344,7 @@ static int __init pxa25x_init(void)
int i, ret = 0;
/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
if (cpu_is_pxa25x())
if (cpu_is_pxa255())
clks_register(&pxa25x_hwuart_clk, 1);
if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
......@@ -317,10 +368,10 @@ static int __init pxa25x_init(void)
}
/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
if (cpu_is_pxa25x())
if (cpu_is_pxa255())
ret = platform_device_register(&pxa_device_hwuart);
clks_register(&gpio7_clk, 1);
clks_register(pxa2xx_clk_aliases, ARRAY_SIZE(pxa2xx_clk_aliases));
return ret;
}
......
arch/arm/mach-pxa/pxa300.c
View file @ 30d38542
......@@ -15,10 +15,16 @@
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <asm/hardware.h>
#include <asm/arch/pxa3xx-regs.h>
#include <asm/arch/mfp-pxa300.h>
#include "generic.h"
#include "devices.h"
#include "clock.h"
static struct pxa3xx_mfp_addr_map pxa300_mfp_addr_map[] __initdata = {
MFP_ADDR_X(GPIO0, GPIO2, 0x00b4),
......@@ -79,15 +85,26 @@ static struct pxa3xx_mfp_addr_map pxa310_mfp_addr_map[] __initdata = {
MFP_ADDR_END,
};
static struct clk common_clks[] = {
PXA3xx_CKEN("NANDCLK", NAND, 156000000, 0, &pxa3xx_device_nand.dev),
};
static struct clk pxa310_clks[] = {
PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev),
};
static int __init pxa300_init(void)
{
if (cpu_is_pxa300() || cpu_is_pxa310()) {
pxa3xx_init_mfp();
pxa3xx_mfp_init_addr(pxa300_mfp_addr_map);
clks_register(ARRAY_AND_SIZE(common_clks));
}
if (cpu_is_pxa310())
if (cpu_is_pxa310()) {
pxa3xx_mfp_init_addr(pxa310_mfp_addr_map);
clks_register(ARRAY_AND_SIZE(pxa310_clks));
}
return 0;
}
......
arch/arm/mach-pxa/pxa320.c
View file @ 30d38542
......@@ -15,11 +15,17 @@
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <asm/hardware.h>
#include <asm/arch/mfp.h>
#include <asm/arch/pxa3xx-regs.h>
#include <asm/arch/mfp-pxa320.h>
#include "generic.h"
#include "devices.h"
#include "clock.h"
static struct pxa3xx_mfp_addr_map pxa320_mfp_addr_map[] __initdata = {
MFP_ADDR_X(GPIO0, GPIO4, 0x0124),
......@@ -74,16 +80,17 @@ static struct pxa3xx_mfp_addr_map pxa320_mfp_addr_map[] __initdata = {
MFP_ADDR_END,
};
static void __init pxa320_init_mfp(void)
{
pxa3xx_init_mfp();
pxa3xx_mfp_init_addr(pxa320_mfp_addr_map);
}
static struct clk pxa320_clks[] = {
PXA3xx_CKEN("NANDCLK", NAND, 104000000, 0, &pxa3xx_device_nand.dev),
};
static int __init pxa320_init(void)
{
if (cpu_is_pxa320())
pxa320_init_mfp();
if (cpu_is_pxa320()) {
pxa3xx_init_mfp();
pxa3xx_mfp_init_addr(pxa320_mfp_addr_map);
clks_register(ARRAY_AND_SIZE(pxa320_clks));
}
return 0;
}
......
arch/arm/mach-pxa/pxa3xx.c
View file @ 30d38542
......@@ -144,7 +144,7 @@ static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
return hsio_clk;
}
static void clk_pxa3xx_cken_enable(struct clk *clk)
void clk_pxa3xx_cken_enable(struct clk *clk)
{
unsigned long mask = 1ul << (clk->cken & 0x1f);
......@@ -154,7 +154,7 @@ static void clk_pxa3xx_cken_enable(struct clk *clk)
CKENB |= mask;
}
static void clk_pxa3xx_cken_disable(struct clk *clk)
void clk_pxa3xx_cken_disable(struct clk *clk)
{
unsigned long mask = 1ul << (clk->cken & 0x1f);
......@@ -164,7 +164,7 @@ static void clk_pxa3xx_cken_disable(struct clk *clk)
CKENB &= ~mask;
}
static const struct clkops clk_pxa3xx_cken_ops = {
const struct clkops clk_pxa3xx_cken_ops = {
.enable = clk_pxa3xx_cken_enable,
.disable = clk_pxa3xx_cken_disable,
};
......@@ -196,24 +196,6 @@ static const struct clkops clk_pout_ops = {
.disable = clk_pout_disable,
};
#define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \
{ \
.name = _name, \
.dev = _dev, \
.ops = &clk_pxa3xx_cken_ops, \
.rate = _rate, \
.cken = CKEN_##_cken, \
.delay = _delay, \
}
#define PXA3xx_CK(_name, _cken, _ops, _dev) \
{ \
.name = _name, \
.dev = _dev, \
.ops = _ops, \
.cken = CKEN_##_cken, \
}
static struct clk pxa3xx_clks[] = {
{
.name = "CLK_POUT",
......@@ -244,7 +226,6 @@ static struct clk pxa3xx_clks[] = {
PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev),
PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev),
PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev),
};
#ifdef CONFIG_PM
......
arch/arm/mach-pxa/pxa930.c 0 → 100644
View file @ 30d38542
/*
* linux/arch/arm/mach-pxa/pxa930.c
*
* Code specific to PXA930
*
* Copyright (C) 2007-2008 Marvell Internation Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/dma-mapping.h>
#include <asm/hardware.h>
#include <asm/arch/mfp-pxa930.h>
static struct pxa3xx_mfp_addr_map pxa930_mfp_addr_map[] __initdata = {
MFP_ADDR(GPIO0, 0x02e0),
MFP_ADDR(GPIO1, 0x02dc),
MFP_ADDR(GPIO2, 0x02e8),
MFP_ADDR(GPIO3, 0x02d8),
MFP_ADDR(GPIO4, 0x02e4),
MFP_ADDR(GPIO5, 0x02ec),
MFP_ADDR(GPIO6, 0x02f8),
MFP_ADDR(GPIO7, 0x02fc),
MFP_ADDR(GPIO8, 0x0300),
MFP_ADDR(GPIO9, 0x02d4),
MFP_ADDR(GPIO10, 0x02f4),
MFP_ADDR(GPIO11, 0x02f0),
MFP_ADDR(GPIO12, 0x0304),
MFP_ADDR(GPIO13, 0x0310),
MFP_ADDR(GPIO14, 0x0308),
MFP_ADDR(GPIO15, 0x030c),
MFP_ADDR(GPIO16, 0x04e8),
MFP_ADDR(GPIO17, 0x04f4),
MFP_ADDR(GPIO18, 0x04f8),
MFP_ADDR(GPIO19, 0x04fc),
MFP_ADDR(GPIO20, 0x0518),
MFP_ADDR(GPIO21, 0x051c),
MFP_ADDR(GPIO22, 0x04ec),
MFP_ADDR(GPIO23, 0x0500),
MFP_ADDR(GPIO24, 0x04f0),
MFP_ADDR(GPIO25, 0x0504),
MFP_ADDR(GPIO26, 0x0510),
MFP_ADDR(GPIO27, 0x0514),
MFP_ADDR(GPIO28, 0x0520),
MFP_ADDR(GPIO29, 0x0600),
MFP_ADDR(GPIO30, 0x0618),
MFP_ADDR(GPIO31, 0x0610),
MFP_ADDR(GPIO32, 0x060c),
MFP_ADDR(GPIO33, 0x061c),
MFP_ADDR(GPIO34, 0x0620),
MFP_ADDR(GPIO35, 0x0628),
MFP_ADDR(GPIO36, 0x062c),
MFP_ADDR(GPIO37, 0x0630),
MFP_ADDR(GPIO38, 0x0634),
MFP_ADDR(GPIO39, 0x0638),
MFP_ADDR(GPIO40, 0x063c),
MFP_ADDR(GPIO41, 0x0614),
MFP_ADDR(GPIO42, 0x0624),
MFP_ADDR(GPIO43, 0x0608),
MFP_ADDR(GPIO44, 0x0604),
MFP_ADDR(GPIO45, 0x050c),
MFP_ADDR(GPIO46, 0x0508),
MFP_ADDR(GPIO47, 0x02bc),
MFP_ADDR(GPIO48, 0x02b4),
MFP_ADDR(GPIO49, 0x02b8),
MFP_ADDR(GPIO50, 0x02c8),
MFP_ADDR(GPIO51, 0x02c0),
MFP_ADDR(GPIO52, 0x02c4),
MFP_ADDR(GPIO53, 0x02d0),
MFP_ADDR(GPIO54, 0x02cc),
MFP_ADDR(GPIO55, 0x029c),
MFP_ADDR(GPIO56, 0x02a0),
MFP_ADDR(GPIO57, 0x0294),
MFP_ADDR(GPIO58, 0x0298),
MFP_ADDR(GPIO59, 0x02a4),
MFP_ADDR(GPIO60, 0x02a8),
MFP_ADDR(GPIO61, 0x02b0),
MFP_ADDR(GPIO62, 0x02ac),
MFP_ADDR(GPIO63, 0x0640),
MFP_ADDR(GPIO64, 0x065c),
MFP_ADDR(GPIO65, 0x0648),
MFP_ADDR(GPIO66, 0x0644),
MFP_ADDR(GPIO67, 0x0674),
MFP_ADDR(GPIO68, 0x0658),
MFP_ADDR(GPIO69, 0x0654),
MFP_ADDR(GPIO70, 0x0660),
MFP_ADDR(GPIO71, 0x0668),
MFP_ADDR(GPIO72, 0x0664),
MFP_ADDR(GPIO73, 0x0650),
MFP_ADDR(GPIO74, 0x066c),
MFP_ADDR(GPIO75, 0x064c),
MFP_ADDR(GPIO76, 0x0670),
MFP_ADDR(GPIO77, 0x0678),
MFP_ADDR(GPIO78, 0x067c),
MFP_ADDR(GPIO79, 0x0694),
MFP_ADDR(GPIO80, 0x069c),
MFP_ADDR(GPIO81, 0x06a0),
MFP_ADDR(GPIO82, 0x06a4),
MFP_ADDR(GPIO83, 0x0698),
MFP_ADDR(GPIO84, 0x06bc),
MFP_ADDR(GPIO85, 0x06b4),
MFP_ADDR(GPIO86, 0x06b0),
MFP_ADDR(GPIO87, 0x06c0),
MFP_ADDR(GPIO88, 0x06c4),
MFP_ADDR(GPIO89, 0x06ac),
MFP_ADDR(GPIO90, 0x0680),
MFP_ADDR(GPIO91, 0x0684),
MFP_ADDR(GPIO92, 0x0688),
MFP_ADDR(GPIO93, 0x0690),
MFP_ADDR(GPIO94, 0x068c),
MFP_ADDR(GPIO95, 0x06a8),
MFP_ADDR(GPIO96, 0x06b8),
MFP_ADDR(GPIO97, 0x0410),
MFP_ADDR(GPIO98, 0x0418),
MFP_ADDR(GPIO99, 0x041c),
MFP_ADDR(GPIO100, 0x0414),
MFP_ADDR(GPIO101, 0x0408),
MFP_ADDR(GPIO102, 0x0324),
MFP_ADDR(GPIO103, 0x040c),
MFP_ADDR(GPIO104, 0x0400),
MFP_ADDR(GPIO105, 0x0328),
MFP_ADDR(GPIO106, 0x0404),
MFP_ADDR(nXCVREN, 0x0204),
MFP_ADDR(DF_CLE_nOE, 0x020c),
MFP_ADDR(DF_nADV1_ALE, 0x0218),
MFP_ADDR(DF_SCLK_E, 0x0214),
MFP_ADDR(DF_SCLK_S, 0x0210),
MFP_ADDR(nBE0, 0x021c),
MFP_ADDR(nBE1, 0x0220),
MFP_ADDR(DF_nADV2_ALE, 0x0224),
MFP_ADDR(DF_INT_RnB, 0x0228),
MFP_ADDR(DF_nCS0, 0x022c),
MFP_ADDR(DF_nCS1, 0x0230),
MFP_ADDR(nLUA, 0x0254),
MFP_ADDR(nLLA, 0x0258),
MFP_ADDR(DF_nWE, 0x0234),
MFP_ADDR(DF_nRE_nOE, 0x0238),
MFP_ADDR(DF_ADDR0, 0x024c),
MFP_ADDR(DF_ADDR1, 0x0250),
MFP_ADDR(DF_ADDR2, 0x025c),
MFP_ADDR(DF_ADDR3, 0x0260),
MFP_ADDR(DF_IO0, 0x023c),
MFP_ADDR(DF_IO1, 0x0240),
MFP_ADDR(DF_IO2, 0x0244),
MFP_ADDR(DF_IO3, 0x0248),
MFP_ADDR(DF_IO4, 0x0264),
MFP_ADDR(DF_IO5, 0x0268),
MFP_ADDR(DF_IO6, 0x026c),
MFP_ADDR(DF_IO7, 0x0270),
MFP_ADDR(DF_IO8, 0x0274),
MFP_ADDR(DF_IO9, 0x0278),
MFP_ADDR(DF_IO10, 0x027c),
MFP_ADDR(DF_IO11, 0x0280),
MFP_ADDR(DF_IO12, 0x0284),
MFP_ADDR(DF_IO13, 0x0288),
MFP_ADDR(DF_IO14, 0x028c),
MFP_ADDR(DF_IO15, 0x0290),
MFP_ADDR(GSIM_UIO, 0x0314),
MFP_ADDR(GSIM_UCLK, 0x0318),
MFP_ADDR(GSIM_UDET, 0x031c),
MFP_ADDR(GSIM_nURST, 0x0320),
MFP_ADDR(PMIC_INT, 0x06c8),
MFP_ADDR(RDY, 0x0200),
MFP_ADDR_END,
};
static int __init pxa930_init(void)
{
if (cpu_is_pxa930()) {
pxa3xx_init_mfp();
pxa3xx_mfp_init_addr(pxa930_mfp_addr_map);
}
return 0;
}
core_initcall(pxa930_init);
arch/arm/mach-pxa/reset.c 0 → 100644
View file @ 30d38542
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <asm/io.h>
#include <asm/proc-fns.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
static void do_hw_reset(void);
static int reset_gpio = -1;
int init_gpio_reset(int gpio)
{
int rc;
rc = gpio_request(gpio, "reset generator");
if (rc) {
printk(KERN_ERR "Can't request reset_gpio\n");
goto out;
}
rc = gpio_direction_input(gpio);
if (rc) {
printk(KERN_ERR "Can't configure reset_gpio for input\n");
gpio_free(gpio);
goto out;
}
out:
if (!rc)
reset_gpio = gpio;
return rc;
}
/*
* Trigger GPIO reset.
* This covers various types of logic connecting gpio pin
* to RESET pins (nRESET or GPIO_RESET):
*/
static void do_gpio_reset(void)
{
BUG_ON(reset_gpio == -1);
/* drive it low */
gpio_direction_output(reset_gpio, 0);
mdelay(2);
/* rising edge or drive high */
gpio_set_value(reset_gpio, 1);
mdelay(2);
/* falling edge */
gpio_set_value(reset_gpio, 0);
/* give it some time */
mdelay(10);
WARN_ON(1);
/* fallback */
do_hw_reset();
}
static void do_hw_reset(void)
{
/* Initialize the watchdog and let it fire */
OWER = OWER_WME;
OSSR = OSSR_M3;
OSMR3 = OSCR + 368640; /* ... in 100 ms */
}
void arch_reset(char mode)
{
if (cpu_is_pxa2xx())
RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
switch (mode) {
case 's':
/* Jump into ROM at address 0 */
cpu_reset(0);
break;
case 'h':
do_hw_reset();
break;
case 'g':
do_gpio_reset();
break;
}
}
arch/arm/mach-pxa/saar.c 0 → 100644
View file @ 30d38542
/*
* linux/arch/arm/mach-pxa/saar.c
*
* Support for the Marvell PXA930 Handheld Platform (aka SAAR)
*
* Copyright (C) 2007-2008 Marvell International Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/smc91x.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/hardware.h>
#include <asm/arch/pxa3xx-regs.h>
#include <asm/arch/mfp-pxa930.h>
#include "devices.h"
#include "generic.h"
/* SAAR MFP configurations */
static mfp_cfg_t saar_mfp_cfg[] __initdata = {
/* Ethernet */
DF_nCS1_nCS3,
GPIO97_GPIO,
};
#define SAAR_ETH_PHYS (0x14000000)
static struct resource smc91x_resources[] = {
[0] = {
.start = (SAAR_ETH_PHYS + 0x300),
.end = (SAAR_ETH_PHYS + 0xfffff),
.flags = IORESOURCE_MEM,
},
[1] = {
.start = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO97)),
.end = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO97)),
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
}
};
static struct smc91x_platdata saar_smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_USE_DMA,
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
.dev = {
.platform_data = &saar_smc91x_info,
},
};
static void __init saar_init(void)
{
/* initialize MFP configurations */
pxa3xx_mfp_config(ARRAY_AND_SIZE(saar_mfp_cfg));
platform_device_register(&smc91x_device);
}
MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)")
/* Maintainer: Eric Miao <eric.miao@marvell.com> */
.phys_io = 0x40000000,
.boot_params = 0xa0000100,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.map_io = pxa_map_io,
.init_irq = pxa3xx_init_irq,
.timer = &pxa_timer,
.init_machine = saar_init,
MACHINE_END
arch/arm/mach-pxa/spitz.c
View file @ 30d38542
......@@ -38,6 +38,7 @@
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/pxa27x-udc.h>
#include <asm/arch/irda.h>
#include <asm/arch/mmc.h>
#include <asm/arch/ohci.h>
......@@ -450,6 +451,7 @@ static void spitz_irda_transceiver_mode(struct device *dev, int mode)
set_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_IR_ON);
else
reset_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_IR_ON);
pxa2xx_transceiver_mode(dev, mode);
}
#ifdef CONFIG_MACH_AKITA
......@@ -459,6 +461,7 @@ static void akita_irda_transceiver_mode(struct device *dev, int mode)
akita_set_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_IR_ON);
else
akita_reset_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_IR_ON);
pxa2xx_transceiver_mode(dev, mode);
}
#endif
......@@ -529,11 +532,7 @@ static struct platform_device *devices[] __initdata = {
static void spitz_poweroff(void)
{
pxa_gpio_mode(SPITZ_GPIO_ON_RESET | GPIO_OUT);
GPSR(SPITZ_GPIO_ON_RESET) = GPIO_bit(SPITZ_GPIO_ON_RESET);
mdelay(1000);
arm_machine_restart('h');
arm_machine_restart('g');
}
static void spitz_restart(char mode)
......@@ -547,6 +546,7 @@ static void spitz_restart(char mode)
static void __init common_init(void)
{
init_gpio_reset(SPITZ_GPIO_ON_RESET);
pm_power_off = spitz_poweroff;
arm_pm_restart = spitz_restart;
......
arch/arm/mach-pxa/ssp.c
View file @ 30d38542
......@@ -14,13 +14,6 @@
* IO-based SSP applications and allows easy port setup for DMA access.
*
* Author: Liam Girdwood <liam.girdwood@wolfsonmicro.com>
*
* Revision history:
* 22nd Aug 2003 Initial version.
* 20th Dec 2004 Added ssp_config for changing port config without
* closing the port.
* 4th Aug 2005 Added option to disable irq handler registration and
* cleaned up irq and clock detection.
*/
#include <linux/module.h>
......@@ -285,7 +278,7 @@ int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags)
goto out_region;
dev->irq = ssp->irq;
} else
dev->irq = 0;
dev->irq = NO_IRQ;
/* turn on SSP port clock */
clk_enable(ssp->clk);
......@@ -306,7 +299,8 @@ void ssp_exit(struct ssp_dev *dev)
struct ssp_device *ssp = dev->ssp;
ssp_disable(dev);
free_irq(dev->irq, dev);
if (dev->irq != NO_IRQ)
free_irq(dev->irq, dev);
clk_disable(ssp->clk);
ssp_free(ssp);
}
......@@ -360,6 +354,7 @@ static int __devinit ssp_probe(struct platform_device *pdev, int type)
dev_err(&pdev->dev, "failed to allocate memory");
return -ENOMEM;
}
ssp->pdev = pdev;
ssp->clk = clk_get(&pdev->dev, "SSPCLK");
if (IS_ERR(ssp->clk)) {
......
arch/arm/mach-pxa/tavorevb.c 0 → 100644
View file @ 30d38542
/*
* linux/arch/arm/mach-pxa/tavorevb.c
*
* Support for the Marvell PXA930 Evaluation Board
*
* Copyright (C) 2007-2008 Marvell International Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/smc91x.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/hardware.h>
#include <asm/arch/pxa3xx-regs.h>
#include <asm/arch/mfp-pxa930.h>
#include "devices.h"
#include "generic.h"
/* Tavor EVB MFP configurations */
static mfp_cfg_t tavorevb_mfp_cfg[] __initdata = {
/* Ethernet */
DF_nCS1_nCS3,
GPIO47_GPIO,
};
#define TAVOREVB_ETH_PHYS (0x14000000)
static struct resource smc91x_resources[] = {
[0] = {
.start = (TAVOREVB_ETH_PHYS + 0x300),
.end = (TAVOREVB_ETH_PHYS + 0xfffff),
.flags = IORESOURCE_MEM,
},
[1] = {
.start = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO47)),
.end = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO47)),
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
}
};
static struct smc91x_platdata tavorevb_smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_USE_DMA,
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
.dev = {
.platform_data = &tavorevb_smc91x_info,
},
};
static void __init tavorevb_init(void)
{
/* initialize MFP configurations */
pxa3xx_mfp_config(ARRAY_AND_SIZE(tavorevb_mfp_cfg));
platform_device_register(&smc91x_device);
}
MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)")
/* Maintainer: Eric Miao <eric.miao@marvell.com> */
.phys_io = 0x40000000,
.boot_params = 0xa0000100,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.map_io = pxa_map_io,
.init_irq = pxa3xx_init_irq,
.timer = &pxa_timer,
.init_machine = tavorevb_init,
MACHINE_END
arch/arm/mach-pxa/tosa-bt.c 0 → 100644
View file @ 30d38542
/*
* Bluetooth built-in chip control
*
* Copyright (c) 2008 Dmitry Baryshkov
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/rfkill.h>
#include <asm/arch/tosa_bt.h>
static void tosa_bt_on(struct tosa_bt_data *data)
{
gpio_set_value(data->gpio_reset, 0);
gpio_set_value(data->gpio_pwr, 1);
gpio_set_value(data->gpio_reset, 1);
mdelay(20);
gpio_set_value(data->gpio_reset, 0);
}
static void tosa_bt_off(struct tosa_bt_data *data)
{
gpio_set_value(data->gpio_reset, 1);
mdelay(10);
gpio_set_value(data->gpio_pwr, 0);
gpio_set_value(data->gpio_reset, 0);
}
static int tosa_bt_toggle_radio(void *data, enum rfkill_state state)
{
pr_info("BT_RADIO going: %s\n",
state == RFKILL_STATE_ON ? "on" : "off");
if (state == RFKILL_STATE_ON) {
pr_info("TOSA_BT: going ON\n");
tosa_bt_on(data);
} else {
pr_info("TOSA_BT: going OFF\n");
tosa_bt_off(data);
}
return 0;
}
static int tosa_bt_probe(struct platform_device *dev)
{
int rc;
struct rfkill *rfk;
struct tosa_bt_data *data = dev->dev.platform_data;
rc = gpio_request(data->gpio_reset, "Bluetooth reset");
if (rc)
goto err_reset;
rc = gpio_direction_output(data->gpio_reset, 0);
if (rc)
goto err_reset_dir;
rc = gpio_request(data->gpio_pwr, "Bluetooth power");
if (rc)
goto err_pwr;
rc = gpio_direction_output(data->gpio_pwr, 0);
if (rc)
goto err_pwr_dir;
rfk = rfkill_allocate(&dev->dev, RFKILL_TYPE_BLUETOOTH);
if (!rfk) {
rc = -ENOMEM;
goto err_rfk_alloc;
}
rfk->name = "tosa-bt";
rfk->toggle_radio = tosa_bt_toggle_radio;
rfk->data = data;
#ifdef CONFIG_RFKILL_LEDS
rfk->led_trigger.name = "tosa-bt";
#endif
rc = rfkill_register(rfk);
if (rc)
goto err_rfkill;
platform_set_drvdata(dev, rfk);
return 0;
err_rfkill:
if (rfk)
rfkill_free(rfk);
rfk = NULL;
err_rfk_alloc:
tosa_bt_off(data);
err_pwr_dir:
gpio_free(data->gpio_pwr);
err_pwr:
err_reset_dir:
gpio_free(data->gpio_reset);
err_reset:
return rc;
}
static int __devexit tosa_bt_remove(struct platform_device *dev)
{
struct tosa_bt_data *data = dev->dev.platform_data;
struct rfkill *rfk = platform_get_drvdata(dev);
platform_set_drvdata(dev, NULL);
if (rfk)
rfkill_unregister(rfk);
rfk = NULL;
tosa_bt_off(data);
gpio_free(data->gpio_pwr);
gpio_free(data->gpio_reset);
return 0;
}
static struct platform_driver tosa_bt_driver = {
.probe = tosa_bt_probe,
.remove = __devexit_p(tosa_bt_remove),
.driver = {
.name = "tosa-bt",
.owner = THIS_MODULE,
},
};
static int __init tosa_bt_init(void)
{
return platform_driver_register(&tosa_bt_driver);
}
static void __exit tosa_bt_exit(void)
{
platform_driver_unregister(&tosa_bt_driver);
}
module_init(tosa_bt_init);
module_exit(tosa_bt_exit);
arch/arm/mach-pxa/tosa.c
View file @ 30d38542
......@@ -18,30 +18,31 @@
#include <linux/major.h>
#include <linux/fs.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/mmc/host.h>
#include <linux/mfd/tc6393xb.h>
#include <linux/mfd/tmio.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/pm.h>
#include <linux/delay.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/gpio.h>
#include <linux/pda_power.h>
#include <linux/rfkill.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/mach-types.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/mfp-pxa25x.h>
#include <asm/arch/irda.h>
#include <asm/arch/i2c.h>
#include <asm/arch/mmc.h>
#include <asm/arch/udc.h>
#include <asm/arch/tosa_bt.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/arch/tosa.h>
#include <asm/hardware/scoop.h>
......@@ -86,7 +87,7 @@ static unsigned long tosa_pin_config[] = {
GPIO6_MMC_CLK,
GPIO8_MMC_CS0,
GPIO9_GPIO, /* Detect */
// GPIO10 nSD_INT
GPIO10_GPIO, /* nSD_INT */
/* CF */
GPIO13_GPIO, /* CD_IRQ */
......@@ -124,34 +125,34 @@ static unsigned long tosa_pin_config[] = {
GPIO44_BTUART_CTS,
GPIO45_BTUART_RTS,
/* IrDA */
GPIO46_STUART_RXD,
GPIO47_STUART_TXD,
/* Keybd */
GPIO58_GPIO,
GPIO59_GPIO,
GPIO60_GPIO,
GPIO61_GPIO,
GPIO62_GPIO,
GPIO63_GPIO,
GPIO64_GPIO,
GPIO65_GPIO,
GPIO66_GPIO,
GPIO67_GPIO,
GPIO68_GPIO,
GPIO69_GPIO,
GPIO70_GPIO,
GPIO71_GPIO,
GPIO72_GPIO,
GPIO73_GPIO,
GPIO74_GPIO,
GPIO75_GPIO,
GPIO58_GPIO | MFP_LPM_DRIVE_LOW,
GPIO59_GPIO | MFP_LPM_DRIVE_LOW,
GPIO60_GPIO | MFP_LPM_DRIVE_LOW,
GPIO61_GPIO | MFP_LPM_DRIVE_LOW,
GPIO62_GPIO | MFP_LPM_DRIVE_LOW,
GPIO63_GPIO | MFP_LPM_DRIVE_LOW,
GPIO64_GPIO | MFP_LPM_DRIVE_LOW,
GPIO65_GPIO | MFP_LPM_DRIVE_LOW,
GPIO66_GPIO | MFP_LPM_DRIVE_LOW,
GPIO67_GPIO | MFP_LPM_DRIVE_LOW,
GPIO68_GPIO | MFP_LPM_DRIVE_LOW,
GPIO69_GPIO | MFP_LPM_DRIVE_LOW,
GPIO70_GPIO | MFP_LPM_DRIVE_LOW,
GPIO71_GPIO | MFP_LPM_DRIVE_LOW,
GPIO72_GPIO | MFP_LPM_DRIVE_LOW,
GPIO73_GPIO | MFP_LPM_DRIVE_LOW,
GPIO74_GPIO | MFP_LPM_DRIVE_LOW,
GPIO75_GPIO | MFP_LPM_DRIVE_LOW,
/* SPI */
GPIO81_SSP2_CLK_OUT,
GPIO82_SSP2_FRM_OUT,
GPIO83_SSP2_TXD,
/* IrDA is managed in other way */
GPIO46_GPIO,
GPIO47_GPIO,
};
/*
......@@ -249,6 +250,15 @@ static int tosa_mci_init(struct device *dev, irq_handler_t tosa_detect_int, void
tosa_mci_platform_data.detect_delay = msecs_to_jiffies(250);
err = gpio_request(TOSA_GPIO_nSD_DETECT, "MMC/SD card detect");
if (err) {
printk(KERN_ERR "tosa_mci_init: can't request nSD_DETECT gpio\n");
goto err_gpio_detect;
}
err = gpio_direction_input(TOSA_GPIO_nSD_DETECT);
if (err)
goto err_gpio_detect_dir;
err = request_irq(TOSA_IRQ_GPIO_nSD_DETECT, tosa_detect_int,
IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"MMC/SD card detect", data);
......@@ -257,7 +267,7 @@ static int tosa_mci_init(struct device *dev, irq_handler_t tosa_detect_int, void
goto err_irq;
}
err = gpio_request(TOSA_GPIO_SD_WP, "sd_wp");
err = gpio_request(TOSA_GPIO_SD_WP, "SD Write Protect");
if (err) {
printk(KERN_ERR "tosa_mci_init: can't request SD_WP gpio\n");
goto err_gpio_wp;
......@@ -266,7 +276,7 @@ static int tosa_mci_init(struct device *dev, irq_handler_t tosa_detect_int, void
if (err)
goto err_gpio_wp_dir;
err = gpio_request(TOSA_GPIO_PWR_ON, "sd_pwr");
err = gpio_request(TOSA_GPIO_PWR_ON, "SD Power");
if (err) {
printk(KERN_ERR "tosa_mci_init: can't request SD_PWR gpio\n");
goto err_gpio_pwr;
......@@ -275,8 +285,20 @@ static int tosa_mci_init(struct device *dev, irq_handler_t tosa_detect_int, void
if (err)
goto err_gpio_pwr_dir;
err = gpio_request(TOSA_GPIO_nSD_INT, "SD Int");
if (err) {
printk(KERN_ERR "tosa_mci_init: can't request SD_PWR gpio\n");
goto err_gpio_int;
}
err = gpio_direction_input(TOSA_GPIO_nSD_INT);
if (err)
goto err_gpio_int_dir;
return 0;
err_gpio_int_dir:
gpio_free(TOSA_GPIO_nSD_INT);
err_gpio_int:
err_gpio_pwr_dir:
gpio_free(TOSA_GPIO_PWR_ON);
err_gpio_pwr:
......@@ -285,6 +307,9 @@ static int tosa_mci_init(struct device *dev, irq_handler_t tosa_detect_int, void
err_gpio_wp:
free_irq(TOSA_IRQ_GPIO_nSD_DETECT, data);
err_irq:
err_gpio_detect_dir:
gpio_free(TOSA_GPIO_nSD_DETECT);
err_gpio_detect:
return err;
}
......@@ -306,9 +331,11 @@ static int tosa_mci_get_ro(struct device *dev)
static void tosa_mci_exit(struct device *dev, void *data)
{
gpio_free(TOSA_GPIO_nSD_INT);
gpio_free(TOSA_GPIO_PWR_ON);
gpio_free(TOSA_GPIO_SD_WP);
free_irq(TOSA_IRQ_GPIO_nSD_DETECT, data);
gpio_free(TOSA_GPIO_nSD_DETECT);
}
static struct pxamci_platform_data tosa_mci_platform_data = {
......@@ -322,29 +349,55 @@ static struct pxamci_platform_data tosa_mci_platform_data = {
/*
* Irda
*/
static void tosa_irda_transceiver_mode(struct device *dev, int mode)
{
if (mode & IR_OFF) {
gpio_set_value(TOSA_GPIO_IR_POWERDWN, 0);
pxa2xx_transceiver_mode(dev, mode);
gpio_direction_output(TOSA_GPIO_IRDA_TX, 0);
} else {
pxa2xx_transceiver_mode(dev, mode);
gpio_set_value(TOSA_GPIO_IR_POWERDWN, 1);
}
}
static int tosa_irda_startup(struct device *dev)
{
int ret;
ret = gpio_request(TOSA_GPIO_IRDA_TX, "IrDA TX");
if (ret)
goto err_tx;
ret = gpio_direction_output(TOSA_GPIO_IRDA_TX, 0);
if (ret)
goto err_tx_dir;
ret = gpio_request(TOSA_GPIO_IR_POWERDWN, "IrDA powerdown");
if (ret)
return ret;
goto err_pwr;
ret = gpio_direction_output(TOSA_GPIO_IR_POWERDWN, 0);
if (ret)
gpio_free(TOSA_GPIO_IR_POWERDWN);
goto err_pwr_dir;
return ret;
}
tosa_irda_transceiver_mode(dev, IR_SIRMODE | IR_OFF);
static void tosa_irda_shutdown(struct device *dev)
{
return 0;
err_pwr_dir:
gpio_free(TOSA_GPIO_IR_POWERDWN);
err_pwr:
err_tx_dir:
gpio_free(TOSA_GPIO_IRDA_TX);
err_tx:
return ret;
}
static void tosa_irda_transceiver_mode(struct device *dev, int mode)
static void tosa_irda_shutdown(struct device *dev)
{
gpio_set_value(TOSA_GPIO_IR_POWERDWN, !(mode & IR_OFF));
tosa_irda_transceiver_mode(dev, IR_SIRMODE | IR_OFF);
gpio_free(TOSA_GPIO_IR_POWERDWN);
gpio_free(TOSA_GPIO_IRDA_TX);
}
static struct pxaficp_platform_data tosa_ficp_platform_data = {
......@@ -354,6 +407,70 @@ static struct pxaficp_platform_data tosa_ficp_platform_data = {
.shutdown = tosa_irda_shutdown,
};
/*
* Tosa AC IN
*/
static int tosa_power_init(struct device *dev)
{
int ret = gpio_request(TOSA_GPIO_AC_IN, "ac in");
if (ret)
goto err_gpio_req;
ret = gpio_direction_input(TOSA_GPIO_AC_IN);
if (ret)
goto err_gpio_in;
return 0;
err_gpio_in:
gpio_free(TOSA_GPIO_AC_IN);
err_gpio_req:
return ret;
}
static void tosa_power_exit(struct device *dev)
{
gpio_free(TOSA_GPIO_AC_IN);
}
static int tosa_power_ac_online(void)
{
return gpio_get_value(TOSA_GPIO_AC_IN) == 0;
}
static char *tosa_ac_supplied_to[] = {
"main-battery",
"backup-battery",
"jacket-battery",
};
static struct pda_power_pdata tosa_power_data = {
.init = tosa_power_init,
.is_ac_online = tosa_power_ac_online,
.exit = tosa_power_exit,
.supplied_to = tosa_ac_supplied_to,
.num_supplicants = ARRAY_SIZE(tosa_ac_supplied_to),
};
static struct resource tosa_power_resource[] = {
{
.name = "ac",
.start = gpio_to_irq(TOSA_GPIO_AC_IN),
.end = gpio_to_irq(TOSA_GPIO_AC_IN),
.flags = IORESOURCE_IRQ |
IORESOURCE_IRQ_HIGHEDGE |
IORESOURCE_IRQ_LOWEDGE,
},
};
static struct platform_device tosa_power_device = {
.name = "pda-power",
.id = -1,
.dev.platform_data = &tosa_power_data,
.resource = tosa_power_resource,
.num_resources = ARRAY_SIZE(tosa_power_resource),
};
/*
* Tosa Keyboard
*/
......@@ -439,7 +556,7 @@ static struct gpio_led tosa_gpio_leds[] = {
},
{
.name = "tosa:blue:bluetooth",
.default_trigger = "none",
.default_trigger = "tosa-bt",
.gpio = TOSA_GPIO_BT_LED,
},
};
......@@ -457,21 +574,184 @@ static struct platform_device tosaled_device = {
},
};
/*
* Toshiba Mobile IO Controller
*/
static struct resource tc6393xb_resources[] = {
[0] = {
.start = TOSA_LCDC_PHYS,
.end = TOSA_LCDC_PHYS + 0x3ffffff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = TOSA_IRQ_GPIO_TC6393XB_INT,
.end = TOSA_IRQ_GPIO_TC6393XB_INT,
.flags = IORESOURCE_IRQ,
},
};
static int tosa_tc6393xb_enable(struct platform_device *dev)
{
int rc;
rc = gpio_request(TOSA_GPIO_TC6393XB_REST_IN, "tc6393xb #pclr");
if (rc)
goto err_req_pclr;
rc = gpio_request(TOSA_GPIO_TC6393XB_SUSPEND, "tc6393xb #suspend");
if (rc)
goto err_req_suspend;
rc = gpio_request(TOSA_GPIO_TC6393XB_L3V_ON, "l3v");
if (rc)
goto err_req_l3v;
rc = gpio_direction_output(TOSA_GPIO_TC6393XB_L3V_ON, 0);
if (rc)
goto err_dir_l3v;
rc = gpio_direction_output(TOSA_GPIO_TC6393XB_SUSPEND, 0);
if (rc)
goto err_dir_suspend;
rc = gpio_direction_output(TOSA_GPIO_TC6393XB_REST_IN, 0);
if (rc)
goto err_dir_pclr;
mdelay(1);
gpio_set_value(TOSA_GPIO_TC6393XB_SUSPEND, 1);
mdelay(10);
gpio_set_value(TOSA_GPIO_TC6393XB_REST_IN, 1);
gpio_set_value(TOSA_GPIO_TC6393XB_L3V_ON, 1);
return 0;
err_dir_pclr:
err_dir_suspend:
err_dir_l3v:
gpio_free(TOSA_GPIO_TC6393XB_L3V_ON);
err_req_l3v:
gpio_free(TOSA_GPIO_TC6393XB_SUSPEND);
err_req_suspend:
gpio_free(TOSA_GPIO_TC6393XB_REST_IN);
err_req_pclr:
return rc;
}
static int tosa_tc6393xb_disable(struct platform_device *dev)
{
gpio_free(TOSA_GPIO_TC6393XB_L3V_ON);
gpio_free(TOSA_GPIO_TC6393XB_SUSPEND);
gpio_free(TOSA_GPIO_TC6393XB_REST_IN);
return 0;
}
static int tosa_tc6393xb_resume(struct platform_device *dev)
{
gpio_set_value(TOSA_GPIO_TC6393XB_SUSPEND, 1);
mdelay(10);
gpio_set_value(TOSA_GPIO_TC6393XB_L3V_ON, 1);
mdelay(10);
return 0;
}
static int tosa_tc6393xb_suspend(struct platform_device *dev)
{
gpio_set_value(TOSA_GPIO_TC6393XB_L3V_ON, 0);
gpio_set_value(TOSA_GPIO_TC6393XB_SUSPEND, 0);
return 0;
}
static struct mtd_partition tosa_nand_partition[] = {
{
.name = "smf",
.offset = 0,
.size = 7 * 1024 * 1024,
},
{
.name = "root",
.offset = MTDPART_OFS_APPEND,
.size = 28 * 1024 * 1024,
},
{
.name = "home",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
static struct nand_bbt_descr tosa_tc6393xb_nand_bbt = {
.options = 0,
.offs = 4,
.len = 2,
.pattern = scan_ff_pattern
};
static struct tmio_nand_data tosa_tc6393xb_nand_config = {
.num_partitions = ARRAY_SIZE(tosa_nand_partition),
.partition = tosa_nand_partition,
.badblock_pattern = &tosa_tc6393xb_nand_bbt,
};
static struct tc6393xb_platform_data tosa_tc6393xb_setup = {
.scr_pll2cr = 0x0cc1,
.scr_gper = 0x3300,
.scr_gpo_dsr =
TOSA_TC6393XB_GPIO_BIT(TOSA_GPIO_CARD_VCC_ON),
.scr_gpo_doecr =
TOSA_TC6393XB_GPIO_BIT(TOSA_GPIO_CARD_VCC_ON),
.irq_base = IRQ_BOARD_START,
.gpio_base = TOSA_TC6393XB_GPIO_BASE,
.enable = tosa_tc6393xb_enable,
.disable = tosa_tc6393xb_disable,
.suspend = tosa_tc6393xb_suspend,
.resume = tosa_tc6393xb_resume,
.nand_data = &tosa_tc6393xb_nand_config,
};
static struct platform_device tc6393xb_device = {
.name = "tc6393xb",
.id = -1,
.dev = {
.platform_data = &tosa_tc6393xb_setup,
},
.num_resources = ARRAY_SIZE(tc6393xb_resources),
.resource = tc6393xb_resources,
};
static struct tosa_bt_data tosa_bt_data = {
.gpio_pwr = TOSA_GPIO_BT_PWR_EN,
.gpio_reset = TOSA_GPIO_BT_RESET,
};
static struct platform_device tosa_bt_device = {
.name = "tosa-bt",
.id = -1,
.dev.platform_data = &tosa_bt_data,
};
static struct platform_device *devices[] __initdata = {
&tosascoop_device,
&tosascoop_jc_device,
&tc6393xb_device,
&tosa_power_device,
&tosakbd_device,
&tosa_gpio_keys_device,
&tosaled_device,
&tosa_bt_device,
};
static void tosa_poweroff(void)
{
gpio_direction_output(TOSA_GPIO_ON_RESET, 0);
gpio_set_value(TOSA_GPIO_ON_RESET, 1);
mdelay(1000);
arm_machine_restart('h');
arm_machine_restart('g');
}
static void tosa_restart(char mode)
......@@ -485,10 +765,14 @@ static void tosa_restart(char mode)
static void __init tosa_init(void)
{
int dummy;
pxa2xx_mfp_config(ARRAY_AND_SIZE(tosa_pin_config));
gpio_set_wake(MFP_PIN_GPIO1, 1);
/* We can't pass to gpio-keys since it will drop the Reset altfunc */
init_gpio_reset(TOSA_GPIO_ON_RESET);
pm_power_off = tosa_poweroff;
arm_pm_restart = tosa_restart;
......@@ -497,6 +781,10 @@ static void __init tosa_init(void)
/* enable batt_fault */
PMCR = 0x01;
dummy = gpiochip_reserve(TOSA_SCOOP_GPIO_BASE, 12);
dummy = gpiochip_reserve(TOSA_SCOOP_JC_GPIO_BASE, 12);
dummy = gpiochip_reserve(TOSA_TC6393XB_GPIO_BASE, 16);
pxa_set_mci_info(&tosa_mci_platform_data);
pxa_set_udc_info(&udc_info);
pxa_set_ficp_info(&tosa_ficp_platform_data);
......
arch/arm/mach-pxa/trizeps4.c
View file @ 30d38542
......@@ -254,6 +254,7 @@ static void board_irda_mode(struct device *dev, int mode)
/* Fast mode */
trizeps_conxs_ircr |= ConXS_IRCR_MODE;
}
pxa2xx_transceiver_mode(dev, mode);
if (mode & IR_OFF) {
trizeps_conxs_ircr |= ConXS_IRCR_SD;
} else {
......
arch/arm/mach-pxa/zylonite.c
View file @ 30d38542
......@@ -19,6 +19,7 @@
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pwm_backlight.h>
#include <linux/smc91x.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
......@@ -29,6 +30,7 @@
#include <asm/arch/zylonite.h>
#include <asm/arch/mmc.h>
#include <asm/arch/pxa27x_keypad.h>
#include <asm/arch/pxa3xx_nand.h>
#include "devices.h"
#include "generic.h"
......@@ -37,6 +39,8 @@
struct platform_mmc_slot zylonite_mmc_slot[MAX_SLOTS];
int gpio_eth_irq;
int gpio_debug_led1;
int gpio_debug_led2;
int wm9713_irq;
......@@ -56,13 +60,57 @@ static struct resource smc91x_resources[] = {
}
};
static struct smc91x_platdata zylonite_smc91x_info = {
.flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT |
SMC91X_NOWAIT | SMC91X_USE_DMA,
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
.dev = {
.platform_data = &zylonite_smc91x_info,
},
};
#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
static struct gpio_led zylonite_debug_leds[] = {
[0] = {
.name = "zylonite:yellow:1",
.default_trigger = "heartbeat",
},
[1] = {
.name = "zylonite:yellow:2",
.default_trigger = "default-on",
},
};
static struct gpio_led_platform_data zylonite_debug_leds_info = {
.leds = zylonite_debug_leds,
.num_leds = ARRAY_SIZE(zylonite_debug_leds),
};
static struct platform_device zylonite_device_leds = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &zylonite_debug_leds_info,
}
};
static void __init zylonite_init_leds(void)
{
zylonite_debug_leds[0].gpio = gpio_debug_led1;
zylonite_debug_leds[1].gpio = gpio_debug_led2;
platform_device_register(&zylonite_device_leds);
}
#else
static inline void zylonite_init_leds(void) {}
#endif
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
static struct platform_pwm_backlight_data zylonite_backlight_data = {
.pwm_id = 3,
......@@ -259,7 +307,7 @@ static void __init zylonite_init_mmc(void)
static inline void zylonite_init_mmc(void) {}
#endif
#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULES)
#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
static unsigned int zylonite_matrix_key_map[] = {
/* KEY(row, col, key_code) */
KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_C), KEY(0, 5, KEY_D),
......@@ -324,6 +372,57 @@ static void __init zylonite_init_keypad(void)
static inline void zylonite_init_keypad(void) {}
#endif
#if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE)
static struct mtd_partition zylonite_nand_partitions[] = {
[0] = {
.name = "Bootloader",
.offset = 0,
.size = 0x060000,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
[1] = {
.name = "Kernel",
.offset = 0x060000,
.size = 0x200000,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
[2] = {
.name = "Filesystem",
.offset = 0x0260000,
.size = 0x3000000, /* 48M - rootfs */
},
[3] = {
.name = "MassStorage",
.offset = 0x3260000,
.size = 0x3d40000,
},
[4] = {
.name = "BBT",
.offset = 0x6FA0000,
.size = 0x80000,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
/* NOTE: we reserve some blocks at the end of the NAND flash for
* bad block management, and the max number of relocation blocks
* differs on different platforms. Please take care with it when
* defining the partition table.
*/
};
static struct pxa3xx_nand_platform_data zylonite_nand_info = {
.enable_arbiter = 1,
.parts = zylonite_nand_partitions,
.nr_parts = ARRAY_SIZE(zylonite_nand_partitions),
};
static void __init zylonite_init_nand(void)
{
pxa3xx_set_nand_info(&zylonite_nand_info);
}
#else
static inline void zylonite_init_nand(void) {}
#endif /* CONFIG_MTD_NAND_PXA3xx || CONFIG_MTD_NAND_PXA3xx_MODULE */
static void __init zylonite_init(void)
{
/* board-processor specific initialization */
......@@ -342,6 +441,8 @@ static void __init zylonite_init(void)
zylonite_init_lcd();
zylonite_init_mmc();
zylonite_init_keypad();
zylonite_init_nand();
zylonite_init_leds();
}
MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
......
arch/arm/mach-pxa/zylonite_pxa300.c
View file @ 30d38542
......@@ -16,9 +16,12 @@
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/i2c/pca953x.h>
#include <asm/gpio.h>
#include <asm/arch/mfp-pxa300.h>
#include <asm/arch/i2c.h>
#include <asm/arch/zylonite.h>
#include "generic.h"
......@@ -109,6 +112,10 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = {
GPIO12_MMC2_DAT3,
GPIO13_MMC2_CLK,
GPIO14_MMC2_CMD,
/* Standard I2C */
GPIO21_I2C_SCL,
GPIO22_I2C_SDA,
};
static mfp_cfg_t pxa300_mfp_cfg[] __initdata = {
......@@ -192,6 +199,39 @@ static void __init zylonite_detect_lcd_panel(void)
pxa3xx_mfp_write(lcd_detect_pins[i], mfpr_save[i]);
}
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
static struct pca953x_platform_data gpio_exp[] = {
[0] = {
.gpio_base = 128,
},
[1] = {
.gpio_base = 144,
},
};
struct i2c_board_info zylonite_i2c_board_info[] = {
{
.type = "pca9539",
.addr = 0x74,
.platform_data = &gpio_exp[0],
.irq = IRQ_GPIO(18),
}, {
.type = "pca9539",
.addr = 0x75,
.platform_data = &gpio_exp[1],
.irq = IRQ_GPIO(19),
},
};
static void __init zylonite_init_i2c(void)
{
pxa_set_i2c_info(NULL);
i2c_register_board_info(0, ARRAY_AND_SIZE(zylonite_i2c_board_info));
}
#else
static inline void zylonite_init_i2c(void) {}
#endif
void __init zylonite_pxa300_init(void)
{
if (cpu_is_pxa300() || cpu_is_pxa310()) {
......@@ -207,6 +247,8 @@ void __init zylonite_pxa300_init(void)
/* WM9713 IRQ */
wm9713_irq = mfp_to_gpio(MFP_PIN_GPIO26);
zylonite_init_i2c();
}
if (cpu_is_pxa300()) {
......@@ -222,4 +264,8 @@ void __init zylonite_pxa300_init(void)
zylonite_mmc_slot[2].gpio_cd = EXT_GPIO(30);
zylonite_mmc_slot[2].gpio_wp = EXT_GPIO(31);
}
/* GPIOs for Debug LEDs */
gpio_debug_led1 = EXT_GPIO(25);
gpio_debug_led2 = EXT_GPIO(26);
}
arch/arm/mach-pxa/zylonite_pxa320.c
View file @ 30d38542
......@@ -116,6 +116,10 @@ static mfp_cfg_t mfp_cfg[] __initdata = {
GPIO27_MMC2_DAT3,
GPIO28_MMC2_CLK,
GPIO29_MMC2_CMD,
/* Debug LEDs */
GPIO1_2_GPIO | MFP_LPM_DRIVE_HIGH,
GPIO4_2_GPIO | MFP_LPM_DRIVE_HIGH,
};
#define NUM_LCD_DETECT_PINS 7
......@@ -189,6 +193,8 @@ void __init zylonite_pxa320_init(void)
/* GPIO pin assignment */
gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO9);
gpio_debug_led1 = mfp_to_gpio(MFP_PIN_GPIO1_2);
gpio_debug_led2 = mfp_to_gpio(MFP_PIN_GPIO4_2);
/* MMC card detect & write protect for controller 0 */
zylonite_mmc_slot[0].gpio_cd = mfp_to_gpio(MFP_PIN_GPIO1);
......
arch/arm/mach-sa1100/clock.c
View file @ 30d38542
......@@ -103,7 +103,7 @@ static void clk_gpio27_disable(void)
}
static struct clk clk_gpio27 = {
.name = "GPIO27_CLK",
.name = "SA1111_CLK",
.rate = 3686400,
.enable = clk_gpio27_enable,
.disable = clk_gpio27_disable,
......
arch/arm/mm/Makefile
View file @ 30d38542
......@@ -76,3 +76,5 @@ obj-$(CONFIG_CPU_V7) += proc-v7.o
obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o
obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
obj-$(CONFIG_CACHE_XSC3L2) += cache-xsc3l2.o
arch/arm/tools/mach-types
View file @ 30d38542
......@@ -12,7 +12,7 @@
#
# http://www.arm.linux.org.uk/developer/machines/?action=new
#
# Last update: Mon Jul 7 16:25:39 2008
# Last update: Sun Jul 13 12:04:05 2008
#
# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
#
......@@ -1812,3 +1812,11 @@ jade MACH_JADE JADE 1821
ks8695_softplc MACH_KS8695_SOFTPLC KS8695_SOFTPLC 1822
gprisc4 MACH_GPRISC4 GPRISC4 1823
stamp9260 MACH_STAMP9260 STAMP9260 1824
smdk6430 MACH_SMDK6430 SMDK6430 1825
smdkc100 MACH_SMDKC100 SMDKC100 1826
tavorevb MACH_TAVOREVB TAVOREVB 1827
saar MACH_SAAR SAAR 1828
deister_eyecam MACH_DEISTER_EYECAM DEISTER_EYECAM 1829
at91sam9m10ek MACH_AT91SAM9M10EK AT91SAM9M10EK 1830
linkstation_produo MACH_LINKSTATION_PRODUO LINKSTATION_PRODUO 1831
hit_b0 MACH_HIT_B0 HIT_B0 1832
arch/sh/boards/renesas/migor/setup.c
View file @ 30d38542
......@@ -30,7 +30,6 @@
static struct smc91x_platdata smc91x_info = {
.flags = SMC91X_USE_16BIT,
.irq_flags = IRQF_TRIGGER_HIGH,
};
static struct resource smc91x_eth_resources[] = {
......@@ -42,7 +41,7 @@ static struct resource smc91x_eth_resources[] = {
},
[1] = {
.start = 32, /* IRQ0 */
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
},
};
......
drivers/input/keyboard/tosakbd.c
View file @ 30d38542
......@@ -215,8 +215,6 @@ static int tosakbd_suspend(struct platform_device *dev, pm_message_t state)
unsigned long flags;
spin_lock_irqsave(&tosakbd->lock, flags);
PGSR1 = (PGSR1 & ~TOSA_GPIO_LOW_STROBE_BIT);
PGSR2 = (PGSR2 & ~TOSA_GPIO_HIGH_STROBE_BIT);
tosakbd->suspended = 1;
spin_unlock_irqrestore(&tosakbd->lock, flags);
......
drivers/mfd/Kconfig
View file @ 30d38542
......@@ -5,6 +5,10 @@
menu "Multifunction device drivers"
depends on HAS_IOMEM
config MFD_CORE
tristate
default n
config MFD_SM501
tristate "Support for Silicon Motion SM501"
---help---
......@@ -38,6 +42,13 @@ config HTC_PASIC3
HTC Magician devices, respectively. Actual functionality is
handled by the leds-pasic3 and ds1wm drivers.
config MFD_TC6393XB
bool "Support Toshiba TC6393XB"
depends on HAVE_GPIO_LIB
select MFD_CORE
help
Support for Toshiba Mobile IO Controller TC6393XB
endmenu
menu "Multimedia Capabilities Port drivers"
......
drivers/mfd/Makefile
View file @ 30d38542
......@@ -8,6 +8,10 @@ obj-$(CONFIG_MFD_ASIC3) += asic3.o
obj-$(CONFIG_HTC_EGPIO) += htc-egpio.o
obj-$(CONFIG_HTC_PASIC3) += htc-pasic3.o
obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o
obj-$(CONFIG_MFD_CORE) += mfd-core.o
obj-$(CONFIG_MCP) += mcp-core.o
obj-$(CONFIG_MCP_SA11X0) += mcp-sa11x0.o
obj-$(CONFIG_MCP_UCB1200) += ucb1x00-core.o
......
drivers/mfd/mfd-core.c 0 → 100644
View file @ 30d38542
/*
* drivers/mfd/mfd-core.c
*
* core MFD support
* Copyright (c) 2006 Ian Molton
* Copyright (c) 2007,2008 Dmitry Baryshkov
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
static int mfd_add_device(struct platform_device *parent,
const struct mfd_cell *cell,
struct resource *mem_base,
int irq_base)
{
struct resource res[cell->num_resources];
struct platform_device *pdev;
int ret = -ENOMEM;
int r;
pdev = platform_device_alloc(cell->name, parent->id);
if (!pdev)
goto fail_alloc;
pdev->dev.parent = &parent->dev;
ret = platform_device_add_data(pdev,
cell, sizeof(struct mfd_cell));
if (ret)
goto fail_device;
memzero(res, sizeof(res));
for (r = 0; r < cell->num_resources; r++) {
res[r].name = cell->resources[r].name;
res[r].flags = cell->resources[r].flags;
/* Find out base to use */
if (cell->resources[r].flags & IORESOURCE_MEM) {
res[r].parent = mem_base;
res[r].start = mem_base->start +
cell->resources[r].start;
res[r].end = mem_base->start +
cell->resources[r].end;
} else if (cell->resources[r].flags & IORESOURCE_IRQ) {
res[r].start = irq_base +
cell->resources[r].start;
res[r].end = irq_base +
cell->resources[r].end;
} else {
res[r].parent = cell->resources[r].parent;
res[r].start = cell->resources[r].start;
res[r].end = cell->resources[r].end;
}
}
platform_device_add_resources(pdev, res, cell->num_resources);
ret = platform_device_add(pdev);
if (ret)
goto fail_device;
return 0;
/* platform_device_del(pdev); */
fail_device:
platform_device_put(pdev);
fail_alloc:
return ret;
}
int mfd_add_devices(
struct platform_device *parent,
const struct mfd_cell *cells, int n_devs,
struct resource *mem_base,
int irq_base)
{
int i;
int ret = 0;
for (i = 0; i < n_devs; i++) {
ret = mfd_add_device(parent, cells + i, mem_base, irq_base);
if (ret)
break;
}
if (ret)
mfd_remove_devices(parent);
return ret;
}
EXPORT_SYMBOL(mfd_add_devices);
static int mfd_remove_devices_fn(struct device *dev, void *unused)
{
platform_device_unregister(
container_of(dev, struct platform_device, dev));
return 0;
}
void mfd_remove_devices(struct platform_device *parent)
{
device_for_each_child(&parent->dev, NULL, mfd_remove_devices_fn);
}
EXPORT_SYMBOL(mfd_remove_devices);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Ian Molton, Dmitry Baryshkov");
drivers/mfd/tc6393xb.c 0 → 100644
View file @ 30d38542
/*
* Toshiba TC6393XB SoC support
*
* Copyright(c) 2005-2006 Chris Humbert
* Copyright(c) 2005 Dirk Opfer
* Copyright(c) 2005 Ian Molton <spyro@f2s.com>
* Copyright(c) 2007 Dmitry Baryshkov
*
* Based on code written by Sharp/Lineo for 2.4 kernels
* Based on locomo.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/fb.h>
#include <linux/clk.h>
#include <linux/mfd/core.h>
#include <linux/mfd/tmio.h>
#include <linux/mfd/tc6393xb.h>
#include <linux/gpio.h>
#define SCR_REVID 0x08 /* b Revision ID */
#define SCR_ISR 0x50 /* b Interrupt Status */
#define SCR_IMR 0x52 /* b Interrupt Mask */
#define SCR_IRR 0x54 /* b Interrupt Routing */
#define SCR_GPER 0x60 /* w GP Enable */
#define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */
#define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */
#define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */
#define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */
#define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */
#define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
#define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
#define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
#define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
#define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
#define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
#define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
#define SCR_CCR 0x98 /* w Clock Control */
#define SCR_PLL2CR 0x9a /* w PLL2 Control */
#define SCR_PLL1CR 0x9c /* l PLL1 Control */
#define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */
#define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */
#define SCR_FER 0xe0 /* b Function Enable */
#define SCR_MCR 0xe4 /* w Mode Control */
#define SCR_CONFIG 0xfc /* b Configuration Control */
#define SCR_DEBUG 0xff /* b Debug */
#define SCR_CCR_CK32K BIT(0)
#define SCR_CCR_USBCK BIT(1)
#define SCR_CCR_UNK1 BIT(4)
#define SCR_CCR_MCLK_MASK (7 << 8)
#define SCR_CCR_MCLK_OFF (0 << 8)
#define SCR_CCR_MCLK_12 (1 << 8)
#define SCR_CCR_MCLK_24 (2 << 8)
#define SCR_CCR_MCLK_48 (3 << 8)
#define SCR_CCR_HCLK_MASK (3 << 12)
#define SCR_CCR_HCLK_24 (0 << 12)
#define SCR_CCR_HCLK_48 (1 << 12)
#define SCR_FER_USBEN BIT(0) /* USB host enable */
#define SCR_FER_LCDCVEN BIT(1) /* polysilicon TFT enable */
#define SCR_FER_SLCDEN BIT(2) /* SLCD enable */
#define SCR_MCR_RDY_MASK (3 << 0)
#define SCR_MCR_RDY_OPENDRAIN (0 << 0)
#define SCR_MCR_RDY_TRISTATE (1 << 0)
#define SCR_MCR_RDY_PUSHPULL (2 << 0)
#define SCR_MCR_RDY_UNK BIT(2)
#define SCR_MCR_RDY_EN BIT(3)
#define SCR_MCR_INT_MASK (3 << 4)
#define SCR_MCR_INT_OPENDRAIN (0 << 4)
#define SCR_MCR_INT_TRISTATE (1 << 4)
#define SCR_MCR_INT_PUSHPULL (2 << 4)
#define SCR_MCR_INT_UNK BIT(6)
#define SCR_MCR_INT_EN BIT(7)
/* bits 8 - 16 are unknown */
#define TC_GPIO_BIT(i) (1 << (i & 0x7))
/*--------------------------------------------------------------------------*/
struct tc6393xb {
void __iomem *scr;
struct gpio_chip gpio;
struct clk *clk; /* 3,6 Mhz */
spinlock_t lock; /* protects RMW cycles */
struct {
u8 fer;
u16 ccr;
u8 gpi_bcr[3];
u8 gpo_dsr[3];
u8 gpo_doecr[3];
} suspend_state;
struct resource rscr;
struct resource *iomem;
int irq;
int irq_base;
};
enum {
TC6393XB_CELL_NAND,
};
/*--------------------------------------------------------------------------*/
static int tc6393xb_nand_enable(struct platform_device *nand)
{
struct platform_device *dev = to_platform_device(nand->dev.parent);
struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
unsigned long flags;
spin_lock_irqsave(&tc6393xb->lock, flags);
/* SMD buffer on */
dev_dbg(&dev->dev, "SMD buffer on\n");
iowrite8(0xff, tc6393xb->scr + SCR_GPI_BCR(1));
spin_unlock_irqrestore(&tc6393xb->lock, flags);
return 0;
}
static struct resource __devinitdata tc6393xb_nand_resources[] = {
{
.name = TMIO_NAND_CONFIG,
.start = 0x0100,
.end = 0x01ff,
.flags = IORESOURCE_MEM,
},
{
.name = TMIO_NAND_CONTROL,
.start = 0x1000,
.end = 0x1007,
.flags = IORESOURCE_MEM,
},
{
.name = TMIO_NAND_IRQ,
.start = IRQ_TC6393_NAND,
.end = IRQ_TC6393_NAND,
.flags = IORESOURCE_IRQ,
},
};
static struct mfd_cell __devinitdata tc6393xb_cells[] = {
[TC6393XB_CELL_NAND] = {
.name = "tmio-nand",
.enable = tc6393xb_nand_enable,
.num_resources = ARRAY_SIZE(tc6393xb_nand_resources),
.resources = tc6393xb_nand_resources,
},
};
/*--------------------------------------------------------------------------*/
static int tc6393xb_gpio_get(struct gpio_chip *chip,
unsigned offset)
{
struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
/* XXX: does dsr also represent inputs? */
return ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8))
& TC_GPIO_BIT(offset);
}
static void __tc6393xb_gpio_set(struct gpio_chip *chip,
unsigned offset, int value)
{
struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
u8 dsr;
dsr = ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8));
if (value)
dsr |= TC_GPIO_BIT(offset);
else
dsr &= ~TC_GPIO_BIT(offset);
iowrite8(dsr, tc6393xb->scr + SCR_GPO_DSR(offset / 8));
}
static void tc6393xb_gpio_set(struct gpio_chip *chip,
unsigned offset, int value)
{
struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
unsigned long flags;
spin_lock_irqsave(&tc6393xb->lock, flags);
__tc6393xb_gpio_set(chip, offset, value);
spin_unlock_irqrestore(&tc6393xb->lock, flags);
}
static int tc6393xb_gpio_direction_input(struct gpio_chip *chip,
unsigned offset)
{
struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
unsigned long flags;
u8 doecr;
spin_lock_irqsave(&tc6393xb->lock, flags);
doecr = ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
doecr &= ~TC_GPIO_BIT(offset);
iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
spin_unlock_irqrestore(&tc6393xb->lock, flags);
return 0;
}
static int tc6393xb_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
unsigned long flags;
u8 doecr;
spin_lock_irqsave(&tc6393xb->lock, flags);
__tc6393xb_gpio_set(chip, offset, value);
doecr = ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
doecr |= TC_GPIO_BIT(offset);
iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
spin_unlock_irqrestore(&tc6393xb->lock, flags);
return 0;
}
static int tc6393xb_register_gpio(struct tc6393xb *tc6393xb, int gpio_base)
{
tc6393xb->gpio.label = "tc6393xb";
tc6393xb->gpio.base = gpio_base;
tc6393xb->gpio.ngpio = 16;
tc6393xb->gpio.set = tc6393xb_gpio_set;
tc6393xb->gpio.get = tc6393xb_gpio_get;
tc6393xb->gpio.direction_input = tc6393xb_gpio_direction_input;
tc6393xb->gpio.direction_output = tc6393xb_gpio_direction_output;
return gpiochip_add(&tc6393xb->gpio);
}
/*--------------------------------------------------------------------------*/
static void
tc6393xb_irq(unsigned int irq, struct irq_desc *desc)
{
struct tc6393xb *tc6393xb = get_irq_data(irq);
unsigned int isr;
unsigned int i, irq_base;
irq_base = tc6393xb->irq_base;
while ((isr = ioread8(tc6393xb->scr + SCR_ISR) &
~ioread8(tc6393xb->scr + SCR_IMR)))
for (i = 0; i < TC6393XB_NR_IRQS; i++) {
if (isr & (1 << i))
generic_handle_irq(irq_base + i);
}
}
static void tc6393xb_irq_ack(unsigned int irq)
{
}
static void tc6393xb_irq_mask(unsigned int irq)
{
struct tc6393xb *tc6393xb = get_irq_chip_data(irq);
unsigned long flags;
u8 imr;
spin_lock_irqsave(&tc6393xb->lock, flags);
imr = ioread8(tc6393xb->scr + SCR_IMR);
imr |= 1 << (irq - tc6393xb->irq_base);
iowrite8(imr, tc6393xb->scr + SCR_IMR);
spin_unlock_irqrestore(&tc6393xb->lock, flags);
}
static void tc6393xb_irq_unmask(unsigned int irq)
{
struct tc6393xb *tc6393xb = get_irq_chip_data(irq);
unsigned long flags;
u8 imr;
spin_lock_irqsave(&tc6393xb->lock, flags);
imr = ioread8(tc6393xb->scr + SCR_IMR);
imr &= ~(1 << (irq - tc6393xb->irq_base));
iowrite8(imr, tc6393xb->scr + SCR_IMR);
spin_unlock_irqrestore(&tc6393xb->lock, flags);
}
static struct irq_chip tc6393xb_chip = {
.name = "tc6393xb",
.ack = tc6393xb_irq_ack,
.mask = tc6393xb_irq_mask,
.unmask = tc6393xb_irq_unmask,
};
static void tc6393xb_attach_irq(struct platform_device *dev)
{
struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
unsigned int irq, irq_base;
irq_base = tc6393xb->irq_base;
for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
set_irq_chip(irq, &tc6393xb_chip);
set_irq_chip_data(irq, tc6393xb);
set_irq_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
set_irq_type(tc6393xb->irq, IRQT_FALLING);
set_irq_data(tc6393xb->irq, tc6393xb);
set_irq_chained_handler(tc6393xb->irq, tc6393xb_irq);
}
static void tc6393xb_detach_irq(struct platform_device *dev)
{
struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
unsigned int irq, irq_base;
set_irq_chained_handler(tc6393xb->irq, NULL);
set_irq_data(tc6393xb->irq, NULL);
irq_base = tc6393xb->irq_base;
for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
set_irq_flags(irq, 0);
set_irq_chip(irq, NULL);
set_irq_chip_data(irq, NULL);
}
}
/*--------------------------------------------------------------------------*/
static int tc6393xb_hw_init(struct platform_device *dev)
{
struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
int i;
iowrite8(tc6393xb->suspend_state.fer, tc6393xb->scr + SCR_FER);
iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR);
iowrite16(tc6393xb->suspend_state.ccr, tc6393xb->scr + SCR_CCR);
iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN |
SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN |
BIT(15), tc6393xb->scr + SCR_MCR);
iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER);
iowrite8(0, tc6393xb->scr + SCR_IRR);
iowrite8(0xbf, tc6393xb->scr + SCR_IMR);
for (i = 0; i < 3; i++) {
iowrite8(tc6393xb->suspend_state.gpo_dsr[i],
tc6393xb->scr + SCR_GPO_DSR(i));
iowrite8(tc6393xb->suspend_state.gpo_doecr[i],
tc6393xb->scr + SCR_GPO_DOECR(i));
iowrite8(tc6393xb->suspend_state.gpi_bcr[i],
tc6393xb->scr + SCR_GPI_BCR(i));
}
return 0;
}
static int __devinit tc6393xb_probe(struct platform_device *dev)
{
struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
struct tc6393xb *tc6393xb;
struct resource *iomem;
struct resource *rscr;
int retval, temp;
int i;
iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
if (!iomem)
return -EINVAL;
tc6393xb = kzalloc(sizeof *tc6393xb, GFP_KERNEL);
if (!tc6393xb) {
retval = -ENOMEM;
goto err_kzalloc;
}
spin_lock_init(&tc6393xb->lock);
platform_set_drvdata(dev, tc6393xb);
tc6393xb->iomem = iomem;
tc6393xb->irq = platform_get_irq(dev, 0);
tc6393xb->irq_base = tcpd->irq_base;
tc6393xb->clk = clk_get(&dev->dev, "GPIO27_CLK" /* "CK3P6MI" */);
if (IS_ERR(tc6393xb->clk)) {
retval = PTR_ERR(tc6393xb->clk);
goto err_clk_get;
}
rscr = &tc6393xb->rscr;
rscr->name = "tc6393xb-core";
rscr->start = iomem->start;
rscr->end = iomem->start + 0xff;
rscr->flags = IORESOURCE_MEM;
retval = request_resource(iomem, rscr);
if (retval)
goto err_request_scr;
tc6393xb->scr = ioremap(rscr->start, rscr->end - rscr->start + 1);
if (!tc6393xb->scr) {
retval = -ENOMEM;
goto err_ioremap;
}
retval = clk_enable(tc6393xb->clk);
if (retval)
goto err_clk_enable;
retval = tcpd->enable(dev);
if (retval)
goto err_enable;
tc6393xb->suspend_state.fer = 0;
for (i = 0; i < 3; i++) {
tc6393xb->suspend_state.gpo_dsr[i] =
(tcpd->scr_gpo_dsr >> (8 * i)) & 0xff;
tc6393xb->suspend_state.gpo_doecr[i] =
(tcpd->scr_gpo_doecr >> (8 * i)) & 0xff;
}
/*
* It may be necessary to change this back to
* platform-dependant code
*/
tc6393xb->suspend_state.ccr = SCR_CCR_UNK1 |
SCR_CCR_HCLK_48;
retval = tc6393xb_hw_init(dev);
if (retval)
goto err_hw_init;
printk(KERN_INFO "Toshiba tc6393xb revision %d at 0x%08lx, irq %d\n",
ioread8(tc6393xb->scr + SCR_REVID),
(unsigned long) iomem->start, tc6393xb->irq);
tc6393xb->gpio.base = -1;
if (tcpd->gpio_base >= 0) {
retval = tc6393xb_register_gpio(tc6393xb, tcpd->gpio_base);
if (retval)
goto err_gpio_add;
}
if (tc6393xb->irq)
tc6393xb_attach_irq(dev);
tc6393xb_cells[TC6393XB_CELL_NAND].driver_data = tcpd->nand_data;
retval = mfd_add_devices(dev,
tc6393xb_cells, ARRAY_SIZE(tc6393xb_cells),
iomem, tcpd->irq_base);
return 0;
if (tc6393xb->irq)
tc6393xb_detach_irq(dev);
err_gpio_add:
if (tc6393xb->gpio.base != -1)
temp = gpiochip_remove(&tc6393xb->gpio);
err_hw_init:
tcpd->disable(dev);
err_clk_enable:
clk_disable(tc6393xb->clk);
err_enable:
iounmap(tc6393xb->scr);
err_ioremap:
release_resource(&tc6393xb->rscr);
err_request_scr:
clk_put(tc6393xb->clk);
err_clk_get:
kfree(tc6393xb);
err_kzalloc:
return retval;
}
static int __devexit tc6393xb_remove(struct platform_device *dev)
{
struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
int ret;
mfd_remove_devices(dev);
if (tc6393xb->irq)
tc6393xb_detach_irq(dev);
if (tc6393xb->gpio.base != -1) {
ret = gpiochip_remove(&tc6393xb->gpio);
if (ret) {
dev_err(&dev->dev, "Can't remove gpio chip: %d\n", ret);
return ret;
}
}
ret = tcpd->disable(dev);
clk_disable(tc6393xb->clk);
iounmap(tc6393xb->scr);
release_resource(&tc6393xb->rscr);
platform_set_drvdata(dev, NULL);
clk_put(tc6393xb->clk);
kfree(tc6393xb);
return ret;
}
#ifdef CONFIG_PM
static int tc6393xb_suspend(struct platform_device *dev, pm_message_t state)
{
struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
int i;
tc6393xb->suspend_state.ccr = ioread16(tc6393xb->scr + SCR_CCR);
tc6393xb->suspend_state.fer = ioread8(tc6393xb->scr + SCR_FER);
for (i = 0; i < 3; i++) {
tc6393xb->suspend_state.gpo_dsr[i] =
ioread8(tc6393xb->scr + SCR_GPO_DSR(i));
tc6393xb->suspend_state.gpo_doecr[i] =
ioread8(tc6393xb->scr + SCR_GPO_DOECR(i));
tc6393xb->suspend_state.gpi_bcr[i] =
ioread8(tc6393xb->scr + SCR_GPI_BCR(i));
}
return tcpd->suspend(dev);
}
static int tc6393xb_resume(struct platform_device *dev)
{
struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
int ret = tcpd->resume(dev);
if (ret)
return ret;
return tc6393xb_hw_init(dev);
}
#else
#define tc6393xb_suspend NULL
#define tc6393xb_resume NULL
#endif
static struct platform_driver tc6393xb_driver = {
.probe = tc6393xb_probe,
.remove = __devexit_p(tc6393xb_remove),
.suspend = tc6393xb_suspend,
.resume = tc6393xb_resume,
.driver = {
.name = "tc6393xb",
.owner = THIS_MODULE,
},
};
static int __init tc6393xb_init(void)
{
return platform_driver_register(&tc6393xb_driver);
}
static void __exit tc6393xb_exit(void)
{
platform_driver_unregister(&tc6393xb_driver);
}
subsys_initcall(tc6393xb_init);
module_exit(tc6393xb_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Ian Molton, Dmitry Baryshkov and Dirk Opfer");
MODULE_DESCRIPTION("tc6393xb Toshiba Mobile IO Controller");
MODULE_ALIAS("platform:tc6393xb");
drivers/mtd/nand/cmx270_nand.c
View file @ 30d38542
......@@ -20,9 +20,11 @@
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/gpio.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/arch/hardware.h>
#include <asm/arch/pxa-regs.h>
......@@ -30,20 +32,6 @@
#define GPIO_NAND_CS (11)
#define GPIO_NAND_RB (89)
/* This macro needed to ensure in-order operation of GPIO and local
* bus. Without both asm command and dummy uncached read there're
* states when NAND access is broken. I've looked for such macro(s) in
* include/asm-arm but found nothing approptiate.
* dmac_clean_range is close, but is makes cache invalidation
* unnecessary here and it cannot be used in module
*/
#define DRAIN_WB() \
do { \
unsigned char dummy; \
asm volatile ("mcr p15, 0, r0, c7, c10, 4":::"r0"); \
dummy=*((unsigned char*)UNCACHED_ADDR); \
} while(0)
/* MTD structure for CM-X270 board */
static struct mtd_info *cmx270_nand_mtd;
......@@ -103,14 +91,14 @@ static int cmx270_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
static inline void nand_cs_on(void)
{
GPCR(GPIO_NAND_CS) = GPIO_bit(GPIO_NAND_CS);
gpio_set_value(GPIO_NAND_CS, 0);
}
static void nand_cs_off(void)
{
DRAIN_WB();
dsb();
GPSR(GPIO_NAND_CS) = GPIO_bit(GPIO_NAND_CS);
gpio_set_value(GPIO_NAND_CS, 1);
}
/*
......@@ -122,7 +110,7 @@ static void cmx270_hwcontrol(struct mtd_info *mtd, int dat,
struct nand_chip* this = mtd->priv;
unsigned int nandaddr = (unsigned int)this->IO_ADDR_W;
DRAIN_WB();
dsb();
if (ctrl & NAND_CTRL_CHANGE) {
if ( ctrl & NAND_ALE )
......@@ -139,12 +127,12 @@ static void cmx270_hwcontrol(struct mtd_info *mtd, int dat,
nand_cs_off();
}
DRAIN_WB();
dsb();
this->IO_ADDR_W = (void __iomem*)nandaddr;
if (dat != NAND_CMD_NONE)
writel((dat << 16), this->IO_ADDR_W);
DRAIN_WB();
dsb();
}
/*
......@@ -152,9 +140,9 @@ static void cmx270_hwcontrol(struct mtd_info *mtd, int dat,
*/
static int cmx270_device_ready(struct mtd_info *mtd)
{
DRAIN_WB();
dsb();
return (GPLR(GPIO_NAND_RB) & GPIO_bit(GPIO_NAND_RB));
return (gpio_get_value(GPIO_NAND_RB));
}
/*
......@@ -168,20 +156,40 @@ static int cmx270_init(void)
int mtd_parts_nb = 0;
int ret;
if (!machine_is_armcore())
return -ENODEV;
ret = gpio_request(GPIO_NAND_CS, "NAND CS");
if (ret) {
pr_warning("CM-X270: failed to request NAND CS gpio\n");
return ret;
}
gpio_direction_output(GPIO_NAND_CS, 1);
ret = gpio_request(GPIO_NAND_RB, "NAND R/B");
if (ret) {
pr_warning("CM-X270: failed to request NAND R/B gpio\n");
goto err_gpio_request;
}
gpio_direction_input(GPIO_NAND_RB);
/* Allocate memory for MTD device structure and private data */
cmx270_nand_mtd = kzalloc(sizeof(struct mtd_info) +
sizeof(struct nand_chip),
GFP_KERNEL);
if (!cmx270_nand_mtd) {
printk("Unable to allocate CM-X270 NAND MTD device structure.\n");
return -ENOMEM;
pr_debug("Unable to allocate CM-X270 NAND MTD device structure.\n");
ret = -ENOMEM;
goto err_kzalloc;
}
cmx270_nand_io = ioremap(PXA_CS1_PHYS, 12);
if (!cmx270_nand_io) {
printk("Unable to ioremap NAND device\n");
pr_debug("Unable to ioremap NAND device\n");
ret = -EINVAL;
goto err1;
goto err_ioremap;
}
/* Get pointer to private data */
......@@ -209,9 +217,9 @@ static int cmx270_init(void)
/* Scan to find existence of the device */
if (nand_scan (cmx270_nand_mtd, 1)) {
printk(KERN_NOTICE "No NAND device\n");
pr_notice("No NAND device\n");
ret = -ENXIO;
goto err2;
goto err_scan;
}
#ifdef CONFIG_MTD_CMDLINE_PARTS
......@@ -229,18 +237,22 @@ static int cmx270_init(void)
}
/* Register the partitions */
printk(KERN_NOTICE "Using %s partition definition\n", part_type);
pr_notice("Using %s partition definition\n", part_type);
ret = add_mtd_partitions(cmx270_nand_mtd, mtd_parts, mtd_parts_nb);
if (ret)
goto err2;
goto err_scan;
/* Return happy */
return 0;
err2:
err_scan:
iounmap(cmx270_nand_io);
err1:
err_ioremap:
kfree(cmx270_nand_mtd);
err_kzalloc:
gpio_free(GPIO_NAND_RB);
err_gpio_request:
gpio_free(GPIO_NAND_CS);
return ret;
......@@ -255,6 +267,9 @@ static void cmx270_cleanup(void)
/* Release resources, unregister device */
nand_release(cmx270_nand_mtd);
gpio_free(GPIO_NAND_RB);
gpio_free(GPIO_NAND_CS);
iounmap(cmx270_nand_io);
/* Free the MTD device structure */
......
drivers/net/smc91x.c
View file @ 30d38542
......@@ -308,7 +308,7 @@ static void smc_reset(struct net_device *dev)
* can't handle it then there will be no recovery except for
* a hard reset or power cycle
*/
if (nowait)
if (lp->cfg.flags & SMC91X_NOWAIT)
cfg |= CONFIG_NO_WAIT;
/*
......@@ -1939,8 +1939,11 @@ static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr,
if (retval)
goto err_out;
#ifdef SMC_USE_PXA_DMA
{
#ifdef CONFIG_ARCH_PXA
# ifdef SMC_USE_PXA_DMA
lp->cfg.flags |= SMC91X_USE_DMA;
# endif
if (lp->cfg.flags & SMC91X_USE_DMA) {
int dma = pxa_request_dma(dev->name, DMA_PRIO_LOW,
smc_pxa_dma_irq, NULL);
if (dma >= 0)
......@@ -1980,7 +1983,7 @@ static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr,
}
err_out:
#ifdef SMC_USE_PXA_DMA
#ifdef CONFIG_ARCH_PXA
if (retval && dev->dma != (unsigned char)-1)
pxa_free_dma(dev->dma);
#endif
......@@ -2050,9 +2053,11 @@ static int smc_enable_device(struct platform_device *pdev)
return 0;
}
static int smc_request_attrib(struct platform_device *pdev)
static int smc_request_attrib(struct platform_device *pdev,
struct net_device *ndev)
{
struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
struct smc_local *lp = netdev_priv(ndev);
if (!res)
return 0;
......@@ -2063,9 +2068,11 @@ static int smc_request_attrib(struct platform_device *pdev)
return 0;
}
static void smc_release_attrib(struct platform_device *pdev)
static void smc_release_attrib(struct platform_device *pdev,
struct net_device *ndev)
{
struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
struct smc_local *lp = netdev_priv(ndev);
if (res)
release_mem_region(res->start, ATTRIB_SIZE);
......@@ -2123,27 +2130,14 @@ static int smc_drv_probe(struct platform_device *pdev)
struct net_device *ndev;
struct resource *res, *ires;
unsigned int __iomem *addr;
unsigned long irq_flags = SMC_IRQ_FLAGS;
int ret;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
if (!res)
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
ret = -ENODEV;
goto out;
}
if (!request_mem_region(res->start, SMC_IO_EXTENT, CARDNAME)) {
ret = -EBUSY;
goto out;
}
ndev = alloc_etherdev(sizeof(struct smc_local));
if (!ndev) {
printk("%s: could not allocate device.\n", CARDNAME);
ret = -ENOMEM;
goto out_release_io;
goto out;
}
SET_NETDEV_DEV(ndev, &pdev->dev);
......@@ -2152,37 +2146,47 @@ static int smc_drv_probe(struct platform_device *pdev)
*/
lp = netdev_priv(ndev);
lp->cfg.irq_flags = SMC_IRQ_FLAGS;
#ifdef SMC_DYNAMIC_BUS_CONFIG
if (pd)
if (pd) {
memcpy(&lp->cfg, pd, sizeof(lp->cfg));
else {
lp->cfg.flags = SMC91X_USE_8BIT;
lp->cfg.flags |= SMC91X_USE_16BIT;
lp->cfg.flags |= SMC91X_USE_32BIT;
lp->io_shift = SMC91X_IO_SHIFT(lp->cfg.flags);
} else {
lp->cfg.flags |= (SMC_CAN_USE_8BIT) ? SMC91X_USE_8BIT : 0;
lp->cfg.flags |= (SMC_CAN_USE_16BIT) ? SMC91X_USE_16BIT : 0;
lp->cfg.flags |= (SMC_CAN_USE_32BIT) ? SMC91X_USE_32BIT : 0;
lp->cfg.flags |= (nowait) ? SMC91X_NOWAIT : 0;
}
lp->cfg.flags &= ~(SMC_CAN_USE_8BIT ? 0 : SMC91X_USE_8BIT);
lp->cfg.flags &= ~(SMC_CAN_USE_16BIT ? 0 : SMC91X_USE_16BIT);
lp->cfg.flags &= ~(SMC_CAN_USE_32BIT ? 0 : SMC91X_USE_32BIT);
#endif
ndev->dma = (unsigned char)-1;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
if (!res)
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
ret = -ENODEV;
goto out_free_netdev;
}
if (!request_mem_region(res->start, SMC_IO_EXTENT, CARDNAME)) {
ret = -EBUSY;
goto out_free_netdev;
}
ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (!ires) {
ret = -ENODEV;
goto out_free_netdev;
goto out_release_io;
}
ndev->irq = ires->start;
if (SMC_IRQ_FLAGS == -1)
lp->cfg.irq_flags = ires->flags & IRQF_TRIGGER_MASK;
ret = smc_request_attrib(pdev);
if (ires->flags & IRQF_TRIGGER_MASK)
irq_flags = ires->flags & IRQF_TRIGGER_MASK;
ret = smc_request_attrib(pdev, ndev);
if (ret)
goto out_free_netdev;
goto out_release_io;
#if defined(CONFIG_SA1100_ASSABET)
NCR_0 |= NCR_ENET_OSC_EN;
#endif
......@@ -2197,7 +2201,7 @@ static int smc_drv_probe(struct platform_device *pdev)
goto out_release_attrib;
}
#ifdef SMC_USE_PXA_DMA
#ifdef CONFIG_ARCH_PXA
{
struct smc_local *lp = netdev_priv(ndev);
lp->device = &pdev->dev;
......@@ -2205,7 +2209,7 @@ static int smc_drv_probe(struct platform_device *pdev)
}
#endif
ret = smc_probe(ndev, addr, lp->cfg.irq_flags);
ret = smc_probe(ndev, addr, irq_flags);
if (ret != 0)
goto out_iounmap;
......@@ -2217,11 +2221,11 @@ static int smc_drv_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, NULL);
iounmap(addr);
out_release_attrib:
smc_release_attrib(pdev);
out_free_netdev:
free_netdev(ndev);
smc_release_attrib(pdev, ndev);
out_release_io:
release_mem_region(res->start, SMC_IO_EXTENT);
out_free_netdev:
free_netdev(ndev);
out:
printk("%s: not found (%d).\n", CARDNAME, ret);
......@@ -2240,14 +2244,14 @@ static int smc_drv_remove(struct platform_device *pdev)
free_irq(ndev->irq, ndev);
#ifdef SMC_USE_PXA_DMA
#ifdef CONFIG_ARCH_PXA
if (ndev->dma != (unsigned char)-1)
pxa_free_dma(ndev->dma);
#endif
iounmap(lp->base);
smc_release_datacs(pdev,ndev);
smc_release_attrib(pdev);
smc_release_attrib(pdev,ndev);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
if (!res)
......
drivers/net/smc91x.h
View file @ 30d38542
......@@ -40,23 +40,46 @@
* Define your architecture specific bus configuration parameters here.
*/
#if defined(CONFIG_ARCH_LUBBOCK)
#if defined(CONFIG_ARCH_LUBBOCK) ||\
defined(CONFIG_MACH_MAINSTONE) ||\
defined(CONFIG_MACH_ZYLONITE) ||\
defined(CONFIG_MACH_LITTLETON)
/* We can only do 16-bit reads and writes in the static memory space. */
#define SMC_CAN_USE_8BIT 0
#include <asm/mach-types.h>
/* Now the bus width is specified in the platform data
* pretend here to support all I/O access types
*/
#define SMC_CAN_USE_8BIT 1
#define SMC_CAN_USE_16BIT 1
#define SMC_CAN_USE_32BIT 0
#define SMC_CAN_USE_32BIT 1
#define SMC_NOWAIT 1
/* The first two address lines aren't connected... */
#define SMC_IO_SHIFT 2
#define SMC_IO_SHIFT (lp->io_shift)
#define SMC_inb(a, r) readb((a) + (r))
#define SMC_inw(a, r) readw((a) + (r))
#define SMC_outw(v, a, r) writew(v, (a) + (r))
#define SMC_inl(a, r) readl((a) + (r))
#define SMC_outb(v, a, r) writeb(v, (a) + (r))
#define SMC_outl(v, a, r) writel(v, (a) + (r))
#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
#define SMC_IRQ_FLAGS (-1) /* from resource */
/* We actually can't write halfwords properly if not word aligned */
static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
{
if (machine_is_mainstone() && reg & 2) {
unsigned int v = val << 16;
v |= readl(ioaddr + (reg & ~2)) & 0xffff;
writel(v, ioaddr + (reg & ~2));
} else {
writew(val, ioaddr + reg);
}
}
#elif defined(CONFIG_BLACKFIN)
#define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
......@@ -195,7 +218,6 @@
#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
#elif defined(CONFIG_ARCH_INNOKOM) || \
defined(CONFIG_MACH_MAINSTONE) || \
defined(CONFIG_ARCH_PXA_IDP) || \
defined(CONFIG_ARCH_RAMSES) || \
defined(CONFIG_ARCH_PCM027)
......@@ -229,22 +251,6 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
}
}
#elif defined(CONFIG_MACH_ZYLONITE)
#define SMC_CAN_USE_8BIT 1
#define SMC_CAN_USE_16BIT 1
#define SMC_CAN_USE_32BIT 0
#define SMC_IO_SHIFT 0
#define SMC_NOWAIT 1
#define SMC_USE_PXA_DMA 1
#define SMC_inb(a, r) readb((a) + (r))
#define SMC_inw(a, r) readw((a) + (r))
#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
#define SMC_outb(v, a, r) writeb(v, (a) + (r))
#define SMC_outw(v, a, r) writew(v, (a) + (r))
#define SMC_IRQ_FLAGS (-1) /* from resource */
#elif defined(CONFIG_ARCH_OMAP)
/* We can only do 16-bit reads and writes in the static memory space. */
......@@ -454,7 +460,6 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r,
#define RPC_LSA_DEFAULT RPC_LED_100_10
#define RPC_LSB_DEFAULT RPC_LED_TX_RX
#define SMC_DYNAMIC_BUS_CONFIG
#endif
......@@ -493,7 +498,7 @@ struct smc_local {
spinlock_t lock;
#ifdef SMC_USE_PXA_DMA
#ifdef CONFIG_ARCH_PXA
/* DMA needs the physical address of the chip */
u_long physaddr;
struct device *device;
......@@ -501,20 +506,17 @@ struct smc_local {
void __iomem *base;
void __iomem *datacs;
/* the low address lines on some platforms aren't connected... */
int io_shift;
struct smc91x_platdata cfg;
};
#ifdef SMC_DYNAMIC_BUS_CONFIG
#define SMC_8BIT(p) (((p)->cfg.flags & SMC91X_USE_8BIT) && SMC_CAN_USE_8BIT)
#define SMC_16BIT(p) (((p)->cfg.flags & SMC91X_USE_16BIT) && SMC_CAN_USE_16BIT)
#define SMC_32BIT(p) (((p)->cfg.flags & SMC91X_USE_32BIT) && SMC_CAN_USE_32BIT)
#else
#define SMC_8BIT(p) SMC_CAN_USE_8BIT
#define SMC_16BIT(p) SMC_CAN_USE_16BIT
#define SMC_32BIT(p) SMC_CAN_USE_32BIT
#endif
#define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
#define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
#define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
#ifdef SMC_USE_PXA_DMA
#ifdef CONFIG_ARCH_PXA
/*
* Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
* always happening in irq context so no need to worry about races. TX is
......@@ -608,7 +610,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
{
DCSR(dma) = 0;
}
#endif /* SMC_USE_PXA_DMA */
#endif /* CONFIG_ARCH_PXA */
/*
......
drivers/pcmcia/Kconfig
View file @ 30d38542
......@@ -219,7 +219,8 @@ config PCMCIA_SA1111
config PCMCIA_PXA2XX
tristate "PXA2xx support"
depends on ARM && ARCH_PXA && PCMCIA
depends on ARCH_LUBBOCK || MACH_MAINSTONE || PXA_SHARPSL || MACH_ARMCORE
depends on (ARCH_LUBBOCK || MACH_MAINSTONE || PXA_SHARPSL \
|| MACH_ARMCORE || ARCH_PXA_PALM)
help
Say Y here to include support for the PXA2xx PCMCIA controller
......
drivers/pcmcia/Makefile
View file @ 30d38542
......@@ -72,4 +72,5 @@ pxa2xx_cs-$(CONFIG_ARCH_LUBBOCK) += pxa2xx_lubbock.o sa1111_generic.o
pxa2xx_cs-$(CONFIG_MACH_MAINSTONE) += pxa2xx_mainstone.o
pxa2xx_cs-$(CONFIG_PXA_SHARPSL) += pxa2xx_sharpsl.o
pxa2xx_cs-$(CONFIG_MACH_ARMCORE) += pxa2xx_cm_x270.o
pxa2xx_cs-$(CONFIG_MACH_PALMTX) += pxa2xx_palmtx.o
drivers/pcmcia/pxa2xx_cm_x270.c
View file @ 30d38542
......@@ -5,83 +5,60 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Compulab Ltd., 2003, 2007
* Compulab Ltd., 2003, 2007, 2008
* Mike Rapoport <mike@compulab.co.il>
*
*/
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <pcmcia/ss.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/cm-x270.h>
#include "soc_common.h"
#define GPIO_PCMCIA_S0_CD_VALID (84)
#define GPIO_PCMCIA_S0_RDYINT (82)
#define GPIO_PCMCIA_RESET (53)
#define PCMCIA_S0_CD_VALID IRQ_GPIO(GPIO_PCMCIA_S0_CD_VALID)
#define PCMCIA_S0_RDYINT IRQ_GPIO(GPIO_PCMCIA_S0_RDYINT)
static struct pcmcia_irqs irqs[] = {
{ 0, PCMCIA_S0_CD_VALID, "PCMCIA0 CD" },
{ 1, PCMCIA_S1_CD_VALID, "PCMCIA1 CD" },
};
static int cmx270_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
{
GPSR(GPIO48_nPOE) = GPIO_bit(GPIO48_nPOE) |
GPIO_bit(GPIO49_nPWE) |
GPIO_bit(GPIO50_nPIOR) |
GPIO_bit(GPIO51_nPIOW) |
GPIO_bit(GPIO85_nPCE_1) |
GPIO_bit(GPIO54_nPCE_2);
pxa_gpio_mode(GPIO48_nPOE_MD);
pxa_gpio_mode(GPIO49_nPWE_MD);
pxa_gpio_mode(GPIO50_nPIOR_MD);
pxa_gpio_mode(GPIO51_nPIOW_MD);
pxa_gpio_mode(GPIO85_nPCE_1_MD);
pxa_gpio_mode(GPIO54_nPCE_2_MD);
pxa_gpio_mode(GPIO55_nPREG_MD);
pxa_gpio_mode(GPIO56_nPWAIT_MD);
pxa_gpio_mode(GPIO57_nIOIS16_MD);
/* Reset signal */
pxa_gpio_mode(GPIO53_nPCE_2 | GPIO_OUT);
GPCR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
set_irq_type(PCMCIA_S0_CD_VALID, IRQ_TYPE_EDGE_BOTH);
set_irq_type(PCMCIA_S1_CD_VALID, IRQ_TYPE_EDGE_BOTH);
/* irq's for slots: */
set_irq_type(PCMCIA_S0_RDYINT, IRQ_TYPE_EDGE_FALLING);
set_irq_type(PCMCIA_S1_RDYINT, IRQ_TYPE_EDGE_FALLING);
skt->irq = (skt->nr == 0) ? PCMCIA_S0_RDYINT : PCMCIA_S1_RDYINT;
return soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs));
int ret = gpio_request(GPIO_PCMCIA_RESET, "PCCard reset");
if (ret)
return ret;
gpio_direction_output(GPIO_PCMCIA_RESET, 0);
skt->irq = PCMCIA_S0_RDYINT;
ret = soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs));
if (!ret)
gpio_free(GPIO_PCMCIA_RESET);
return ret;
}
static void cmx270_pcmcia_shutdown(struct soc_pcmcia_socket *skt)
{
soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs));
set_irq_type(IRQ_TO_GPIO(PCMCIA_S0_CD_VALID), IRQ_TYPE_NONE);
set_irq_type(IRQ_TO_GPIO(PCMCIA_S1_CD_VALID), IRQ_TYPE_NONE);
set_irq_type(IRQ_TO_GPIO(PCMCIA_S0_RDYINT), IRQ_TYPE_NONE);
set_irq_type(IRQ_TO_GPIO(PCMCIA_S1_RDYINT), IRQ_TYPE_NONE);
gpio_free(GPIO_PCMCIA_RESET);
}
static void cmx270_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
struct pcmcia_state *state)
{
state->detect = (PCC_DETECT(skt->nr) == 0) ? 1 : 0;
state->ready = (PCC_READY(skt->nr) == 0) ? 0 : 1;
state->detect = (gpio_get_value(GPIO_PCMCIA_S0_CD_VALID) == 0) ? 1 : 0;
state->ready = (gpio_get_value(GPIO_PCMCIA_S0_RDYINT) == 0) ? 0 : 1;
state->bvd1 = 1;
state->bvd2 = 1;
state->vs_3v = 0;
......@@ -93,32 +70,16 @@ static void cmx270_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
static int cmx270_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
const socket_state_t *state)
{
GPSR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
pxa_gpio_mode(GPIO49_nPWE | GPIO_OUT);
switch (skt->nr) {
case 0:
if (state->flags & SS_RESET) {
GPCR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
GPSR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
udelay(10);
GPCR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
GPSR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
}
break;
case 1:
if (state->flags & SS_RESET) {
GPCR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
GPSR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
gpio_set_value(GPIO_PCMCIA_RESET, 1);
udelay(10);
GPCR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
GPSR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
gpio_set_value(GPIO_PCMCIA_RESET, 0);
}
break;
}
pxa_gpio_mode(GPIO49_nPWE_MD);
return 0;
}
......@@ -139,7 +100,7 @@ static struct pcmcia_low_level cmx270_pcmcia_ops __initdata = {
.configure_socket = cmx270_pcmcia_configure_socket,
.socket_init = cmx270_pcmcia_socket_init,
.socket_suspend = cmx270_pcmcia_socket_suspend,
.nr = 2,
.nr = 1,
};
static struct platform_device *cmx270_pcmcia_device;
......
drivers/pcmcia/pxa2xx_palmtx.c 0 → 100644
View file @ 30d38542
/*
* linux/drivers/pcmcia/pxa2xx_palmtx.c
*
* Driver for Palm T|X PCMCIA
*
* Copyright (C) 2007-2008 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <asm/mach-types.h>
#include <asm/arch/gpio.h>
#include <asm/arch/palmtx.h>
#include "soc_common.h"
static int palmtx_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
{
skt->irq = IRQ_GPIO(GPIO_NR_PALMTX_PCMCIA_READY);
return 0;
}
static void palmtx_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt)
{
}
static void palmtx_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
struct pcmcia_state *state)
{
state->detect = 1; /* always inserted */
state->ready = !!gpio_get_value(GPIO_NR_PALMTX_PCMCIA_READY);
state->bvd1 = 1;
state->bvd2 = 1;
state->wrprot = 0;
state->vs_3v = 1;
state->vs_Xv = 0;
}
static int
palmtx_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
const socket_state_t *state)
{
gpio_set_value(GPIO_NR_PALMTX_PCMCIA_POWER1, 1);
gpio_set_value(GPIO_NR_PALMTX_PCMCIA_POWER2, 1);
gpio_set_value(GPIO_NR_PALMTX_PCMCIA_RESET,
!!(state->flags & SS_RESET));
return 0;
}
static void palmtx_pcmcia_socket_init(struct soc_pcmcia_socket *skt)
{
}
static void palmtx_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
{
}
static struct pcmcia_low_level palmtx_pcmcia_ops = {
.owner = THIS_MODULE,
.first = 0,
.nr = 1,
.hw_init = palmtx_pcmcia_hw_init,
.hw_shutdown = palmtx_pcmcia_hw_shutdown,
.socket_state = palmtx_pcmcia_socket_state,
.configure_socket = palmtx_pcmcia_configure_socket,
.socket_init = palmtx_pcmcia_socket_init,
.socket_suspend = palmtx_pcmcia_socket_suspend,
};
static struct platform_device *palmtx_pcmcia_device;
static int __init palmtx_pcmcia_init(void)
{
int ret;
if (!machine_is_palmtx())
return -ENODEV;
palmtx_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1);
if (!palmtx_pcmcia_device)
return -ENOMEM;
ret = platform_device_add_data(palmtx_pcmcia_device, &palmtx_pcmcia_ops,
sizeof(palmtx_pcmcia_ops));
if (!ret)
ret = platform_device_add(palmtx_pcmcia_device);
if (ret)
platform_device_put(palmtx_pcmcia_device);
return ret;
}
static void __exit palmtx_pcmcia_exit(void)
{
platform_device_unregister(palmtx_pcmcia_device);
}
fs_initcall(palmtx_pcmcia_init);
module_exit(palmtx_pcmcia_exit);
MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
MODULE_DESCRIPTION("PCMCIA support for Palm T|X");
MODULE_ALIAS("platform:pxa2xx-pcmcia");
MODULE_LICENSE("GPL");
drivers/power/Kconfig
View file @ 30d38542
......@@ -49,4 +49,10 @@ config BATTERY_OLPC
help
Say Y to enable support for the battery on the OLPC laptop.
config BATTERY_PALMTX
tristate "Palm T|X battery"
depends on MACH_PALMTX
help
Say Y to enable support for the battery in Palm T|X.
endif # POWER_SUPPLY
drivers/power/Makefile
View file @ 30d38542
......@@ -20,3 +20,4 @@ obj-$(CONFIG_APM_POWER) += apm_power.o
obj-$(CONFIG_BATTERY_DS2760) += ds2760_battery.o
obj-$(CONFIG_BATTERY_PMU) += pmu_battery.o
obj-$(CONFIG_BATTERY_OLPC) += olpc_battery.o
obj-$(CONFIG_BATTERY_PALMTX) += palmtx_battery.o
drivers/power/palmtx_battery.c 0 → 100644
View file @ 30d38542
/*
* linux/drivers/power/palmtx_battery.c
*
* Battery measurement code for Palm T|X Handheld computer
*
* based on tosa_battery.c
*
* Copyright (C) 2008 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/power_supply.h>
#include <linux/wm97xx.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <asm/mach-types.h>
#include <asm/arch/palmtx.h>
static DEFINE_MUTEX(bat_lock);
static struct work_struct bat_work;
struct mutex work_lock;
int bat_status = POWER_SUPPLY_STATUS_DISCHARGING;
static unsigned long palmtx_read_bat(struct power_supply *bat_ps)
{
return wm97xx_read_aux_adc(bat_ps->dev->parent->driver_data,
WM97XX_AUX_ID3) * 1000 / 414;
}
static unsigned long palmtx_read_temp(struct power_supply *bat_ps)
{
return wm97xx_read_aux_adc(bat_ps->dev->parent->driver_data,
WM97XX_AUX_ID2);
}
static int palmtx_bat_get_property(struct power_supply *bat_ps,
enum power_supply_property psp,
union power_supply_propval *val)
{
switch (psp) {
case POWER_SUPPLY_PROP_STATUS:
val->intval = bat_status;
break;
case POWER_SUPPLY_PROP_TECHNOLOGY:
val->intval = POWER_SUPPLY_TECHNOLOGY_LIPO;
break;
case POWER_SUPPLY_PROP_VOLTAGE_NOW:
val->intval = palmtx_read_bat(bat_ps);
break;
case POWER_SUPPLY_PROP_VOLTAGE_MAX:
case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
val->intval = PALMTX_BAT_MAX_VOLTAGE;
break;
case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
val->intval = PALMTX_BAT_MIN_VOLTAGE;
break;
case POWER_SUPPLY_PROP_TEMP:
val->intval = palmtx_read_temp(bat_ps);
break;
case POWER_SUPPLY_PROP_PRESENT:
val->intval = 1;
break;
default:
return -EINVAL;
}
return 0;
}
static void palmtx_bat_external_power_changed(struct power_supply *bat_ps)
{
schedule_work(&bat_work);
}
static char *status_text[] = {
[POWER_SUPPLY_STATUS_UNKNOWN] = "Unknown",
[POWER_SUPPLY_STATUS_CHARGING] = "Charging",
[POWER_SUPPLY_STATUS_DISCHARGING] = "Discharging",
};
static void palmtx_bat_update(struct power_supply *bat_ps)
{
int old_status = bat_status;
mutex_lock(&work_lock);
bat_status = gpio_get_value(GPIO_NR_PALMTX_POWER_DETECT) ?
POWER_SUPPLY_STATUS_CHARGING :
POWER_SUPPLY_STATUS_DISCHARGING;
if (old_status != bat_status) {
pr_debug("%s %s -> %s\n", bat_ps->name,
status_text[old_status],
status_text[bat_status]);
power_supply_changed(bat_ps);
}
mutex_unlock(&work_lock);
}
static enum power_supply_property palmtx_bat_main_props[] = {
POWER_SUPPLY_PROP_STATUS,
POWER_SUPPLY_PROP_TECHNOLOGY,
POWER_SUPPLY_PROP_VOLTAGE_NOW,
POWER_SUPPLY_PROP_VOLTAGE_MAX,
POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
POWER_SUPPLY_PROP_TEMP,
POWER_SUPPLY_PROP_PRESENT,
};
struct power_supply bat_ps = {
.name = "main-battery",
.type = POWER_SUPPLY_TYPE_BATTERY,
.properties = palmtx_bat_main_props,
.num_properties = ARRAY_SIZE(palmtx_bat_main_props),
.get_property = palmtx_bat_get_property,
.external_power_changed = palmtx_bat_external_power_changed,
.use_for_apm = 1,
};
static void palmtx_bat_work(struct work_struct *work)
{
palmtx_bat_update(&bat_ps);
}
#ifdef CONFIG_PM
static int palmtx_bat_suspend(struct platform_device *dev, pm_message_t state)
{
flush_scheduled_work();
return 0;
}
static int palmtx_bat_resume(struct platform_device *dev)
{
schedule_work(&bat_work);
return 0;
}
#else
#define palmtx_bat_suspend NULL
#define palmtx_bat_resume NULL
#endif
static int __devinit palmtx_bat_probe(struct platform_device *dev)
{
int ret = 0;
if (!machine_is_palmtx())
return -ENODEV;
mutex_init(&work_lock);
INIT_WORK(&bat_work, palmtx_bat_work);
ret = power_supply_register(&dev->dev, &bat_ps);
if (!ret)
schedule_work(&bat_work);
return ret;
}
static int __devexit palmtx_bat_remove(struct platform_device *dev)
{
power_supply_unregister(&bat_ps);
return 0;
}
static struct platform_driver palmtx_bat_driver = {
.driver.name = "wm97xx-battery",
.driver.owner = THIS_MODULE,
.probe = palmtx_bat_probe,
.remove = __devexit_p(palmtx_bat_remove),
.suspend = palmtx_bat_suspend,
.resume = palmtx_bat_resume,
};
static int __init palmtx_bat_init(void)
{
return platform_driver_register(&palmtx_bat_driver);
}
static void __exit palmtx_bat_exit(void)
{
platform_driver_unregister(&palmtx_bat_driver);
}
module_init(palmtx_bat_init);
module_exit(palmtx_bat_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
MODULE_DESCRIPTION("Palm T|X battery driver");
drivers/usb/gadget/pxa25x_udc.c
View file @ 30d38542
......@@ -152,9 +152,10 @@ static int is_vbus_present(void)
static void pullup_off(void)
{
struct pxa2xx_udc_mach_info *mach = the_controller->mach;
int off_level = mach->gpio_pullup_inverted;
if (mach->gpio_pullup)
gpio_set_value(mach->gpio_pullup, 0);
gpio_set_value(mach->gpio_pullup, off_level);
else if (mach->udc_command)
mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
}
......@@ -162,9 +163,10 @@ static void pullup_off(void)
static void pullup_on(void)
{
struct pxa2xx_udc_mach_info *mach = the_controller->mach;
int on_level = !mach->gpio_pullup_inverted;
if (mach->gpio_pullup)
gpio_set_value(mach->gpio_pullup, 1);
gpio_set_value(mach->gpio_pullup, on_level);
else if (mach->udc_command)
mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
}
......
drivers/video/pxafb.c
View file @ 30d38542
......@@ -227,6 +227,22 @@ static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
case 4: ret = LCCR3_4BPP; break;
case 8: ret = LCCR3_8BPP; break;
case 16: ret = LCCR3_16BPP; break;
case 24:
switch (var->red.length + var->green.length +
var->blue.length + var->transp.length) {
case 18: ret = LCCR3_18BPP_P | LCCR3_PDFOR_3; break;
case 19: ret = LCCR3_19BPP_P; break;
}
break;
case 32:
switch (var->red.length + var->green.length +
var->blue.length + var->transp.length) {
case 18: ret = LCCR3_18BPP | LCCR3_PDFOR_3; break;
case 19: ret = LCCR3_19BPP; break;
case 24: ret = LCCR3_24BPP | LCCR3_PDFOR_3; break;
case 25: ret = LCCR3_25BPP; break;
}
break;
}
return ret;
}
......@@ -345,6 +361,41 @@ static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
var->green.offset = 5; var->green.length = 6;
var->blue.offset = 0; var->blue.length = 5;
var->transp.offset = var->transp.length = 0;
} else if (var->bits_per_pixel > 16) {
struct pxafb_mode_info *mode;
mode = pxafb_getmode(inf, var);
if (!mode)
return -EINVAL;
switch (mode->depth) {
case 18: /* RGB666 */
var->transp.offset = var->transp.length = 0;
var->red.offset = 12; var->red.length = 6;
var->green.offset = 6; var->green.length = 6;
var->blue.offset = 0; var->blue.length = 6;
break;
case 19: /* RGBT666 */
var->transp.offset = 18; var->transp.length = 1;
var->red.offset = 12; var->red.length = 6;
var->green.offset = 6; var->green.length = 6;
var->blue.offset = 0; var->blue.length = 6;
break;
case 24: /* RGB888 */
var->transp.offset = var->transp.length = 0;
var->red.offset = 16; var->red.length = 8;
var->green.offset = 8; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
break;
case 25: /* RGBT888 */
var->transp.offset = 24; var->transp.length = 1;
var->red.offset = 16; var->red.length = 8;
var->green.offset = 8; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
break;
default:
return -EINVAL;
}
} else {
var->red.offset = var->green.offset = 0;
var->blue.offset = var->transp.offset = 0;
......@@ -376,7 +427,7 @@ static int pxafb_set_par(struct fb_info *info)
struct pxafb_info *fbi = (struct pxafb_info *)info;
struct fb_var_screeninfo *var = &info->var;
if (var->bits_per_pixel == 16)
if (var->bits_per_pixel >= 16)
fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
else if (!fbi->cmap_static)
fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
......@@ -391,7 +442,7 @@ static int pxafb_set_par(struct fb_info *info)
fbi->fb.fix.line_length = var->xres_virtual *
var->bits_per_pixel / 8;
if (var->bits_per_pixel == 16)
if (var->bits_per_pixel >= 16)
fbi->palette_size = 0;
else
fbi->palette_size = var->bits_per_pixel == 1 ?
......@@ -404,7 +455,7 @@ static int pxafb_set_par(struct fb_info *info)
*/
pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
if (fbi->fb.var.bits_per_pixel == 16)
if (fbi->fb.var.bits_per_pixel >= 16)
fb_dealloc_cmap(&fbi->fb.cmap);
else
fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
......@@ -831,6 +882,8 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var,
case 4:
case 8:
case 16:
case 24:
case 32:
break;
default:
printk(KERN_ERR "%s: invalid bit depth %d\n",
......@@ -968,6 +1021,11 @@ static void pxafb_setup_gpio(struct pxafb_info *fbi)
for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
/* 18 bit interface */
if (fbi->fb.var.bits_per_pixel > 16) {
pxa_gpio_mode(86 | GPIO_ALT_FN_2_OUT);
pxa_gpio_mode(87 | GPIO_ALT_FN_2_OUT);
}
pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
......
include/asm-arm/arch-pxa/cm-x270.h deleted 100644 → 0
View file @ 20b7997e
/*
* linux/include/asm/arch-pxa/cm-x270.h
*
* Copyright Compulab Ltd., 2003, 2007
* Mike Rapoport <mike@compulab.co.il>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* CM-x270 device physical addresses */
#define CMX270_CS1_PHYS (PXA_CS1_PHYS)
#define MARATHON_PHYS (PXA_CS2_PHYS)
#define CMX270_IDE104_PHYS (PXA_CS3_PHYS)
#define CMX270_IT8152_PHYS (PXA_CS4_PHYS)
/* Statically mapped regions */
#define CMX270_VIRT_BASE (0xe8000000)
#define CMX270_IT8152_VIRT (CMX270_VIRT_BASE)
#define CMX270_IDE104_VIRT (CMX270_IT8152_VIRT + SZ_64M)
/* GPIO related definitions */
#define GPIO_IT8152_IRQ (22)
#define IRQ_GPIO_IT8152_IRQ IRQ_GPIO(GPIO_IT8152_IRQ)
#define PME_IRQ IRQ_GPIO(0)
#define CMX270_IDE_IRQ IRQ_GPIO(100)
#define CMX270_GPIRQ1 IRQ_GPIO(101)
#define CMX270_TOUCHIRQ IRQ_GPIO(96)
#define CMX270_ETHIRQ IRQ_GPIO(10)
#define CMX270_GFXIRQ IRQ_GPIO(95)
#define CMX270_NANDIRQ IRQ_GPIO(89)
#define CMX270_MMC_IRQ IRQ_GPIO(83)
/* PCMCIA related definitions */
#define PCC_DETECT(x) (GPLR(84 - (x)) & GPIO_bit(84 - (x)))
#define PCC_READY(x) (GPLR(82 - (x)) & GPIO_bit(82 - (x)))
#define PCMCIA_S0_CD_VALID IRQ_GPIO(84)
#define PCMCIA_S0_CD_VALID_EDGE GPIO_BOTH_EDGES
#define PCMCIA_S1_CD_VALID IRQ_GPIO(83)
#define PCMCIA_S1_CD_VALID_EDGE GPIO_BOTH_EDGES
#define PCMCIA_S0_RDYINT IRQ_GPIO(82)
#define PCMCIA_S1_RDYINT IRQ_GPIO(81)
#define PCMCIA_RESET_GPIO 53
include/asm-arm/arch-pxa/eseries-gpio.h 0 → 100644
View file @ 30d38542
/*
* eseries-gpio.h
*
* Copyright (C) Ian Molton <spyro@f2s.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/* e-series power button */
#define GPIO_ESERIES_POWERBTN 0
/* UDC GPIO definitions */
#define GPIO_E7XX_USB_DISC 13
#define GPIO_E7XX_USB_PULLUP 3
#define GPIO_E800_USB_DISC 4
#define GPIO_E800_USB_PULLUP 84
/* e740 PCMCIA GPIO definitions */
/* Note: PWR1 seems to be inverted */
#define GPIO_E740_PCMCIA_CD0 8
#define GPIO_E740_PCMCIA_CD1 44
#define GPIO_E740_PCMCIA_RDY0 11
#define GPIO_E740_PCMCIA_RDY1 6
#define GPIO_E740_PCMCIA_RST0 27
#define GPIO_E740_PCMCIA_RST1 24
#define GPIO_E740_PCMCIA_PWR0 20
#define GPIO_E740_PCMCIA_PWR1 23
/* e750 PCMCIA GPIO definitions */
#define GPIO_E750_PCMCIA_CD0 8
#define GPIO_E750_PCMCIA_RDY0 12
#define GPIO_E750_PCMCIA_RST0 27
#define GPIO_E750_PCMCIA_PWR0 20
/* e800 PCMCIA GPIO definitions */
#define GPIO_E800_PCMCIA_RST0 69
#define GPIO_E800_PCMCIA_RST1 72
#define GPIO_E800_PCMCIA_PWR0 20
#define GPIO_E800_PCMCIA_PWR1 73
/* e7xx IrDA power control */
#define GPIO_E7XX_IR_ON 38
/* ASIC related GPIOs */
#define GPIO_ESERIES_TMIO_IRQ 5
#define GPIO_E800_ANGELX_IRQ 8
include/asm-arm/arch-pxa/eseries-irq.h 0 → 100644
View file @ 30d38542
/*
* eseries-irq.h
*
* Copyright (C) Ian Molton <spyro@f2s.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#define ANGELX_IRQ_BASE (IRQ_BOARD_START+8)
#define IRQ_ANGELX(n) (ANGELX_IRQ_BASE + (n))
#define ANGELX_RDY0_IRQ IRQ_ANGELX(0)
#define ANGELX_ST0_IRQ IRQ_ANGELX(1)
#define ANGELX_CD0_IRQ IRQ_ANGELX(2)
#define ANGELX_RDY1_IRQ IRQ_ANGELX(3)
#define ANGELX_ST1_IRQ IRQ_ANGELX(4)
#define ANGELX_CD1_IRQ IRQ_ANGELX(5)
#define TMIO_IRQ_BASE (IRQ_BOARD_START+0)
#define IRQ_TMIO(n) (TMIO_IRQ_BASE + (n))
#define TMIO_SD_IRQ IRQ_TMIO(1)
#define TMIO_USB_IRQ IRQ_TMIO(2)
include/asm-arm/arch-pxa/hardware.h
View file @ 30d38542
......@@ -69,6 +69,12 @@
_id == 0x212; \
})
#define __cpu_is_pxa255(id) \
({ \
unsigned int _id = (id) >> 4 & 0xfff; \
_id == 0x2d0; \
})
#define __cpu_is_pxa25x(id) \
({ \
unsigned int _id = (id) >> 4 & 0xfff; \
......@@ -76,6 +82,7 @@
})
#else
#define __cpu_is_pxa21x(id) (0)
#define __cpu_is_pxa255(id) (0)
#define __cpu_is_pxa25x(id) (0)
#endif
......@@ -119,11 +126,26 @@
#define __cpu_is_pxa320(id) (0)
#endif
#ifdef CONFIG_CPU_PXA930
#define __cpu_is_pxa930(id) \
({ \
unsigned int _id = (id) >> 4 & 0xfff; \
_id == 0x683; \
})
#else
#define __cpu_is_pxa930(id) (0)
#endif
#define cpu_is_pxa21x() \
({ \
__cpu_is_pxa21x(read_cpuid_id()); \
})
#define cpu_is_pxa255() \
({ \
__cpu_is_pxa255(read_cpuid_id()); \
})
#define cpu_is_pxa25x() \
({ \
__cpu_is_pxa25x(read_cpuid_id()); \
......@@ -149,6 +171,12 @@
__cpu_is_pxa320(read_cpuid_id()); \
})
#define cpu_is_pxa930() \
({ \
unsigned int id = read_cpuid(CPUID_ID); \
__cpu_is_pxa930(id); \
})
/*
* CPUID Core Generation Bit
* <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
......@@ -196,6 +224,11 @@ extern void pxa_gpio_set_value(unsigned gpio, int value);
*/
extern unsigned int get_memclk_frequency_10khz(void);
/*
* register GPIO as reset generator
*/
extern int init_gpio_reset(int gpio);
#endif
#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
......
include/asm-arm/arch-pxa/irqs.h
View file @ 30d38542
......@@ -180,10 +180,13 @@
#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1)
#elif defined(CONFIG_ARCH_LUBBOCK) || \
defined(CONFIG_MACH_LOGICPD_PXA270) || \
defined(CONFIG_MACH_TOSA) || \
defined(CONFIG_MACH_MAINSTONE) || \
defined(CONFIG_MACH_PCM027) || \
defined(CONFIG_MACH_MAGICIAN)
#define NR_IRQS (IRQ_BOARD_END)
#elif defined(CONFIG_MACH_ZYLONITE)
#define NR_IRQS (IRQ_BOARD_START + 32)
#else
#define NR_IRQS (IRQ_BOARD_START)
#endif
......
include/asm-arm/arch-pxa/mfp-pxa2xx.h
View file @ 30d38542
......@@ -128,5 +128,6 @@
#define GPIO84_GPIO MFP_CFG_IN(GPIO84, AF0)
extern void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num);
extern void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm);
extern int gpio_set_wake(unsigned int gpio, unsigned int on);
#endif /* __ASM_ARCH_MFP_PXA2XX_H */
include/asm-arm/arch-pxa/mfp-pxa930.h 0 → 100644
View file @ 30d38542
/*
* linux/include/asm-arm/arch-pxa/mfp-pxa930.h
*
* PXA930 specific MFP configuration definitions
*
* Copyright (C) 2007-2008 Marvell International Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MFP_PXA9xx_H
#define __ASM_ARCH_MFP_PXA9xx_H
#include <asm/arch/mfp.h>
#include <asm/arch/mfp-pxa3xx.h>
/* GPIO */
#define GPIO46_GPIO MFP_CFG(GPIO46, AF0)
#define GPIO49_GPIO MFP_CFG(GPIO49, AF0)
#define GPIO50_GPIO MFP_CFG(GPIO50, AF0)
#define GPIO51_GPIO MFP_CFG(GPIO51, AF0)
#define GPIO52_GPIO MFP_CFG(GPIO52, AF0)
#define GPIO56_GPIO MFP_CFG(GPIO56, AF0)
#define GPIO58_GPIO MFP_CFG(GPIO58, AF0)
#define GPIO59_GPIO MFP_CFG(GPIO59, AF0)
#define GPIO60_GPIO MFP_CFG(GPIO60, AF0)
#define GPIO61_GPIO MFP_CFG(GPIO61, AF0)
#define GPIO62_GPIO MFP_CFG(GPIO62, AF0)
#define GSIM_UCLK_GPIO_79 MFP_CFG(GSIM_UCLK, AF0)
#define GSIM_UIO_GPIO_80 MFP_CFG(GSIM_UIO, AF0)
#define GSIM_nURST_GPIO_81 MFP_CFG(GSIM_nURST, AF0)
#define GSIM_UDET_GPIO_82 MFP_CFG(GSIM_UDET, AF0)
#define DF_IO15_GPIO_28 MFP_CFG(DF_IO15, AF0)
#define DF_IO14_GPIO_29 MFP_CFG(DF_IO14, AF0)
#define DF_IO13_GPIO_30 MFP_CFG(DF_IO13, AF0)
#define DF_IO12_GPIO_31 MFP_CFG(DF_IO12, AF0)
#define DF_IO11_GPIO_32 MFP_CFG(DF_IO11, AF0)
#define DF_IO10_GPIO_33 MFP_CFG(DF_IO10, AF0)
#define DF_IO9_GPIO_34 MFP_CFG(DF_IO9, AF0)
#define DF_IO8_GPIO_35 MFP_CFG(DF_IO8, AF0)
#define DF_IO7_GPIO_36 MFP_CFG(DF_IO7, AF0)
#define DF_IO6_GPIO_37 MFP_CFG(DF_IO6, AF0)
#define DF_IO5_GPIO_38 MFP_CFG(DF_IO5, AF0)
#define DF_IO4_GPIO_39 MFP_CFG(DF_IO4, AF0)
#define DF_IO3_GPIO_40 MFP_CFG(DF_IO3, AF0)
#define DF_IO2_GPIO_41 MFP_CFG(DF_IO2, AF0)
#define DF_IO1_GPIO_42 MFP_CFG(DF_IO1, AF0)
#define DF_IO0_GPIO_43 MFP_CFG(DF_IO0, AF0)
#define DF_nCS0_GPIO_44 MFP_CFG(DF_nCS0, AF0)
#define DF_nCS1_GPIO_45 MFP_CFG(DF_nCS1, AF0)
#define DF_nWE_GPIO_46 MFP_CFG(DF_nWE, AF0)
#define DF_nRE_nOE_GPIO_47 MFP_CFG(DF_nRE_nOE, AF0)
#define DF_CLE_nOE_GPIO_48 MFP_CFG(DF_CLE_nOE, AF0)
#define DF_nADV1_ALE_GPIO_49 MFP_CFG(DF_nADV1_ALE, AF0)
#define DF_nADV2_ALE_GPIO_50 MFP_CFG(DF_nADV2_ALE, AF0)
#define DF_INT_RnB_GPIO_51 MFP_CFG(DF_INT_RnB, AF0)
#define DF_SCLK_E_GPIO_52 MFP_CFG(DF_SCLK_E, AF0)
#define DF_ADDR0_GPIO_53 MFP_CFG(DF_ADDR0, AF0)
#define DF_ADDR1_GPIO_54 MFP_CFG(DF_ADDR1, AF0)
#define DF_ADDR2_GPIO_55 MFP_CFG(DF_ADDR2, AF0)
#define DF_ADDR3_GPIO_56 MFP_CFG(DF_ADDR3, AF0)
#define nXCVREN_GPIO_57 MFP_CFG(nXCVREN, AF0)
#define nLUA_GPIO_58 MFP_CFG(nLUA, AF0)
#define nLLA_GPIO_59 MFP_CFG(nLLA, AF0)
#define nBE0_GPIO_60 MFP_CFG(nBE0, AF0)
#define nBE1_GPIO_61 MFP_CFG(nBE1, AF0)
#define RDY_GPIO_62 MFP_CFG(RDY, AF0)
/* Chip Select */
#define DF_nCS0_nCS2 MFP_CFG_LPM(DF_nCS0, AF3, PULL_HIGH)
#define DF_nCS1_nCS3 MFP_CFG_LPM(DF_nCS1, AF3, PULL_HIGH)
/* AC97 */
#define GPIO83_BAC97_SYSCLK MFP_CFG(GPIO83, AF3)
#define GPIO84_BAC97_SDATA_IN0 MFP_CFG(GPIO84, AF3)
#define GPIO85_BAC97_BITCLK MFP_CFG(GPIO85, AF3)
#define GPIO86_BAC97_nRESET MFP_CFG(GPIO86, AF3)
#define GPIO87_BAC97_SYNC MFP_CFG(GPIO87, AF3)
#define GPIO88_BAC97_SDATA_OUT MFP_CFG(GPIO88, AF3)
/* I2C */
#define GPIO39_CI2C_SCL MFP_CFG_LPM(GPIO39, AF3, PULL_HIGH)
#define GPIO40_CI2C_SDA MFP_CFG_LPM(GPIO40, AF3, PULL_HIGH)
#define GPIO51_CI2C_SCL MFP_CFG_LPM(GPIO51, AF3, PULL_HIGH)
#define GPIO52_CI2C_SDA MFP_CFG_LPM(GPIO52, AF3, PULL_HIGH)
#define GPIO63_CI2C_SCL MFP_CFG_LPM(GPIO63, AF4, PULL_HIGH)
#define GPIO64_CI2C_SDA MFP_CFG_LPM(GPIO64, AF4, PULL_HIGH)
#define GPIO77_CI2C_SCL MFP_CFG_LPM(GPIO77, AF2, PULL_HIGH)
#define GPIO78_CI2C_SDA MFP_CFG_LPM(GPIO78, AF2, PULL_HIGH)
#define GPIO89_CI2C_SCL MFP_CFG_LPM(GPIO89, AF1, PULL_HIGH)
#define GPIO90_CI2C_SDA MFP_CFG_LPM(GPIO90, AF1, PULL_HIGH)
#define GPIO95_CI2C_SCL MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
#define GPIO96_CI2C_SDA MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
#define GPIO97_CI2C_SCL MFP_CFG_LPM(GPIO97, AF3, PULL_HIGH)
#define GPIO98_CI2C_SDA MFP_CFG_LPM(GPIO98, AF3, PULL_HIGH)
/* QCI */
#define GPIO63_CI_DD_9 MFP_CFG_LPM(GPIO63, AF1, PULL_LOW)
#define GPIO64_CI_DD_8 MFP_CFG_LPM(GPIO64, AF1, PULL_LOW)
#define GPIO65_CI_DD_7 MFP_CFG_LPM(GPIO65, AF1, PULL_LOW)
#define GPIO66_CI_DD_6 MFP_CFG_LPM(GPIO66, AF1, PULL_LOW)
#define GPIO67_CI_DD_5 MFP_CFG_LPM(GPIO67, AF1, PULL_LOW)
#define GPIO68_CI_DD_4 MFP_CFG_LPM(GPIO68, AF1, PULL_LOW)
#define GPIO69_CI_DD_3 MFP_CFG_LPM(GPIO69, AF1, PULL_LOW)
#define GPIO70_CI_DD_2 MFP_CFG_LPM(GPIO70, AF1, PULL_LOW)
#define GPIO71_CI_DD_1 MFP_CFG_LPM(GPIO71, AF1, PULL_LOW)
#define GPIO72_CI_DD_0 MFP_CFG_LPM(GPIO72, AF1, PULL_LOW)
#define GPIO73_CI_HSYNC MFP_CFG_LPM(GPIO73, AF1, PULL_LOW)
#define GPIO74_CI_VSYNC MFP_CFG_LPM(GPIO74, AF1, PULL_LOW)
#define GPIO75_CI_MCLK MFP_CFG_LPM(GPIO75, AF1, PULL_LOW)
#define GPIO76_CI_PCLK MFP_CFG_LPM(GPIO76, AF1, PULL_LOW)
/* KEYPAD */
#define GPIO4_KP_DKIN_4 MFP_CFG_LPM(GPIO4, AF3, FLOAT)
#define GPIO5_KP_DKIN_5 MFP_CFG_LPM(GPIO5, AF3, FLOAT)
#define GPIO6_KP_DKIN_6 MFP_CFG_LPM(GPIO6, AF3, FLOAT)
#define GPIO7_KP_DKIN_7 MFP_CFG_LPM(GPIO7, AF3, FLOAT)
#define GPIO8_KP_DKIN_4 MFP_CFG_LPM(GPIO8, AF3, FLOAT)
#define GPIO9_KP_DKIN_5 MFP_CFG_LPM(GPIO9, AF3, FLOAT)
#define GPIO10_KP_DKIN_6 MFP_CFG_LPM(GPIO10, AF3, FLOAT)
#define GPIO11_KP_DKIN_7 MFP_CFG_LPM(GPIO11, AF3, FLOAT)
#define GPIO12_KP_DKIN_0 MFP_CFG_LPM(GPIO12, AF2, FLOAT)
#define GPIO13_KP_DKIN_1 MFP_CFG_LPM(GPIO13, AF2, FLOAT)
#define GPIO14_KP_DKIN_2 MFP_CFG_LPM(GPIO14, AF2, FLOAT)
#define GPIO15_KP_DKIN_3 MFP_CFG_LPM(GPIO15, AF2, FLOAT)
#define GPIO41_KP_DKIN_0 MFP_CFG_LPM(GPIO41, AF2, FLOAT)
#define GPIO42_KP_DKIN_1 MFP_CFG_LPM(GPIO42, AF2, FLOAT)
#define GPIO43_KP_DKIN_2 MFP_CFG_LPM(GPIO43, AF2, FLOAT)
#define GPIO44_KP_DKIN_3 MFP_CFG_LPM(GPIO44, AF2, FLOAT)
#define GPIO41_KP_DKIN_4 MFP_CFG_LPM(GPIO41, AF4, FLOAT)
#define GPIO42_KP_DKIN_5 MFP_CFG_LPM(GPIO42, AF4, FLOAT)
#define GPIO0_KP_MKIN_0 MFP_CFG_LPM(GPIO0, AF1, FLOAT)
#define GPIO2_KP_MKIN_1 MFP_CFG_LPM(GPIO2, AF1, FLOAT)
#define GPIO4_KP_MKIN_2 MFP_CFG_LPM(GPIO4, AF1, FLOAT)
#define GPIO6_KP_MKIN_3 MFP_CFG_LPM(GPIO6, AF1, FLOAT)
#define GPIO8_KP_MKIN_4 MFP_CFG_LPM(GPIO8, AF1, FLOAT)
#define GPIO10_KP_MKIN_5 MFP_CFG_LPM(GPIO10, AF1, FLOAT)
#define GPIO12_KP_MKIN_6 MFP_CFG_LPM(GPIO12, AF1, FLOAT)
#define GPIO14_KP_MKIN_7 MFP_CFG(GPIO14, AF1)
#define GPIO35_KP_MKIN_5 MFP_CFG(GPIO35, AF4)
#define GPIO1_KP_MKOUT_0 MFP_CFG_LPM(GPIO1, AF1, DRIVE_HIGH)
#define GPIO3_KP_MKOUT_1 MFP_CFG_LPM(GPIO3, AF1, DRIVE_HIGH)
#define GPIO5_KP_MKOUT_2 MFP_CFG_LPM(GPIO5, AF1, DRIVE_HIGH)
#define GPIO7_KP_MKOUT_3 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH)
#define GPIO9_KP_MKOUT_4 MFP_CFG_LPM(GPIO9, AF1, DRIVE_HIGH)
#define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF1, DRIVE_HIGH)
#define GPIO13_KP_MKOUT_6 MFP_CFG_LPM(GPIO13, AF1, DRIVE_HIGH)
#define GPIO15_KP_MKOUT_7 MFP_CFG_LPM(GPIO15, AF1, DRIVE_HIGH)
#define GPIO36_KP_MKOUT_5 MFP_CFG_LPM(GPIO36, AF4, DRIVE_HIGH)
/* LCD */
#define GPIO17_LCD_FCLK_RD MFP_CFG(GPIO17, AF1)
#define GPIO18_LCD_LCLK_A0 MFP_CFG(GPIO18, AF1)
#define GPIO19_LCD_PCLK_WR MFP_CFG(GPIO19, AF1)
#define GPIO20_LCD_BIAS MFP_CFG(GPIO20, AF1)
#define GPIO21_LCD_CS MFP_CFG(GPIO21, AF1)
#define GPIO22_LCD_CS2 MFP_CFG(GPIO22, AF2)
#define GPIO22_LCD_VSYNC MFP_CFG(GPIO22, AF1)
#define GPIO23_LCD_DD0 MFP_CFG(GPIO23, AF1)
#define GPIO24_LCD_DD1 MFP_CFG(GPIO24, AF1)
#define GPIO25_LCD_DD2 MFP_CFG(GPIO25, AF1)
#define GPIO26_LCD_DD3 MFP_CFG(GPIO26, AF1)
#define GPIO27_LCD_DD4 MFP_CFG(GPIO27, AF1)
#define GPIO28_LCD_DD5 MFP_CFG(GPIO28, AF1)
#define GPIO29_LCD_DD6 MFP_CFG(GPIO29, AF1)
#define GPIO30_LCD_DD7 MFP_CFG(GPIO30, AF1)
#define GPIO31_LCD_DD8 MFP_CFG(GPIO31, AF1)
#define GPIO32_LCD_DD9 MFP_CFG(GPIO32, AF1)
#define GPIO33_LCD_DD10 MFP_CFG(GPIO33, AF1)
#define GPIO34_LCD_DD11 MFP_CFG(GPIO34, AF1)
#define GPIO35_LCD_DD12 MFP_CFG(GPIO35, AF1)
#define GPIO36_LCD_DD13 MFP_CFG(GPIO36, AF1)
#define GPIO37_LCD_DD14 MFP_CFG(GPIO37, AF1)
#define GPIO38_LCD_DD15 MFP_CFG(GPIO38, AF1)
#define GPIO39_LCD_DD16 MFP_CFG(GPIO39, AF1)
#define GPIO40_LCD_DD17 MFP_CFG(GPIO40, AF1)
#define GPIO41_LCD_CS2 MFP_CFG(GPIO41, AF3)
#define GPIO42_LCD_VSYNC2 MFP_CFG(GPIO42, AF3)
#define GPIO44_LCD_DD7 MFP_CFG(GPIO44, AF1)
/* Mini-LCD */
#define GPIO17_MLCD_FCLK MFP_CFG(GPIO17, AF3)
#define GPIO18_MLCD_LCLK MFP_CFG(GPIO18, AF3)
#define GPIO19_MLCD_PCLK MFP_CFG(GPIO19, AF3)
#define GPIO20_MLCD_BIAS MFP_CFG(GPIO20, AF3)
#define GPIO23_MLCD_DD0 MFP_CFG(GPIO23, AF3)
#define GPIO24_MLCD_DD1 MFP_CFG(GPIO24, AF3)
#define GPIO25_MLCD_DD2 MFP_CFG(GPIO25, AF3)
#define GPIO26_MLCD_DD3 MFP_CFG(GPIO26, AF3)
#define GPIO27_MLCD_DD4 MFP_CFG(GPIO27, AF3)
#define GPIO28_MLCD_DD5 MFP_CFG(GPIO28, AF3)
#define GPIO29_MLCD_DD6 MFP_CFG(GPIO29, AF3)
#define GPIO30_MLCD_DD7 MFP_CFG(GPIO30, AF3)
#define GPIO31_MLCD_DD8 MFP_CFG(GPIO31, AF3)
#define GPIO32_MLCD_DD9 MFP_CFG(GPIO32, AF3)
#define GPIO33_MLCD_DD10 MFP_CFG(GPIO33, AF3)
#define GPIO34_MLCD_DD11 MFP_CFG(GPIO34, AF3)
#define GPIO35_MLCD_DD12 MFP_CFG(GPIO35, AF3)
#define GPIO36_MLCD_DD13 MFP_CFG(GPIO36, AF3)
#define GPIO37_MLCD_DD14 MFP_CFG(GPIO37, AF3)
#define GPIO38_MLCD_DD15 MFP_CFG(GPIO38, AF3)
#define GPIO44_MLCD_DD7 MFP_CFG(GPIO44, AF5)
/* MMC1 */
#define GPIO10_MMC1_DAT3 MFP_CFG(GPIO10, AF4)
#define GPIO11_MMC1_DAT2 MFP_CFG(GPIO11, AF4)
#define GPIO12_MMC1_DAT1 MFP_CFG(GPIO12, AF4)
#define GPIO13_MMC1_DAT0 MFP_CFG(GPIO13, AF4)
#define GPIO14_MMC1_CMD MFP_CFG(GPIO14, AF4)
#define GPIO15_MMC1_CLK MFP_CFG(GPIO15, AF4)
#define GPIO55_MMC1_CMD MFP_CFG(GPIO55, AF3)
#define GPIO56_MMC1_CLK MFP_CFG(GPIO56, AF3)
#define GPIO57_MMC1_DAT0 MFP_CFG(GPIO57, AF3)
#define GPIO58_MMC1_DAT1 MFP_CFG(GPIO58, AF3)
#define GPIO59_MMC1_DAT2 MFP_CFG(GPIO59, AF3)
#define GPIO60_MMC1_DAT3 MFP_CFG(GPIO60, AF3)
#define DF_ADDR0_MMC1_CLK MFP_CFG(DF_ADDR0, AF2)
#define DF_ADDR1_MMC1_CMD MFP_CFG(DF_ADDR1, AF2)
#define DF_ADDR2_MMC1_DAT0 MFP_CFG(DF_ADDR2, AF2)
#define DF_ADDR3_MMC1_DAT1 MFP_CFG(DF_ADDR3, AF3)
#define nXCVREN_MMC1_DAT2 MFP_CFG(nXCVREN, AF2)
/* MMC2 */
#define GPIO31_MMC2_CMD MFP_CFG(GPIO31, AF7)
#define GPIO32_MMC2_CLK MFP_CFG(GPIO32, AF7)
#define GPIO33_MMC2_DAT0 MFP_CFG(GPIO33, AF7)
#define GPIO34_MMC2_DAT1 MFP_CFG(GPIO34, AF7)
#define GPIO35_MMC2_DAT2 MFP_CFG(GPIO35, AF7)
#define GPIO36_MMC2_DAT3 MFP_CFG(GPIO36, AF7)
#define GPIO101_MMC2_DAT3 MFP_CFG(GPIO101, AF1)
#define GPIO102_MMC2_DAT2 MFP_CFG(GPIO102, AF1)
#define GPIO103_MMC2_DAT1 MFP_CFG(GPIO103, AF1)
#define GPIO104_MMC2_DAT0 MFP_CFG(GPIO104, AF1)
#define GPIO105_MMC2_CMD MFP_CFG(GPIO105, AF1)
#define GPIO106_MMC2_CLK MFP_CFG(GPIO106, AF1)
#define DF_IO10_MMC2_DAT3 MFP_CFG(DF_IO10, AF3)
#define DF_IO11_MMC2_DAT2 MFP_CFG(DF_IO11, AF3)
#define DF_IO12_MMC2_DAT1 MFP_CFG(DF_IO12, AF3)
#define DF_IO13_MMC2_DAT0 MFP_CFG(DF_IO13, AF3)
#define DF_IO14_MMC2_CLK MFP_CFG(DF_IO14, AF3)
#define DF_IO15_MMC2_CMD MFP_CFG(DF_IO15, AF3)
/* BSSP1 */
#define GPIO12_BSSP1_CLK MFP_CFG(GPIO12, AF3)
#define GPIO13_BSSP1_FRM MFP_CFG(GPIO13, AF3)
#define GPIO14_BSSP1_RXD MFP_CFG(GPIO14, AF3)
#define GPIO15_BSSP1_TXD MFP_CFG(GPIO15, AF3)
#define GPIO97_BSSP1_CLK MFP_CFG(GPIO97, AF5)
#define GPIO98_BSSP1_FRM MFP_CFG(GPIO98, AF5)
/* BSSP2 */
#define GPIO84_BSSP2_SDATA_IN MFP_CFG(GPIO84, AF1)
#define GPIO85_BSSP2_BITCLK MFP_CFG(GPIO85, AF1)
#define GPIO86_BSSP2_SYSCLK MFP_CFG(GPIO86, AF1)
#define GPIO87_BSSP2_SYNC MFP_CFG(GPIO87, AF1)
#define GPIO88_BSSP2_DATA_OUT MFP_CFG(GPIO88, AF1)
#define GPIO86_BSSP2_SDATA_IN MFP_CFG(GPIO86, AF4)
/* BSSP3 */
#define GPIO79_BSSP3_CLK MFP_CFG(GPIO79, AF1)
#define GPIO80_BSSP3_FRM MFP_CFG(GPIO80, AF1)
#define GPIO81_BSSP3_TXD MFP_CFG(GPIO81, AF1)
#define GPIO82_BSSP3_RXD MFP_CFG(GPIO82, AF1)
#define GPIO83_BSSP3_SYSCLK MFP_CFG(GPIO83, AF1)
/* BSSP4 */
#define GPIO43_BSSP4_CLK MFP_CFG(GPIO43, AF4)
#define GPIO44_BSSP4_FRM MFP_CFG(GPIO44, AF4)
#define GPIO45_BSSP4_TXD MFP_CFG(GPIO45, AF4)
#define GPIO46_BSSP4_RXD MFP_CFG(GPIO46, AF4)
#define GPIO51_BSSP4_CLK MFP_CFG(GPIO51, AF4)
#define GPIO52_BSSP4_FRM MFP_CFG(GPIO52, AF4)
#define GPIO53_BSSP4_TXD MFP_CFG(GPIO53, AF4)
#define GPIO54_BSSP4_RXD MFP_CFG(GPIO54, AF4)
/* GSSP1 */
#define GPIO79_GSSP1_CLK MFP_CFG(GPIO79, AF2)
#define GPIO80_GSSP1_FRM MFP_CFG(GPIO80, AF2)
#define GPIO81_GSSP1_TXD MFP_CFG(GPIO81, AF2)
#define GPIO82_GSSP1_RXD MFP_CFG(GPIO82, AF2)
#define GPIO83_GSSP1_SYSCLK MFP_CFG(GPIO83, AF2)
#define GPIO93_GSSP1_CLK MFP_CFG(GPIO93, AF4)
#define GPIO94_GSSP1_FRM MFP_CFG(GPIO94, AF4)
#define GPIO95_GSSP1_TXD MFP_CFG(GPIO95, AF4)
#define GPIO96_GSSP1_RXD MFP_CFG(GPIO96, AF4)
/* GSSP2 */
#define GPIO47_GSSP2_CLK MFP_CFG(GPIO47, AF4)
#define GPIO48_GSSP2_FRM MFP_CFG(GPIO48, AF4)
#define GPIO49_GSSP2_RXD MFP_CFG(GPIO49, AF4)
#define GPIO50_GSSP2_TXD MFP_CFG(GPIO50, AF4)
#define GPIO69_GSSP2_CLK MFP_CFG(GPIO69, AF4)
#define GPIO70_GSSP2_FRM MFP_CFG(GPIO70, AF4)
#define GPIO71_GSSP2_RXD MFP_CFG(GPIO71, AF4)
#define GPIO72_GSSP2_TXD MFP_CFG(GPIO72, AF4)
#define GPIO84_GSSP2_RXD MFP_CFG(GPIO84, AF2)
#define GPIO85_GSSP2_CLK MFP_CFG(GPIO85, AF2)
#define GPIO86_GSSP2_SYSCLK MFP_CFG(GPIO86, AF2)
#define GPIO87_GSSP2_FRM MFP_CFG(GPIO87, AF2)
#define GPIO88_GSSP2_TXD MFP_CFG(GPIO88, AF2)
#define GPIO86_GSSP2_RXD MFP_CFG(GPIO86, AF5)
#define GPIO103_GSSP2_CLK MFP_CFG(GPIO103, AF2)
#define GPIO104_GSSP2_FRM MFP_CFG(GPIO104, AF2)
#define GPIO105_GSSP2_RXD MFP_CFG(GPIO105, AF2)
#define GPIO106_GSSP2_TXD MFP_CFG(GPIO106, AF2)
/* UART1 - FFUART */
#define GPIO47_UART1_DSR_N MFP_CFG(GPIO47, AF1)
#define GPIO48_UART1_DTR_N MFP_CFG(GPIO48, AF1)
#define GPIO49_UART1_RI MFP_CFG(GPIO49, AF1)
#define GPIO50_UART1_DCD MFP_CFG(GPIO50, AF1)
#define GPIO51_UART1_CTS MFP_CFG(GPIO51, AF1)
#define GPIO52_UART1_RTS MFP_CFG(GPIO52, AF1)
#define GPIO53_UART1_RXD MFP_CFG(GPIO53, AF1)
#define GPIO54_UART1_TXD MFP_CFG(GPIO54, AF1)
#define GPIO63_UART1_TXD MFP_CFG(GPIO63, AF2)
#define GPIO64_UART1_RXD MFP_CFG(GPIO64, AF2)
#define GPIO65_UART1_DSR MFP_CFG(GPIO65, AF2)
#define GPIO66_UART1_DTR MFP_CFG(GPIO66, AF2)
#define GPIO67_UART1_RI MFP_CFG(GPIO67, AF2)
#define GPIO68_UART1_DCD MFP_CFG(GPIO68, AF2)
#define GPIO69_UART1_CTS MFP_CFG(GPIO69, AF2)
#define GPIO70_UART1_RTS MFP_CFG(GPIO70, AF2)
/* UART2 - BTUART */
#define GPIO91_UART2_RXD MFP_CFG(GPIO91, AF1)
#define GPIO92_UART2_TXD MFP_CFG(GPIO92, AF1)
#define GPIO93_UART2_CTS MFP_CFG(GPIO93, AF1)
#define GPIO94_UART2_RTS MFP_CFG(GPIO94, AF1)
/* UART3 - STUART */
#define GPIO43_UART3_RTS MFP_CFG(GPIO43, AF3)
#define GPIO44_UART3_CTS MFP_CFG(GPIO44, AF3)
#define GPIO45_UART3_RXD MFP_CFG(GPIO45, AF3)
#define GPIO46_UART3_TXD MFP_CFG(GPIO46, AF3)
#define GPIO75_UART3_RTS MFP_CFG(GPIO75, AF5)
#define GPIO76_UART3_CTS MFP_CFG(GPIO76, AF5)
#define GPIO77_UART3_TXD MFP_CFG(GPIO77, AF5)
#define GPIO78_UART3_RXD MFP_CFG(GPIO78, AF5)
/* DFI */
#define DF_IO0_DF_IO0 MFP_CFG(DF_IO0, AF2)
#define DF_IO1_DF_IO1 MFP_CFG(DF_IO1, AF2)
#define DF_IO2_DF_IO2 MFP_CFG(DF_IO2, AF2)
#define DF_IO3_DF_IO3 MFP_CFG(DF_IO3, AF2)
#define DF_IO4_DF_IO4 MFP_CFG(DF_IO4, AF2)
#define DF_IO5_DF_IO5 MFP_CFG(DF_IO5, AF2)
#define DF_IO6_DF_IO6 MFP_CFG(DF_IO6, AF2)
#define DF_IO7_DF_IO7 MFP_CFG(DF_IO7, AF2)
#define DF_IO8_DF_IO8 MFP_CFG(DF_IO8, AF2)
#define DF_IO9_DF_IO9 MFP_CFG(DF_IO9, AF2)
#define DF_IO10_DF_IO10 MFP_CFG(DF_IO10, AF2)
#define DF_IO11_DF_IO11 MFP_CFG(DF_IO11, AF2)
#define DF_IO12_DF_IO12 MFP_CFG(DF_IO12, AF2)
#define DF_IO13_DF_IO13 MFP_CFG(DF_IO13, AF2)
#define DF_IO14_DF_IO14 MFP_CFG(DF_IO14, AF2)
#define DF_IO15_DF_IO15 MFP_CFG(DF_IO15, AF2)
#define DF_nADV1_ALE_DF_nADV1 MFP_CFG(DF_nADV1_ALE, AF2)
#define DF_nADV2_ALE_DF_nADV2 MFP_CFG(DF_nADV2_ALE, AF2)
#define DF_nCS0_DF_nCS0 MFP_CFG(DF_nCS0, AF2)
#define DF_nCS1_DF_nCS1 MFP_CFG(DF_nCS1, AF2)
#define DF_nRE_nOE_DF_nOE MFP_CFG(DF_nRE_nOE, AF2)
#define DF_nWE_DF_nWE MFP_CFG(DF_nWE, AF2)
/* DFI - NAND */
#define DF_CLE_nOE_ND_CLE MFP_CFG_LPM(DF_CLE_nOE, AF1, PULL_HIGH)
#define DF_INT_RnB_ND_INT_RnB MFP_CFG_LPM(DF_INT_RnB, AF1, PULL_LOW)
#define DF_IO0_ND_IO0 MFP_CFG_LPM(DF_IO0, AF1, PULL_LOW)
#define DF_IO1_ND_IO1 MFP_CFG_LPM(DF_IO1, AF1, PULL_LOW)
#define DF_IO2_ND_IO2 MFP_CFG_LPM(DF_IO2, AF1, PULL_LOW)
#define DF_IO3_ND_IO3 MFP_CFG_LPM(DF_IO3, AF1, PULL_LOW)
#define DF_IO4_ND_IO4 MFP_CFG_LPM(DF_IO4, AF1, PULL_LOW)
#define DF_IO5_ND_IO5 MFP_CFG_LPM(DF_IO5, AF1, PULL_LOW)
#define DF_IO6_ND_IO6 MFP_CFG_LPM(DF_IO6, AF1, PULL_LOW)
#define DF_IO7_ND_IO7 MFP_CFG_LPM(DF_IO7, AF1, PULL_LOW)
#define DF_IO8_ND_IO8 MFP_CFG_LPM(DF_IO8, AF1, PULL_LOW)
#define DF_IO9_ND_IO9 MFP_CFG_LPM(DF_IO9, AF1, PULL_LOW)
#define DF_IO10_ND_IO10 MFP_CFG_LPM(DF_IO10, AF1, PULL_LOW)
#define DF_IO11_ND_IO11 MFP_CFG_LPM(DF_IO11, AF1, PULL_LOW)
#define DF_IO12_ND_IO12 MFP_CFG_LPM(DF_IO12, AF1, PULL_LOW)
#define DF_IO13_ND_IO13 MFP_CFG_LPM(DF_IO13, AF1, PULL_LOW)
#define DF_IO14_ND_IO14 MFP_CFG_LPM(DF_IO14, AF1, PULL_LOW)
#define DF_IO15_ND_IO15 MFP_CFG_LPM(DF_IO15, AF1, PULL_LOW)
#define DF_nADV1_ALE_ND_ALE MFP_CFG_LPM(DF_nADV1_ALE, AF1, PULL_HIGH)
#define DF_nADV2_ALE_ND_ALE MFP_CFG_LPM(DF_nADV2_ALE, AF1, PULL_HIGH)
#define DF_nADV2_ALE_nCS3 MFP_CFG_LPM(DF_nADV2_ALE, AF3, PULL_HIGH)
#define DF_nCS0_ND_nCS0 MFP_CFG_LPM(DF_nCS0, AF1, PULL_HIGH)
#define DF_nCS1_ND_nCS1 MFP_CFG_LPM(DF_nCS1, AF1, PULL_HIGH)
#define DF_nRE_nOE_ND_nRE MFP_CFG_LPM(DF_nRE_nOE, AF1, PULL_HIGH)
#define DF_nWE_ND_nWE MFP_CFG_LPM(DF_nWE, AF1, PULL_HIGH)
/* PWM */
#define GPIO41_PWM0 MFP_CFG_LPM(GPIO41, AF1, PULL_LOW)
#define GPIO42_PWM1 MFP_CFG_LPM(GPIO42, AF1, PULL_LOW)
#define GPIO43_PWM3 MFP_CFG_LPM(GPIO43, AF1, PULL_LOW)
#define GPIO20_PWM0 MFP_CFG_LPM(GPIO20, AF2, PULL_LOW)
#define GPIO21_PWM2 MFP_CFG_LPM(GPIO21, AF3, PULL_LOW)
#define GPIO22_PWM3 MFP_CFG_LPM(GPIO22, AF3, PULL_LOW)
/* CIR */
#define GPIO46_CIR_OUT MFP_CFG(GPIO46, AF1)
#define GPIO77_CIR_OUT MFP_CFG(GPIO77, AF3)
/* USB P2 */
#define GPIO0_USB_P2_7 MFP_CFG(GPIO0, AF3)
#define GPIO15_USB_P2_7 MFP_CFG(GPIO15, AF5)
#define GPIO16_USB_P2_7 MFP_CFG(GPIO16, AF2)
#define GPIO48_USB_P2_7 MFP_CFG(GPIO48, AF7)
#define GPIO49_USB_P2_7 MFP_CFG(GPIO49, AF6)
#define DF_IO9_USB_P2_7 MFP_CFG(DF_IO9, AF3)
#define GPIO48_USB_P2_8 MFP_CFG(GPIO48, AF2)
#define GPIO50_USB_P2_7 MFP_CFG_X(GPIO50, AF2, DS02X, FLOAT)
#define GPIO51_USB_P2_5 MFP_CFG(GPIO51, AF2)
#define GPIO47_USB_P2_4 MFP_CFG(GPIO47, AF2)
#define GPIO53_USB_P2_3 MFP_CFG(GPIO53, AF2)
#define GPIO54_USB_P2_6 MFP_CFG(GPIO54, AF2)
#define GPIO49_USB_P2_2 MFP_CFG(GPIO49, AF2)
#define GPIO52_USB_P2_1 MFP_CFG(GPIO52, AF2)
#define GPIO63_USB_P2_8 MFP_CFG(GPIO63, AF3)
#define GPIO64_USB_P2_7 MFP_CFG(GPIO64, AF3)
#define GPIO65_USB_P2_6 MFP_CFG(GPIO65, AF3)
#define GPIO66_USG_P2_5 MFP_CFG(GPIO66, AF3)
#define GPIO67_USB_P2_4 MFP_CFG(GPIO67, AF3)
#define GPIO68_USB_P2_3 MFP_CFG(GPIO68, AF3)
#define GPIO69_USB_P2_2 MFP_CFG(GPIO69, AF3)
#define GPIO70_USB_P2_1 MFP_CFG(GPIO70, AF3)
/* ULPI */
#define GPIO31_USB_ULPI_D0 MFP_CFG(GPIO31, AF4)
#define GPIO30_USB_ULPI_D1 MFP_CFG(GPIO30, AF7)
#define GPIO33_USB_ULPI_D2 MFP_CFG(GPIO33, AF5)
#define GPIO34_USB_ULPI_D3 MFP_CFG(GPIO34, AF5)
#define GPIO35_USB_ULPI_D4 MFP_CFG(GPIO35, AF5)
#define GPIO36_USB_ULPI_D5 MFP_CFG(GPIO36, AF5)
#define GPIO41_USB_ULPI_D6 MFP_CFG(GPIO41, AF5)
#define GPIO42_USB_ULPI_D7 MFP_CFG(GPIO42, AF5)
#define GPIO37_USB_ULPI_DIR MFP_CFG(GPIO37, AF4)
#define GPIO38_USB_ULPI_CLK MFP_CFG(GPIO38, AF4)
#define GPIO39_USB_ULPI_STP MFP_CFG(GPIO39, AF4)
#define GPIO40_USB_ULPI_NXT MFP_CFG(GPIO40, AF4)
#define GPIO3_CLK26MOUTDMD MFP_CFG(GPIO3, AF3)
#define GPIO40_CLK26MOUTDMD MFP_CFG(GPIO40, AF7)
#define GPIO94_CLK26MOUTDMD MFP_CFG(GPIO94, AF5)
#define GPIO104_CLK26MOUTDMD MFP_CFG(GPIO104, AF4)
#define DF_ADDR1_CLK26MOUTDMD MFP_CFG(DF_ADDR2, AF3)
#define DF_ADDR3_CLK26MOUTDMD MFP_CFG(DF_ADDR3, AF3)
#define GPIO14_CLK26MOUT MFP_CFG(GPIO14, AF5)
#define GPIO38_CLK26MOUT MFP_CFG(GPIO38, AF7)
#define GPIO92_CLK26MOUT MFP_CFG(GPIO92, AF5)
#define GPIO105_CLK26MOUT MFP_CFG(GPIO105, AF4)
#define GPIO2_CLK13MOUTDMD MFP_CFG(GPIO2, AF3)
#define GPIO39_CLK13MOUTDMD MFP_CFG(GPIO39, AF7)
#define GPIO50_CLK13MOUTDMD MFP_CFG(GPIO50, AF3)
#define GPIO93_CLK13MOUTDMD MFP_CFG(GPIO93, AF5)
#define GPIO103_CLK13MOUTDMD MFP_CFG(GPIO103, AF4)
#define DF_ADDR2_CLK13MOUTDMD MFP_CFG(DF_ADDR2, AF3)
/* 1 wire */
#define GPIO95_OW_DQ_IN MFP_CFG(GPIO95, AF5)
#endif /* __ASM_ARCH_MFP_PXA9xx_H */
include/asm-arm/arch-pxa/mfp.h
View file @ 30d38542
......@@ -210,6 +210,14 @@ enum {
MFP_PIN_DF_IO14,
MFP_PIN_DF_IO15,
/* additional pins on PXA930 */
MFP_PIN_GSIM_UIO,
MFP_PIN_GSIM_UCLK,
MFP_PIN_GSIM_UDET,
MFP_PIN_GSIM_nURST,
MFP_PIN_PMIC_INT,
MFP_PIN_RDY,
MFP_PIN_MAX,
};
......
include/asm-arm/arch-pxa/palmtx.h 0 → 100644
View file @ 30d38542
/*
* GPIOs and interrupts for Palm T|X Handheld Computer
*
* Based on palmld-gpio.h by Alex Osborne
*
* Authors: Marek Vasut <marek.vasut@gmail.com>
* Cristiano P. <cristianop@users.sourceforge.net>
* Jan Herman <2hp@seznam.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef _INCLUDE_PALMTX_H_
#define _INCLUDE_PALMTX_H_
/** HERE ARE GPIOs **/
/* GPIOs */
#define GPIO_NR_PALMTX_GPIO_RESET 1
#define GPIO_NR_PALMTX_POWER_DETECT 12 /* 90 */
#define GPIO_NR_PALMTX_HOTSYNC_BUTTON_N 10
#define GPIO_NR_PALMTX_EARPHONE_DETECT 107
/* SD/MMC */
#define GPIO_NR_PALMTX_SD_DETECT_N 14
#define GPIO_NR_PALMTX_SD_POWER 114 /* probably */
#define GPIO_NR_PALMTX_SD_READONLY 115 /* probably */
/* TOUCHSCREEN */
#define GPIO_NR_PALMTX_WM9712_IRQ 27
/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */
#define GPIO_NR_PALMTX_IR_DISABLE 40
/* USB */
#define GPIO_NR_PALMTX_USB_DETECT_N 13
#define GPIO_NR_PALMTX_USB_POWER 95
#define GPIO_NR_PALMTX_USB_PULLUP 93
/* LCD/BACKLIGHT */
#define GPIO_NR_PALMTX_BL_POWER 84
#define GPIO_NR_PALMTX_LCD_POWER 96
/* LCD BORDER */
#define GPIO_NR_PALMTX_BORDER_SWITCH 98
#define GPIO_NR_PALMTX_BORDER_SELECT 22
/* BLUETOOTH */
#define GPIO_NR_PALMTX_BT_POWER 17
#define GPIO_NR_PALMTX_BT_RESET 83
/* PCMCIA (WiFi) */
#define GPIO_NR_PALMTX_PCMCIA_POWER1 94
#define GPIO_NR_PALMTX_PCMCIA_POWER2 108
#define GPIO_NR_PALMTX_PCMCIA_RESET 79
#define GPIO_NR_PALMTX_PCMCIA_READY 116
/* NAND Flash ... this GPIO may be incorrect! */
#define GPIO_NR_PALMTX_NAND_BUFFER_DIR 79
/* INTERRUPTS */
#define IRQ_GPIO_PALMTX_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMTX_SD_DETECT_N)
#define IRQ_GPIO_PALMTX_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMTX_WM9712_IRQ)
#define IRQ_GPIO_PALMTX_USB_DETECT IRQ_GPIO(GPIO_NR_PALMTX_USB_DETECT)
#define IRQ_GPIO_PALMTX_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMTX_GPIO_RESET)
/** HERE ARE INIT VALUES **/
/* Various addresses */
#define PALMTX_PCMCIA_PHYS 0x28000000
#define PALMTX_PCMCIA_VIRT 0xf0000000
#define PALMTX_PCMCIA_SIZE 0x100000
#define PALMTX_PHYS_RAM_START 0xa0000000
#define PALMTX_PHYS_IO_START 0x40000000
#define PALMTX_PHYS_FLASH_START PXA_CS0_PHYS /* ChipSelect 0 */
#define PALMTX_PHYS_NAND_START PXA_CS1_PHYS /* ChipSelect 1 */
/* TOUCHSCREEN */
#define AC97_LINK_FRAME 21
/* BATTERY */
#define PALMTX_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */
#define PALMTX_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */
#define PALMTX_BAT_MAX_CURRENT 0 /* unknokn */
#define PALMTX_BAT_MIN_CURRENT 0 /* unknown */
#define PALMTX_BAT_MAX_CHARGE 1 /* unknown */
#define PALMTX_BAT_MIN_CHARGE 1 /* unknown */
#define PALMTX_MAX_LIFE_MINS 360 /* on-life in minutes */
#define PALMTX_BAT_MEASURE_DELAY (HZ * 1)
/* BACKLIGHT */
#define PALMTX_MAX_INTENSITY 0xFE
#define PALMTX_DEFAULT_INTENSITY 0x7E
#define PALMTX_LIMIT_MASK 0x7F
#define PALMTX_PRESCALER 0x3F
#define PALMTX_PERIOD_NS 3500
#endif
include/asm-arm/arch-pxa/pxa27x-udc.h
View file @ 30d38542
......@@ -97,7 +97,7 @@
#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */
#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
#define UP2OCR_SEOS(x) ((x & 7) << 24) /* Single-Ended Output Select */
#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
......
include/asm-arm/arch-pxa/pxa2xx_spi.h
View file @ 30d38542
......@@ -41,4 +41,6 @@ struct pxa2xx_spi_chip {
void (*cs_control)(u32 command);
};
extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info);
#endif /*PXA2XX_SPI_H_*/
include/asm-arm/arch-pxa/pxa3xx_nand.h
View file @ 30d38542
......@@ -15,4 +15,6 @@ struct pxa3xx_nand_platform_data {
struct mtd_partition *parts;
unsigned int nr_parts;
};
extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info);
#endif /* __ASM_ARCH_PXA3XX_NAND_H */
include/asm-arm/arch-pxa/pxafb.h
View file @ 30d38542
......@@ -71,7 +71,8 @@ struct pxafb_mode_info {
u_char bpp;
u_int cmap_greyscale:1,
unused:31;
depth:8,
unused:23;
/* Parallel Mode Timing */
u_char hsync_len;
......
include/asm-arm/arch-pxa/regs-lcd.h
View file @ 30d38542
......@@ -27,6 +27,12 @@
#define LCCR3_4BPP (2 << 24)
#define LCCR3_8BPP (3 << 24)
#define LCCR3_16BPP (4 << 24)
#define LCCR3_18BPP (5 << 24)
#define LCCR3_18BPP_P (6 << 24)
#define LCCR3_19BPP (7 << 24)
#define LCCR3_19BPP_P (1 << 29)
#define LCCR3_24BPP ((1 << 29) | (1 << 24))
#define LCCR3_25BPP ((1 << 29) | (2 << 24))
#define LCCR3_PDFOR_0 (0 << 30)
#define LCCR3_PDFOR_1 (1 << 30)
......
include/asm-arm/arch-pxa/regs-ssp.h
View file @ 30d38542
......@@ -20,6 +20,10 @@
#define SSTSS (0x38) /* SSP Timeslot Status */
#define SSACD (0x3C) /* SSP Audio Clock Divider */
#if defined(CONFIG_PXA3xx)
#define SSACDD (0x40) /* SSP Audio Clock Dither Divider */
#endif
/* Common PXA2xx bits first */
#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
......@@ -29,10 +33,12 @@
#define SSCR0_National (0x2 << 4) /* National Microwire */
#define SSCR0_ECS (1 << 6) /* External clock select */
#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
#if defined(CONFIG_PXA25x)
#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
#elif defined(CONFIG_PXA27x)
#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
#define SSCR0_EDSS (1 << 20) /* Extended data size select */
......@@ -45,6 +51,10 @@
#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
#endif
#if defined(CONFIG_PXA3xx)
#define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */
#endif
#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
......@@ -109,5 +119,9 @@
#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
#if defined(CONFIG_PXA3xx)
#define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */
#endif
#endif /* __ASM_ARCH_REGS_SSP_H */
include/asm-arm/arch-pxa/system.h
View file @ 30d38542
......@@ -21,19 +21,4 @@ static inline void arch_idle(void)
}
static inline void arch_reset(char mode)
{
if (cpu_is_pxa2xx())
RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
if (mode == 's') {
/* Jump into ROM at address 0 */
cpu_reset(0);
} else {
/* Initialize the watchdog and let it fire */
OWER = OWER_WME;
OSSR = OSSR_M3;
OSMR3 = OSCR + 368640; /* ... in 100 ms */
}
}
void arch_reset(char mode);
include/asm-arm/arch-pxa/tosa.h
View file @ 30d38542
......@@ -25,21 +25,18 @@
*/
#define TOSA_SCOOP_GPIO_BASE NR_BUILTIN_GPIO
#define TOSA_SCOOP_PXA_VCORE1 SCOOP_GPCR_PA11
#define TOSA_SCOOP_TC6393_REST_IN SCOOP_GPCR_PA12
#define TOSA_GPIO_TC6393XB_REST_IN (TOSA_SCOOP_GPIO_BASE + 1)
#define TOSA_GPIO_IR_POWERDWN (TOSA_SCOOP_GPIO_BASE + 2)
#define TOSA_GPIO_SD_WP (TOSA_SCOOP_GPIO_BASE + 3)
#define TOSA_GPIO_PWR_ON (TOSA_SCOOP_GPIO_BASE + 4)
#define TOSA_SCOOP_AUD_PWR_ON SCOOP_GPCR_PA16
#define TOSA_SCOOP_BT_RESET SCOOP_GPCR_PA17
#define TOSA_SCOOP_BT_PWR_EN SCOOP_GPCR_PA18
#define TOSA_GPIO_BT_RESET (TOSA_SCOOP_GPIO_BASE + 6)
#define TOSA_GPIO_BT_PWR_EN (TOSA_SCOOP_GPIO_BASE + 7)
#define TOSA_SCOOP_AC_IN_OL SCOOP_GPCR_PA19
/* GPIO Direction 1 : output mode / 0:input mode */
#define TOSA_SCOOP_IO_DIR ( TOSA_SCOOP_PXA_VCORE1 | TOSA_SCOOP_TC6393_REST_IN | \
TOSA_SCOOP_AUD_PWR_ON |\
TOSA_SCOOP_BT_RESET | TOSA_SCOOP_BT_PWR_EN )
/* GPIO out put level when init 1: Hi */
#define TOSA_SCOOP_IO_OUT ( TOSA_SCOOP_TC6393_REST_IN )
#define TOSA_SCOOP_IO_DIR (TOSA_SCOOP_PXA_VCORE1 | \
TOSA_SCOOP_AUD_PWR_ON)
/*
* SCOOP2 jacket GPIOs
......@@ -49,16 +46,34 @@
#define TOSA_GPIO_NOTE_LED (TOSA_SCOOP_JC_GPIO_BASE + 1)
#define TOSA_GPIO_CHRG_ERR_LED (TOSA_SCOOP_JC_GPIO_BASE + 2)
#define TOSA_GPIO_USB_PULLUP (TOSA_SCOOP_JC_GPIO_BASE + 3)
#define TOSA_SCOOP_JC_TC6393_SUSPEND SCOOP_GPCR_PA15
#define TOSA_SCOOP_JC_TC3693_L3V_ON SCOOP_GPCR_PA16
#define TOSA_GPIO_TC6393XB_SUSPEND (TOSA_SCOOP_JC_GPIO_BASE + 4)
#define TOSA_GPIO_TC6393XB_L3V_ON (TOSA_SCOOP_JC_GPIO_BASE + 5)
#define TOSA_SCOOP_JC_WLAN_DETECT SCOOP_GPCR_PA17
#define TOSA_GPIO_WLAN_LED (TOSA_SCOOP_JC_GPIO_BASE + 7)
#define TOSA_SCOOP_JC_CARD_LIMIT_SEL SCOOP_GPCR_PA19
/* GPIO Direction 1 : output mode / 0:input mode */
#define TOSA_SCOOP_JC_IO_DIR ( \
TOSA_SCOOP_JC_TC6393_SUSPEND | TOSA_SCOOP_JC_TC3693_L3V_ON | \
TOSA_SCOOP_JC_CARD_LIMIT_SEL )
#define TOSA_SCOOP_JC_IO_DIR (TOSA_SCOOP_JC_CARD_LIMIT_SEL)
/*
* TC6393XB GPIOs
*/
#define TOSA_TC6393XB_GPIO_BASE (NR_BUILTIN_GPIO + 2 * 12)
#define TOSA_TC6393XB_GPIO(i) (TOSA_TC6393XB_GPIO_BASE + (i))
#define TOSA_TC6393XB_GPIO_BIT(gpio) (1 << (gpio - TOSA_TC6393XB_GPIO_BASE))
#define TOSA_GPIO_TG_ON (TOSA_TC6393XB_GPIO_BASE + 0)
#define TOSA_GPIO_L_MUTE (TOSA_TC6393XB_GPIO_BASE + 1)
#define TOSA_GPIO_BL_C20MA (TOSA_TC6393XB_GPIO_BASE + 3)
#define TOSA_GPIO_CARD_VCC_ON (TOSA_TC6393XB_GPIO_BASE + 4)
#define TOSA_GPIO_CHARGE_OFF (TOSA_TC6393XB_GPIO_BASE + 6)
#define TOSA_GPIO_CHARGE_OFF_JC (TOSA_TC6393XB_GPIO_BASE + 7)
#define TOSA_GPIO_BAT0_V_ON (TOSA_TC6393XB_GPIO_BASE + 9)
#define TOSA_GPIO_BAT1_V_ON (TOSA_TC6393XB_GPIO_BASE + 10)
#define TOSA_GPIO_BU_CHRG_ON (TOSA_TC6393XB_GPIO_BASE + 11)
#define TOSA_GPIO_BAT_SW_ON (TOSA_TC6393XB_GPIO_BASE + 12)
#define TOSA_GPIO_BAT0_TH_ON (TOSA_TC6393XB_GPIO_BASE + 14)
#define TOSA_GPIO_BAT1_TH_ON (TOSA_TC6393XB_GPIO_BASE + 15)
/*
* Timing Generator
......@@ -84,13 +99,13 @@
#define TOSA_GPIO_JACKET_DETECT (7)
#define TOSA_GPIO_nSD_DETECT (9)
#define TOSA_GPIO_nSD_INT (10)
#define TOSA_GPIO_TC6393_CLK (11)
#define TOSA_GPIO_TC6393XB_CLK (11)
#define TOSA_GPIO_BAT1_CRG (12)
#define TOSA_GPIO_CF_CD (13)
#define TOSA_GPIO_BAT0_CRG (14)
#define TOSA_GPIO_TC6393_INT (15)
#define TOSA_GPIO_TC6393XB_INT (15)
#define TOSA_GPIO_BAT0_LOW (17)
#define TOSA_GPIO_TC6393_RDY (18)
#define TOSA_GPIO_TC6393XB_RDY (18)
#define TOSA_GPIO_ON_RESET (19)
#define TOSA_GPIO_EAR_IN (20)
#define TOSA_GPIO_CF_IRQ (21) /* CF slot0 Ready */
......@@ -99,6 +114,7 @@
#define TOSA_GPIO_TP_INT (32) /* Touch Panel pen down interrupt */
#define TOSA_GPIO_JC_CF_IRQ (36) /* CF slot1 Ready */
#define TOSA_GPIO_BAT_LOCKED (38) /* Battery locked */
#define TOSA_GPIO_IRDA_TX (47)
#define TOSA_GPIO_TG_SPI_SCLK (81)
#define TOSA_GPIO_TG_SPI_CS (82)
#define TOSA_GPIO_TG_SPI_MOSI (83)
......@@ -137,7 +153,7 @@
#define TOSA_IRQ_GPIO_BAT1_CRG IRQ_GPIO(TOSA_GPIO_BAT1_CRG)
#define TOSA_IRQ_GPIO_CF_CD IRQ_GPIO(TOSA_GPIO_CF_CD)
#define TOSA_IRQ_GPIO_BAT0_CRG IRQ_GPIO(TOSA_GPIO_BAT0_CRG)
#define TOSA_IRQ_GPIO_TC6393_INT IRQ_GPIO(TOSA_GPIO_TC6393_INT)
#define TOSA_IRQ_GPIO_TC6393XB_INT IRQ_GPIO(TOSA_GPIO_TC6393XB_INT)
#define TOSA_IRQ_GPIO_BAT0_LOW IRQ_GPIO(TOSA_GPIO_BAT0_LOW)
#define TOSA_IRQ_GPIO_EAR_IN IRQ_GPIO(TOSA_GPIO_EAR_IN)
#define TOSA_IRQ_GPIO_CF_IRQ IRQ_GPIO(TOSA_GPIO_CF_IRQ)
......
include/asm-arm/arch-pxa/tosa_bt.h 0 → 100644
View file @ 30d38542
/*
* Tosa bluetooth built-in chip control.
*
* Later it may be shared with some other platforms.
*
* Copyright (c) 2008 Dmitry Baryshkov
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef TOSA_BT_H
#define TOSA_BT_H
struct tosa_bt_data {
int gpio_pwr;
int gpio_reset;
};
#endif
include/asm-arm/arch-pxa/uncompress.h
View file @ 30d38542
......@@ -11,11 +11,11 @@
#include <linux/serial_reg.h>
#include <asm/arch/pxa-regs.h>
#include <asm/mach-types.h>
#define __REG(x) ((volatile unsigned long *)x)
#define UART FFUART
#define __REG(x) ((volatile unsigned long *)x)
static volatile unsigned long *UART = FFUART;
static inline void putc(char c)
{
......@@ -33,8 +33,13 @@ static inline void flush(void)
{
}
static inline void arch_decomp_setup(void)
{
if (machine_is_littleton())
UART = STUART;
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()
include/asm-arm/arch-pxa/zylonite.h
View file @ 30d38542
......@@ -16,6 +16,8 @@ struct platform_mmc_slot {
extern struct platform_mmc_slot zylonite_mmc_slot[];
extern int gpio_eth_irq;
extern int gpio_debug_led1;
extern int gpio_debug_led2;
extern int wm9713_irq;
......
include/asm-arm/mach/udc_pxa2xx.h
View file @ 30d38542
......@@ -23,6 +23,7 @@ struct pxa2xx_udc_mach_info {
*/
bool gpio_vbus_inverted;
u16 gpio_vbus; /* high == vbus present */
bool gpio_pullup_inverted;
u16 gpio_pullup; /* high == pullup activated */
};
include/linux/mfd/core.h 0 → 100644
View file @ 30d38542
#ifndef MFD_CORE_H
#define MFD_CORE_H
/*
* drivers/mfd/mfd-core.h
*
* core MFD support
* Copyright (c) 2006 Ian Molton
* Copyright (c) 2007 Dmitry Baryshkov
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/platform_device.h>
/*
* This struct describes the MFD part ("cell").
* After registration the copy of this structure will become the platform data
* of the resulting platform_device
*/
struct mfd_cell {
const char *name;
int (*enable)(struct platform_device *dev);
int (*disable)(struct platform_device *dev);
int (*suspend)(struct platform_device *dev);
int (*resume)(struct platform_device *dev);
void *driver_data; /* driver-specific data */
/*
* This resources can be specified relatievly to the parent device.
* For accessing device you should use resources from device
*/
int num_resources;
const struct resource *resources;
};
static inline struct mfd_cell *
mfd_get_cell(struct platform_device *pdev)
{
return (struct mfd_cell *)pdev->dev.platform_data;
}
extern int mfd_add_devices(
struct platform_device *parent,
const struct mfd_cell *cells, int n_devs,
struct resource *mem_base,
int irq_base);
extern void mfd_remove_devices(struct platform_device *parent);
#endif
include/linux/mfd/tc6393xb.h 0 → 100644
View file @ 30d38542
/*
* Toshiba TC6393XB SoC support
*
* Copyright(c) 2005-2006 Chris Humbert
* Copyright(c) 2005 Dirk Opfer
* Copyright(c) 2005 Ian Molton <spyro@f2s.com>
* Copyright(c) 2007 Dmitry Baryshkov
*
* Based on code written by Sharp/Lineo for 2.4 kernels
* Based on locomo.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef TC6393XB_H
#define TC6393XB_H
/* Also one should provide the CK3P6MI clock */
struct tc6393xb_platform_data {
u16 scr_pll2cr; /* PLL2 Control */
u16 scr_gper; /* GP Enable */
u32 scr_gpo_doecr; /* GPO Data OE Control */
u32 scr_gpo_dsr; /* GPO Data Set */
int (*enable)(struct platform_device *dev);
int (*disable)(struct platform_device *dev);
int (*suspend)(struct platform_device *dev);
int (*resume)(struct platform_device *dev);
int irq_base; /* a base for cascaded irq */
int gpio_base;
struct tmio_nand_data *nand_data;
};
/*
* Relative to irq_base
*/
#define IRQ_TC6393_NAND 0
#define IRQ_TC6393_MMC 1
#define IRQ_TC6393_OHCI 2
#define IRQ_TC6393_SERIAL 3
#define IRQ_TC6393_FB 4
#define TC6393XB_NR_IRQS 8
#endif
include/linux/mfd/tmio.h 0 → 100644
View file @ 30d38542
#ifndef MFD_TMIO_H
#define MFD_TMIO_H
/*
* data for the NAND controller
*/
struct tmio_nand_data {
struct nand_bbt_descr *badblock_pattern;
struct mtd_partition *partition;
unsigned int num_partitions;
};
#define TMIO_NAND_CONFIG "tmio-nand-config"
#define TMIO_NAND_CONTROL "tmio-nand-control"
#define TMIO_NAND_IRQ "tmio-nand"
#endif
include/linux/smc91x.h
View file @ 30d38542
......@@ -5,9 +5,19 @@
#define SMC91X_USE_16BIT (1 << 1)
#define SMC91X_USE_32BIT (1 << 2)
#define SMC91X_NOWAIT (1 << 3)
/* two bits for IO_SHIFT, let's hope later designs will keep this sane */
#define SMC91X_IO_SHIFT_0 (0 << 4)
#define SMC91X_IO_SHIFT_1 (1 << 4)
#define SMC91X_IO_SHIFT_2 (2 << 4)
#define SMC91X_IO_SHIFT_3 (3 << 4)
#define SMC91X_IO_SHIFT(x) (((x) >> 4) & 0x3)
#define SMC91X_USE_DMA (1 << 6)
struct smc91x_platdata {
unsigned long flags;
unsigned long irq_flags; /* IRQF_... */
};
#endif /* __SMC91X_H__ */
sound/soc/pxa/Kconfig
View file @ 30d38542
......@@ -48,6 +48,7 @@ config SND_PXA2XX_SOC_POODLE
config SND_PXA2XX_SOC_TOSA
tristate "SoC AC97 Audio support for Tosa"
depends on SND_PXA2XX_SOC && MACH_TOSA
depends on MFD_TC6393XB
select SND_PXA2XX_SOC_AC97
select SND_SOC_WM9712
help
......
sound/soc/pxa/tosa.c
View file @ 30d38542
......@@ -21,6 +21,7 @@
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/device.h>
#include <linux/gpio.h>
#include <sound/core.h>
#include <sound/pcm.h>
......@@ -28,7 +29,7 @@
#include <sound/soc-dapm.h>
#include <asm/mach-types.h>
#include <asm/hardware/tmio.h>
#include <asm/arch/tosa.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/hardware.h>
#include <asm/arch/audio.h>
......@@ -137,10 +138,7 @@ static int tosa_set_spk(struct snd_kcontrol *kcontrol,
static int tosa_hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
if (SND_SOC_DAPM_EVENT_ON(event))
set_tc6393_gpio(&tc6393_device.dev,TOSA_TC6393_L_MUTE);
else
reset_tc6393_gpio(&tc6393_device.dev,TOSA_TC6393_L_MUTE);
gpio_set_value(TOSA_GPIO_L_MUTE, SND_SOC_DAPM_EVENT_ON(event) ? 1 :0);
return 0;
}
......@@ -254,16 +252,28 @@ static int __init tosa_init(void)
if (!machine_is_tosa())
return -ENODEV;
ret = gpio_request(TOSA_GPIO_L_MUTE, "Headphone Jack");
if (ret)
return ret;
gpio_direction_output(TOSA_GPIO_L_MUTE, 0);
tosa_snd_device = platform_device_alloc("soc-audio", -1);
if (!tosa_snd_device)
return -ENOMEM;
if (!tosa_snd_device) {
ret = -ENOMEM;
goto err_alloc;
}
platform_set_drvdata(tosa_snd_device, &tosa_snd_devdata);
tosa_snd_devdata.dev = &tosa_snd_device->dev;
ret = platform_device_add(tosa_snd_device);
if (ret)
platform_device_put(tosa_snd_device);
if (!ret)
return 0;
platform_device_put(tosa_snd_device);
err_alloc:
gpio_free(TOSA_GPIO_L_MUTE);
return ret;
}
......@@ -271,6 +281,7 @@ static int __init tosa_init(void)
static void __exit tosa_exit(void)
{
platform_device_unregister(tosa_snd_device);
gpio_free(TOSA_GPIO_L_MUTE);
}
module_init(tosa_init);
......
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