Commit 32f0160c authored by David S. Miller's avatar David S. Miller

Merge branch '40GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-queue

Jeff Kirsher says:

====================
Intel Wired LAN Driver Updates 2017-11-27

This series contains updates to e1000, e1000e and i40e.

Gustavo A. R. Silva fixes a sizeof() issue where we were taking the size of
the pointer (which is always the size of the pointer).

Sasha does a follow up fix to a previous fix for buffer overrun, to resolve
community feedback from David Laight and the use of magic numbers.

Amritha fixes the reporting of error codes for when adding a cloud filter
fails.

Ahmad Fatoum brushes the dust off the e1000 driver to fix a code comment
and debug message which was incorrect about what the code was really doing.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 2e724dca 8abd20b4
...@@ -4307,8 +4307,10 @@ static void e1000_init_rx_addrs(struct e1000_hw *hw) ...@@ -4307,8 +4307,10 @@ static void e1000_init_rx_addrs(struct e1000_hw *hw)
rar_num = E1000_RAR_ENTRIES; rar_num = E1000_RAR_ENTRIES;
/* Zero out the other 15 receive addresses. */ /* Zero out the following 14 receive addresses. RAR[15] is for
e_dbg("Clearing RAR[1-15]\n"); * manageability
*/
e_dbg("Clearing RAR[1-14]\n");
for (i = 1; i < rar_num; i++) { for (i = 1; i < rar_num; i++) {
E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
E1000_WRITE_FLUSH(); E1000_WRITE_FLUSH();
......
...@@ -113,7 +113,8 @@ ...@@ -113,7 +113,8 @@
#define NVM_SIZE_MULTIPLIER 4096 /*multiplier for NVMS field */ #define NVM_SIZE_MULTIPLIER 4096 /*multiplier for NVMS field */
#define E1000_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs */ #define E1000_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs */
#define E1000_CTRL_EXT_NVMVS 0x3 /*NVM valid sector */ #define E1000_CTRL_EXT_NVMVS 0x3 /*NVM valid sector */
#define E1000_TARC0_CB_MULTIQ_3_REQ (1 << 28 | 1 << 29) #define E1000_TARC0_CB_MULTIQ_3_REQ 0x30000000
#define E1000_TARC0_CB_MULTIQ_2_REQ 0x20000000
#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
#define E1000_ICH_RAR_ENTRIES 7 #define E1000_ICH_RAR_ENTRIES 7
......
...@@ -3034,9 +3034,12 @@ static void e1000_configure_tx(struct e1000_adapter *adapter) ...@@ -3034,9 +3034,12 @@ static void e1000_configure_tx(struct e1000_adapter *adapter)
ew32(IOSFPC, reg_val); ew32(IOSFPC, reg_val);
reg_val = er32(TARC(0)); reg_val = er32(TARC(0));
/* SPT and KBL Si errata workaround to avoid Tx hang */ /* SPT and KBL Si errata workaround to avoid Tx hang.
reg_val &= ~BIT(28); * Dropping the number of outstanding requests from
reg_val |= BIT(29); * 3 to 2 in order to avoid a buffer overrun.
*/
reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ;
ew32(TARC(0), reg_val); ew32(TARC(0), reg_val);
} }
} }
......
...@@ -7401,7 +7401,6 @@ static int i40e_configure_clsflower(struct i40e_vsi *vsi, ...@@ -7401,7 +7401,6 @@ static int i40e_configure_clsflower(struct i40e_vsi *vsi,
dev_err(&pf->pdev->dev, dev_err(&pf->pdev->dev,
"Failed to add cloud filter, err %s\n", "Failed to add cloud filter, err %s\n",
i40e_stat_str(&pf->hw, err)); i40e_stat_str(&pf->hw, err));
err = i40e_aq_rc_to_posix(err, pf->hw.aq.asq_last_status);
goto err; goto err;
} }
......
...@@ -2086,7 +2086,7 @@ static int i40e_vc_request_queues_msg(struct i40e_vf *vf, u8 *msg, int msglen) ...@@ -2086,7 +2086,7 @@ static int i40e_vc_request_queues_msg(struct i40e_vf *vf, u8 *msg, int msglen)
} }
return i40e_vc_send_msg_to_vf(vf, VIRTCHNL_OP_REQUEST_QUEUES, 0, return i40e_vc_send_msg_to_vf(vf, VIRTCHNL_OP_REQUEST_QUEUES, 0,
(u8 *)vfres, sizeof(vfres)); (u8 *)vfres, sizeof(*vfres));
} }
/** /**
......
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