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Commit 3512a78a authored by Lucas De Marchi's avatar Lucas De Marchi Committed by Rodrigo Vivi
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drm/xe: Use XE_REG/XE_REG_MCR 

These should replace the _MMIO() and MCR_REG() from i915, with the goal
of being more extensible, allowing to pass the additional fields for
struct xe_reg and struct xe_reg_mcr. Replace all uses of _MMIO() and
MCR_REG() in xe.

Since the RTP, reg-save-restore and WA infra are not ready to use the
new type, just undef the macro like was done for the i915 types
previously. That conversion will come later.

v2: Remove MEDIA_SOFT_SCRATCH_COUNT/MEDIA_SOFT_SCRATCH re-added by
    mistake (Matt Roper)
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230427223256.1432787-8-lucas.demarchi@intel.comSigned-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 36e22be4
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Showing with 254 additions and 262 deletions
drivers/gpu/drm/xe/regs/xe_engine_regs.h
View file @ 3512a78a
...@@ -10,63 +10,63 @@ ...@@ -10,63 +10,63 @@
#include "regs/xe_reg_defs.h" #include "regs/xe_reg_defs.h"
#define RING_TAIL(base) _MMIO((base) + 0x30) #define RING_TAIL(base) XE_REG((base) + 0x30)
#define RING_HEAD(base) _MMIO((base) + 0x34) #define RING_HEAD(base) XE_REG((base) + 0x34)
#define HEAD_ADDR 0x001FFFFC #define HEAD_ADDR 0x001FFFFC
#define RING_START(base) _MMIO((base) + 0x38) #define RING_START(base) XE_REG((base) + 0x38)
#define RING_CTL(base) _MMIO((base) + 0x3c) #define RING_CTL(base) XE_REG((base) + 0x3c)
#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */ #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */ #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
#define RING_PSMI_CTL(base) _MMIO((base) + 0x50) #define RING_PSMI_CTL(base) XE_REG((base) + 0x50)
#define RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12) #define RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
#define WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7) #define WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c) #define RING_ACTHD_UDW(base) XE_REG((base) + 0x5c)
#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) #define RING_DMA_FADD_UDW(base) XE_REG((base) + 0x60)
#define RING_IPEIR(base) _MMIO((base) + 0x64) #define RING_IPEIR(base) XE_REG((base) + 0x64)
#define RING_IPEHR(base) _MMIO((base) + 0x68) #define RING_IPEHR(base) XE_REG((base) + 0x68)
#define RING_ACTHD(base) _MMIO((base) + 0x74) #define RING_ACTHD(base) XE_REG((base) + 0x74)
#define RING_DMA_FADD(base) _MMIO((base) + 0x78) #define RING_DMA_FADD(base) XE_REG((base) + 0x78)
#define RING_HWS_PGA(base) _MMIO((base) + 0x80) #define RING_HWS_PGA(base) XE_REG((base) + 0x80)
#define IPEIR(base) _MMIO((base) + 0x88) #define IPEIR(base) XE_REG((base) + 0x88)
#define IPEHR(base) _MMIO((base) + 0x8c) #define IPEHR(base) XE_REG((base) + 0x8c)
#define RING_HWSTAM(base) _MMIO((base) + 0x98) #define RING_HWSTAM(base) XE_REG((base) + 0x98)
#define RING_MI_MODE(base) _MMIO((base) + 0x9c) #define RING_MI_MODE(base) XE_REG((base) + 0x9c)
#define RING_NOPID(base) _MMIO((base) + 0x94) #define RING_NOPID(base) XE_REG((base) + 0x94)
#define RING_IMR(base) _MMIO((base) + 0xa8) #define RING_IMR(base) XE_REG((base) + 0xa8)
#define RING_MAX_NONPRIV_SLOTS 12 #define RING_MAX_NONPRIV_SLOTS 12
#define RING_EIR(base) _MMIO((base) + 0xb0) #define RING_EIR(base) XE_REG((base) + 0xb0)
#define RING_EMR(base) _MMIO((base) + 0xb4) #define RING_EMR(base) XE_REG((base) + 0xb4)
#define RING_ESR(base) _MMIO((base) + 0xb8) #define RING_ESR(base) XE_REG((base) + 0xb8)
#define RING_BBADDR(base) _MMIO((base) + 0x140) #define RING_BBADDR(base) XE_REG((base) + 0x140)
#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) #define RING_BBADDR_UDW(base) XE_REG((base) + 0x168)
#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234) #define RING_EXECLIST_STATUS_LO(base) XE_REG((base) + 0x234)
#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4) #define RING_EXECLIST_STATUS_HI(base) XE_REG((base) + 0x234 + 4)
#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244) #define RING_CONTEXT_CONTROL(base) XE_REG((base) + 0x244)
#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3) #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3)
#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0) #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)
#define RING_MODE(base) _MMIO((base) + 0x29c) #define RING_MODE(base) XE_REG((base) + 0x29c)
#define GFX_DISABLE_LEGACY_MODE REG_BIT(3) #define GFX_DISABLE_LEGACY_MODE REG_BIT(3)
#define RING_TIMESTAMP(base) _MMIO((base) + 0x358) #define RING_TIMESTAMP(base) XE_REG((base) + 0x358)
#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4) #define RING_TIMESTAMP_UDW(base) XE_REG((base) + 0x358 + 4)
#define RING_VALID_MASK 0x00000001 #define RING_VALID_MASK 0x00000001
#define RING_VALID 0x00000001 #define RING_VALID 0x00000001
#define STOP_RING REG_BIT(8) #define STOP_RING REG_BIT(8)
#define TAIL_ADDR 0x001FFFF8 #define TAIL_ADDR 0x001FFFF8
#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) #define RING_CTX_TIMESTAMP(base) XE_REG((base) + 0x3a8)
#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4d0) + (i) * 4) #define RING_FORCE_TO_NONPRIV(base, i) XE_REG(((base) + 0x4d0) + (i) * 4)
#define RING_FORCE_TO_NONPRIV_DENY REG_BIT(30) #define RING_FORCE_TO_NONPRIV_DENY REG_BIT(30)
#define RING_FORCE_TO_NONPRIV_ACCESS_MASK REG_GENMASK(29, 28) #define RING_FORCE_TO_NONPRIV_ACCESS_MASK REG_GENMASK(29, 28)
#define RING_FORCE_TO_NONPRIV_ACCESS_RW REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 0) #define RING_FORCE_TO_NONPRIV_ACCESS_RW REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 0)
...@@ -84,16 +84,16 @@ ...@@ -84,16 +84,16 @@
RING_FORCE_TO_NONPRIV_DENY) RING_FORCE_TO_NONPRIV_DENY)
#define RING_MAX_NONPRIV_SLOTS 12 #define RING_MAX_NONPRIV_SLOTS 12
#define RING_EXECLIST_SQ_CONTENTS_LO(base) _MMIO((base) + 0x510) #define RING_EXECLIST_SQ_CONTENTS_LO(base) XE_REG((base) + 0x510)
#define RING_EXECLIST_SQ_CONTENTS_HI(base) _MMIO((base) + 0x510 + 4) #define RING_EXECLIST_SQ_CONTENTS_HI(base) XE_REG((base) + 0x510 + 4)
#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550) #define RING_EXECLIST_CONTROL(base) XE_REG((base) + 0x550)
#define EL_CTRL_LOAD REG_BIT(0) #define EL_CTRL_LOAD REG_BIT(0)
#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10) #define VDBOX_CGCTL3F10(base) XE_REG((base) + 0x3f10)
#define IECPUNIT_CLKGATE_DIS REG_BIT(22) #define IECPUNIT_CLKGATE_DIS REG_BIT(22)
#define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18) #define VDBOX_CGCTL3F18(base) XE_REG((base) + 0x3f18)
#define ALNUNIT_CLKGATE_DIS REG_BIT(13) #define ALNUNIT_CLKGATE_DIS REG_BIT(13)
#endif #endif
drivers/gpu/drm/xe/regs/xe_gt_regs.h
View file @ 3512a78a
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
#include "regs/xe_reg_defs.h" #include "regs/xe_reg_defs.h"
/* RPM unit config (Gen8+) */ /* RPM unit config (Gen8+) */
#define RPM_CONFIG0 _MMIO(0xd00) #define RPM_CONFIG0 XE_REG(0xd00)
#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3) #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3)
#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1
...@@ -17,25 +17,26 @@ ...@@ -17,25 +17,26 @@
#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3
#define RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1) #define RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1)
#define FORCEWAKE_ACK_MEDIA_VDBOX(n) _MMIO(0xd50 + (n) * 4) #define FORCEWAKE_ACK_MEDIA_VDBOX(n) XE_REG(0xd50 + (n) * 4)
#define FORCEWAKE_ACK_MEDIA_VEBOX(n) _MMIO(0xd70 + (n) * 4) #define FORCEWAKE_ACK_MEDIA_VEBOX(n) XE_REG(0xd70 + (n) * 4)
#define FORCEWAKE_ACK_RENDER _MMIO(0xd84) #define FORCEWAKE_ACK_RENDER XE_REG(0xd84)
#define GMD_ID _MMIO(0xd8c) #define GMD_ID XE_REG(0xd8c)
#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22) #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14) #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
#define GMD_ID_STEP REG_GENMASK(5, 0) #define GMD_ID_STEP REG_GENMASK(5, 0)
#define FORCEWAKE_ACK_GT_MTL _MMIO(0xdfc) #define FORCEWAKE_ACK_GT_MTL XE_REG(0xdfc)
#define LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */ /* L3 Cache Control */
#define LNCFCMOCS(i) XE_REG(0xb020 + (i) * 4)
#define LNCFCMOCS_REG_COUNT 32 #define LNCFCMOCS_REG_COUNT 32
#define MCFG_MCR_SELECTOR _MMIO(0xfd0) #define MCFG_MCR_SELECTOR XE_REG(0xfd0)
#define MTL_MCR_SELECTOR _MMIO(0xfd4) #define MTL_MCR_SELECTOR XE_REG(0xfd4)
#define SF_MCR_SELECTOR _MMIO(0xfd8) #define SF_MCR_SELECTOR XE_REG(0xfd8)
#define MCR_SELECTOR _MMIO(0xfdc) #define MCR_SELECTOR XE_REG(0xfdc)
#define GAM_MCR_SELECTOR _MMIO(0xfe0) #define GAM_MCR_SELECTOR XE_REG(0xfe0)
#define MCR_MULTICAST REG_BIT(31) #define MCR_MULTICAST REG_BIT(31)
#define MCR_SLICE_MASK REG_GENMASK(30, 27) #define MCR_SLICE_MASK REG_GENMASK(30, 27)
#define MCR_SLICE(slice) REG_FIELD_PREP(MCR_SLICE_MASK, slice) #define MCR_SLICE(slice) REG_FIELD_PREP(MCR_SLICE_MASK, slice)
...@@ -44,19 +45,19 @@ ...@@ -44,19 +45,19 @@
#define MTL_MCR_GROUPID REG_GENMASK(11, 8) #define MTL_MCR_GROUPID REG_GENMASK(11, 8)
#define MTL_MCR_INSTANCEID REG_GENMASK(3, 0) #define MTL_MCR_INSTANCEID REG_GENMASK(3, 0)
#define FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0) #define FF_SLICE_CS_CHICKEN1 XE_REG(0x20e0)
#define FFSC_PERCTX_PREEMPT_CTRL REG_BIT(14) #define FFSC_PERCTX_PREEMPT_CTRL REG_BIT(14)
#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) #define FF_SLICE_CS_CHICKEN2 XE_REG(0x20e4)
#define PERF_FIX_BALANCING_CFE_DISABLE REG_BIT(15) #define PERF_FIX_BALANCING_CFE_DISABLE REG_BIT(15)
#define CS_DEBUG_MODE1 _MMIO(0x20ec) #define CS_DEBUG_MODE1 XE_REG(0x20ec)
#define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1) #define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
#define REPLAY_MODE_GRANULARITY REG_BIT(0) #define REPLAY_MODE_GRANULARITY REG_BIT(0)
#define PS_INVOCATION_COUNT _MMIO(0x2348) #define PS_INVOCATION_COUNT XE_REG(0x2348)
#define CS_CHICKEN1 _MMIO(0x2580) #define CS_CHICKEN1 XE_REG(0x2580)
#define PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1)) #define PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
#define PREEMPT_GPGPU_MID_THREAD_LEVEL PREEMPT_GPGPU_LEVEL(0, 0) #define PREEMPT_GPGPU_MID_THREAD_LEVEL PREEMPT_GPGPU_LEVEL(0, 0)
#define PREEMPT_GPGPU_THREAD_GROUP_LEVEL PREEMPT_GPGPU_LEVEL(0, 1) #define PREEMPT_GPGPU_THREAD_GROUP_LEVEL PREEMPT_GPGPU_LEVEL(0, 1)
...@@ -64,70 +65,70 @@ ...@@ -64,70 +65,70 @@
#define PREEMPT_GPGPU_LEVEL_MASK PREEMPT_GPGPU_LEVEL(1, 1) #define PREEMPT_GPGPU_LEVEL_MASK PREEMPT_GPGPU_LEVEL(1, 1)
#define PREEMPT_3D_OBJECT_LEVEL REG_BIT(0) #define PREEMPT_3D_OBJECT_LEVEL REG_BIT(0)
#define GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */ #define GLOBAL_MOCS(i) XE_REG(0x4000 + (i) * 4) /* Global MOCS regs */
#define CCS_AUX_INV _MMIO(0x4208) #define CCS_AUX_INV XE_REG(0x4208)
#define VD0_AUX_INV _MMIO(0x4218) #define VD0_AUX_INV XE_REG(0x4218)
#define VE0_AUX_INV _MMIO(0x4238) #define VE0_AUX_INV XE_REG(0x4238)
#define VE1_AUX_INV _MMIO(0x42b8) #define VE1_AUX_INV XE_REG(0x42b8)
#define AUX_INV REG_BIT(0) #define AUX_INV REG_BIT(0)
#define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900) #define XEHP_TILE0_ADDR_RANGE XE_REG_MCR(0x4900)
#define XEHP_FLAT_CCS_BASE_ADDR MCR_REG(0x4910) #define XEHP_FLAT_CCS_BASE_ADDR XE_REG_MCR(0x4910)
#define CHICKEN_RASTER_1 MCR_REG(0x6204) #define CHICKEN_RASTER_1 XE_REG_MCR(0x6204)
#define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8) #define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8)
#define CHICKEN_RASTER_2 MCR_REG(0x6208) #define CHICKEN_RASTER_2 XE_REG_MCR(0x6208)
#define TBIMR_FAST_CLIP REG_BIT(5) #define TBIMR_FAST_CLIP REG_BIT(5)
#define VFLSKPD MCR_REG(0x62a8) #define VFLSKPD XE_REG_MCR(0x62a8)
#define DIS_OVER_FETCH_CACHE REG_BIT(1) #define DIS_OVER_FETCH_CACHE REG_BIT(1)
#define DIS_MULT_MISS_RD_SQUASH REG_BIT(0) #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
#define FF_MODE2 _MMIO(0x6604) #define FF_MODE2 XE_REG(0x6604)
#define XEHP_FF_MODE2 MCR_REG(0x6604) #define XEHP_FF_MODE2 XE_REG_MCR(0x6604)
#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24) #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
#define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224) #define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16) #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4) #define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
#define CACHE_MODE_1 _MMIO(0x7004) #define CACHE_MODE_1 XE_REG(0x7004)
#define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11) #define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11)
#define XEHP_PSS_MODE2 MCR_REG(0x703c) #define XEHP_PSS_MODE2 XE_REG_MCR(0x703c)
#define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) #define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5)
#define HIZ_CHICKEN _MMIO(0x7018) #define HIZ_CHICKEN XE_REG(0x7018)
#define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14) #define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14)
#define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13) #define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13)
#define COMMON_SLICE_CHICKEN1 _MMIO(0x7010) #define COMMON_SLICE_CHICKEN1 XE_REG(0x7010)
#define COMMON_SLICE_CHICKEN4 _MMIO(0x7300) #define COMMON_SLICE_CHICKEN4 XE_REG(0x7300)
#define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6) #define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6)
#define COMMON_SLICE_CHICKEN3 _MMIO(0x7304) #define COMMON_SLICE_CHICKEN3 XE_REG(0x7304)
#define XEHP_COMMON_SLICE_CHICKEN3 MCR_REG(0x7304) #define XEHP_COMMON_SLICE_CHICKEN3 XE_REG_MCR(0x7304)
#define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12) #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
#define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12) #define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
#define BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11) #define BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
#define DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9) #define DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
#define XEHP_SLICE_COMMON_ECO_CHICKEN1 MCR_REG(0x731c) #define XEHP_SLICE_COMMON_ECO_CHICKEN1 XE_REG_MCR(0x731c)
#define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14) #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
#define VF_PREEMPTION _MMIO(0x83a4) #define VF_PREEMPTION XE_REG(0x83a4)
#define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0) #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0)
#define VFG_PREEMPTION_CHICKEN _MMIO(0x83b4) #define VFG_PREEMPTION_CHICKEN XE_REG(0x83b4)
#define POLYGON_TRIFAN_LINELOOP_DISABLE REG_BIT(4) #define POLYGON_TRIFAN_LINELOOP_DISABLE REG_BIT(4)
#define XEHP_SQCM MCR_REG(0x8724) #define XEHP_SQCM XE_REG_MCR(0x8724)
#define EN_32B_ACCESS REG_BIT(30) #define EN_32B_ACCESS REG_BIT(30)
#define MIRROR_FUSE3 _MMIO(0x9118) #define MIRROR_FUSE3 XE_REG(0x9118)
#define L3BANK_PAIR_COUNT 4 #define L3BANK_PAIR_COUNT 4
#define L3BANK_MASK REG_GENMASK(3, 0) #define L3BANK_MASK REG_GENMASK(3, 0)
/* on Xe_HP the same fuses indicates mslices instead of L3 banks */ /* on Xe_HP the same fuses indicates mslices instead of L3 banks */
...@@ -135,30 +136,30 @@ ...@@ -135,30 +136,30 @@
#define MEML3_EN_MASK REG_GENMASK(3, 0) #define MEML3_EN_MASK REG_GENMASK(3, 0)
/* Fuse readout registers for GT */ /* Fuse readout registers for GT */
#define XEHP_FUSE4 _MMIO(0x9114) #define XEHP_FUSE4 XE_REG(0x9114)
#define GT_L3_EXC_MASK REG_GENMASK(6, 4) #define GT_L3_EXC_MASK REG_GENMASK(6, 4)
#define GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140) #define GT_VEBOX_VDBOX_DISABLE XE_REG(0x9140)
#define GT_VEBOX_DISABLE_MASK REG_GENMASK(19, 16) #define GT_VEBOX_DISABLE_MASK REG_GENMASK(19, 16)
#define GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0) #define GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0)
#define XELP_EU_ENABLE _MMIO(0x9134) /* "_DISABLE" on Xe_LP */ #define XELP_EU_ENABLE XE_REG(0x9134) /* "_DISABLE" on Xe_LP */
#define XELP_EU_MASK REG_GENMASK(7, 0) #define XELP_EU_MASK REG_GENMASK(7, 0)
#define XELP_GT_GEOMETRY_DSS_ENABLE _MMIO(0x913c) #define XELP_GT_GEOMETRY_DSS_ENABLE XE_REG(0x913c)
#define XEHP_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144) #define XEHP_GT_COMPUTE_DSS_ENABLE XE_REG(0x9144)
#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT _MMIO(0x9148) #define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT XE_REG(0x9148)
#define GDRST _MMIO(0x941c) #define GDRST XE_REG(0x941c)
#define GRDOM_GUC REG_BIT(3) #define GRDOM_GUC REG_BIT(3)
#define GRDOM_FULL REG_BIT(0) #define GRDOM_FULL REG_BIT(0)
#define MISCCPCTL _MMIO(0x9424) #define MISCCPCTL XE_REG(0x9424)
#define DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1) #define DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1)
#define UNSLCGCTL9430 _MMIO(0x9430) #define UNSLCGCTL9430 XE_REG(0x9430)
#define MSQDUNIT_CLKGATE_DIS REG_BIT(3) #define MSQDUNIT_CLKGATE_DIS REG_BIT(3)
#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434) #define UNSLICE_UNIT_LEVEL_CLKGATE XE_REG(0x9434)
#define VFUNIT_CLKGATE_DIS REG_BIT(20) #define VFUNIT_CLKGATE_DIS REG_BIT(20)
#define TSGUNIT_CLKGATE_DIS REG_BIT(17) /* XEHPSDV */ #define TSGUNIT_CLKGATE_DIS REG_BIT(17) /* XEHPSDV */
#define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */ #define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */
...@@ -166,7 +167,7 @@ ...@@ -166,7 +167,7 @@
#define HSUNIT_CLKGATE_DIS REG_BIT(8) #define HSUNIT_CLKGATE_DIS REG_BIT(8)
#define VSUNIT_CLKGATE_DIS REG_BIT(3) #define VSUNIT_CLKGATE_DIS REG_BIT(3)
#define UNSLCGCTL9440 _MMIO(0x9440) #define UNSLCGCTL9440 XE_REG(0x9440)
#define GAMTLBOACS_CLKGATE_DIS REG_BIT(28) #define GAMTLBOACS_CLKGATE_DIS REG_BIT(28)
#define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27) #define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27)
#define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26) #define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26)
...@@ -180,7 +181,7 @@ ...@@ -180,7 +181,7 @@
#define GAMTLBBLT_CLKGATE_DIS REG_BIT(14) #define GAMTLBBLT_CLKGATE_DIS REG_BIT(14)
#define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6) #define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6)
#define UNSLCGCTL9444 _MMIO(0x9444) #define UNSLCGCTL9444 XE_REG(0x9444)
#define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30) #define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30)
#define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29) #define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29)
#define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28) #define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28)
...@@ -198,7 +199,7 @@ ...@@ -198,7 +199,7 @@
#define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16) #define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
#define LTCDD_CLKGATE_DIS REG_BIT(10) #define LTCDD_CLKGATE_DIS REG_BIT(10)
#define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4) #define XEHP_SLICE_UNIT_LEVEL_CLKGATE XE_REG_MCR(0x94d4)
#define L3_CR2X_CLKGATE_DIS REG_BIT(17) #define L3_CR2X_CLKGATE_DIS REG_BIT(17)
#define L3_CLKGATE_DIS REG_BIT(16) #define L3_CLKGATE_DIS REG_BIT(16)
#define NODEDSS_CLKGATE_DIS REG_BIT(12) #define NODEDSS_CLKGATE_DIS REG_BIT(12)
...@@ -206,85 +207,85 @@ ...@@ -206,85 +207,85 @@
#define RCCUNIT_CLKGATE_DIS REG_BIT(7) #define RCCUNIT_CLKGATE_DIS REG_BIT(7)
#define SARBUNIT_CLKGATE_DIS REG_BIT(5) #define SARBUNIT_CLKGATE_DIS REG_BIT(5)
#define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4) #define UNSLICE_UNIT_LEVEL_CLKGATE2 XE_REG(0x94e4)
#define VSUNIT_CLKGATE2_DIS REG_BIT(19) #define VSUNIT_CLKGATE2_DIS REG_BIT(19)
#define SUBSLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x9524) #define SUBSLICE_UNIT_LEVEL_CLKGATE XE_REG_MCR(0x9524)
#define DSS_ROUTER_CLKGATE_DIS REG_BIT(28) #define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
#define GWUNIT_CLKGATE_DIS REG_BIT(16) #define GWUNIT_CLKGATE_DIS REG_BIT(16)
#define SUBSLICE_UNIT_LEVEL_CLKGATE2 MCR_REG(0x9528) #define SUBSLICE_UNIT_LEVEL_CLKGATE2 XE_REG_MCR(0x9528)
#define CPSSUNIT_CLKGATE_DIS REG_BIT(9) #define CPSSUNIT_CLKGATE_DIS REG_BIT(9)
#define SSMCGCTL9530 MCR_REG(0x9530) #define SSMCGCTL9530 XE_REG_MCR(0x9530)
#define RTFUNIT_CLKGATE_DIS REG_BIT(18) #define RTFUNIT_CLKGATE_DIS REG_BIT(18)
#define DFR_RATIO_EN_AND_CHICKEN MCR_REG(0x9550) #define DFR_RATIO_EN_AND_CHICKEN XE_REG_MCR(0x9550)
#define DFR_DISABLE REG_BIT(9) #define DFR_DISABLE REG_BIT(9)
#define RPNSWREQ _MMIO(0xa008) #define RPNSWREQ XE_REG(0xa008)
#define REQ_RATIO_MASK REG_GENMASK(31, 23) #define REQ_RATIO_MASK REG_GENMASK(31, 23)
#define RC_CONTROL _MMIO(0xa090) #define RC_CONTROL XE_REG(0xa090)
#define RC_STATE _MMIO(0xa094) #define RC_STATE XE_REG(0xa094)
#define PMINTRMSK _MMIO(0xa168) #define PMINTRMSK XE_REG(0xa168)
#define PMINTR_DISABLE_REDIRECT_TO_GUC REG_BIT(31) #define PMINTR_DISABLE_REDIRECT_TO_GUC REG_BIT(31)
#define ARAT_EXPIRED_INTRMSK REG_BIT(9) #define ARAT_EXPIRED_INTRMSK REG_BIT(9)
#define FORCEWAKE_GT _MMIO(0xa188) #define FORCEWAKE_GT XE_REG(0xa188)
#define PG_ENABLE _MMIO(0xa210) #define PG_ENABLE XE_REG(0xa210)
#define CTC_MODE _MMIO(0xa26c) #define CTC_MODE XE_REG(0xa26c)
#define CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1) #define CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1)
#define CTC_SOURCE_DIVIDE_LOGIC REG_BIT(0) #define CTC_SOURCE_DIVIDE_LOGIC REG_BIT(0)
#define FORCEWAKE_RENDER _MMIO(0xa278) #define FORCEWAKE_RENDER XE_REG(0xa278)
#define FORCEWAKE_MEDIA_VDBOX(n) _MMIO(0xa540 + (n) * 4) #define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4)
#define FORCEWAKE_MEDIA_VEBOX(n) _MMIO(0xa560 + (n) * 4) #define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4)
#define XEHPC_LNCFMISCCFGREG0 MCR_REG(0xb01c) #define XEHPC_LNCFMISCCFGREG0 XE_REG_MCR(0xb01c)
#define XEHPC_OVRLSCCC REG_BIT(0) #define XEHPC_OVRLSCCC REG_BIT(0)
#define XEHP_L3NODEARBCFG MCR_REG(0xb0b4) #define XEHP_L3NODEARBCFG XE_REG_MCR(0xb0b4)
#define XEHP_LNESPARE REG_BIT(19) #define XEHP_LNESPARE REG_BIT(19)
#define XEHP_L3SQCREG5 MCR_REG(0xb158) #define XEHP_L3SQCREG5 XE_REG_MCR(0xb158)
#define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0) #define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
#define XEHP_L3SCQREG7 MCR_REG(0xb188) #define XEHP_L3SCQREG7 XE_REG_MCR(0xb188)
#define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3) #define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
#define XEHP_MERT_MOD_CTRL MCR_REG(0xcf28) #define XEHP_MERT_MOD_CTRL XE_REG_MCR(0xcf28)
#define RENDER_MOD_CTRL MCR_REG(0xcf2c) #define RENDER_MOD_CTRL XE_REG_MCR(0xcf2c)
#define COMP_MOD_CTRL MCR_REG(0xcf30) #define COMP_MOD_CTRL XE_REG_MCR(0xcf30)
#define XEHP_VDBX_MOD_CTRL MCR_REG(0xcf34) #define XEHP_VDBX_MOD_CTRL XE_REG_MCR(0xcf34)
#define XEHP_VEBX_MOD_CTRL MCR_REG(0xcf38) #define XEHP_VEBX_MOD_CTRL XE_REG_MCR(0xcf38)
#define FORCE_MISS_FTLB REG_BIT(3) #define FORCE_MISS_FTLB REG_BIT(3)
#define XEHP_GAMSTLB_CTRL MCR_REG(0xcf4c) #define XEHP_GAMSTLB_CTRL XE_REG_MCR(0xcf4c)
#define CONTROL_BLOCK_CLKGATE_DIS REG_BIT(12) #define CONTROL_BLOCK_CLKGATE_DIS REG_BIT(12)
#define EGRESS_BLOCK_CLKGATE_DIS REG_BIT(11) #define EGRESS_BLOCK_CLKGATE_DIS REG_BIT(11)
#define TAG_BLOCK_CLKGATE_DIS REG_BIT(7) #define TAG_BLOCK_CLKGATE_DIS REG_BIT(7)
#define XEHP_GAMCNTRL_CTRL MCR_REG(0xcf54) #define XEHP_GAMCNTRL_CTRL XE_REG_MCR(0xcf54)
#define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12) #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
#define GLOBAL_INVALIDATION_MODE REG_BIT(2) #define GLOBAL_INVALIDATION_MODE REG_BIT(2)
#define SAMPLER_MODE MCR_REG(0xe18c) #define SAMPLER_MODE XE_REG_MCR(0xe18c)
#define ENABLE_SMALLPL REG_BIT(15) #define ENABLE_SMALLPL REG_BIT(15)
#define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9) #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
#define SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) #define SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
#define HALF_SLICE_CHICKEN7 MCR_REG(0xe194) #define HALF_SLICE_CHICKEN7 XE_REG_MCR(0xe194)
#define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15) #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
#define CACHE_MODE_SS MCR_REG(0xe420) #define CACHE_MODE_SS XE_REG_MCR(0xe420)
#define ENABLE_EU_COUNT_FOR_TDL_FLUSH REG_BIT(10) #define ENABLE_EU_COUNT_FOR_TDL_FLUSH REG_BIT(10)
#define DISABLE_ECC REG_BIT(5) #define DISABLE_ECC REG_BIT(5)
#define ENABLE_PREFETCH_INTO_IC REG_BIT(3) #define ENABLE_PREFETCH_INTO_IC REG_BIT(3)
#define ROW_CHICKEN4 MCR_REG(0xe48c) #define ROW_CHICKEN4 XE_REG_MCR(0xe48c)
#define DISABLE_GRF_CLEAR REG_BIT(13) #define DISABLE_GRF_CLEAR REG_BIT(13)
#define XEHP_DIS_BBL_SYSPIPE REG_BIT(11) #define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
#define DISABLE_TDL_PUSH REG_BIT(9) #define DISABLE_TDL_PUSH REG_BIT(9)
...@@ -293,84 +294,84 @@ ...@@ -293,84 +294,84 @@
#define THREAD_EX_ARB_MODE REG_GENMASK(3, 2) #define THREAD_EX_ARB_MODE REG_GENMASK(3, 2)
#define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2) #define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
#define ROW_CHICKEN MCR_REG(0xe4f0) #define ROW_CHICKEN XE_REG_MCR(0xe4f0)
#define UGM_BACKUP_MODE REG_BIT(13) #define UGM_BACKUP_MODE REG_BIT(13)
#define MDQ_ARBITRATION_MODE REG_BIT(12) #define MDQ_ARBITRATION_MODE REG_BIT(12)
#define ROW_CHICKEN2 MCR_REG(0xe4f4) #define ROW_CHICKEN2 XE_REG_MCR(0xe4f4)
#define DISABLE_READ_SUPPRESSION REG_BIT(15) #define DISABLE_READ_SUPPRESSION REG_BIT(15)
#define DISABLE_EARLY_READ REG_BIT(14) #define DISABLE_EARLY_READ REG_BIT(14)
#define ENABLE_LARGE_GRF_MODE REG_BIT(12) #define ENABLE_LARGE_GRF_MODE REG_BIT(12)
#define PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8) #define PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
#define DISABLE_DOP_GATING REG_BIT(0) #define DISABLE_DOP_GATING REG_BIT(0)
#define XEHP_HDC_CHICKEN0 MCR_REG(0xe5f0) #define XEHP_HDC_CHICKEN0 XE_REG_MCR(0xe5f0)
#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11) #define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
#define RT_CTRL MCR_REG(0xe530) #define RT_CTRL XE_REG_MCR(0xe530)
#define DIS_NULL_QUERY REG_BIT(10) #define DIS_NULL_QUERY REG_BIT(10)
#define LSC_CHICKEN_BIT_0 MCR_REG(0xe7c8) #define LSC_CHICKEN_BIT_0 XE_REG_MCR(0xe7c8)
#define DISABLE_D8_D16_COASLESCE REG_BIT(30) #define DISABLE_D8_D16_COASLESCE REG_BIT(30)
#define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15) #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15)
#define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4) #define LSC_CHICKEN_BIT_0_UDW XE_REG_MCR(0xe7c8 + 4)
#define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32) #define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32)
#define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32) #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32)
#define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32) #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32)
#define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32) #define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32)
#define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32) #define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32)
#define SARB_CHICKEN1 MCR_REG(0xe90c) #define SARB_CHICKEN1 XE_REG_MCR(0xe90c)
#define COMP_CKN_IN REG_GENMASK(30, 29) #define COMP_CKN_IN REG_GENMASK(30, 29)
#define RCU_MODE _MMIO(0x14800) #define RCU_MODE XE_REG(0x14800)
#define RCU_MODE_CCS_ENABLE REG_BIT(0) #define RCU_MODE_CCS_ENABLE REG_BIT(0)
#define FORCEWAKE_ACK_GT _MMIO(0x130044) #define FORCEWAKE_ACK_GT XE_REG(0x130044)
#define FORCEWAKE_KERNEL BIT(0) #define FORCEWAKE_KERNEL BIT(0)
#define FORCEWAKE_USER BIT(1) #define FORCEWAKE_USER BIT(1)
#define FORCEWAKE_KERNEL_FALLBACK BIT(15) #define FORCEWAKE_KERNEL_FALLBACK BIT(15)
#define GT_CORE_STATUS _MMIO(0x138060) #define GT_CORE_STATUS XE_REG(0x138060)
#define RCN_MASK REG_GENMASK(2, 0) #define RCN_MASK REG_GENMASK(2, 0)
#define GT_RC0 0 #define GT_RC0 0
#define GT_RC6 3 #define GT_RC6 3
#define GT_GFX_RC6_LOCKED _MMIO(0x138104) #define GT_GFX_RC6_LOCKED XE_REG(0x138104)
#define GT_GFX_RC6 _MMIO(0x138108) #define GT_GFX_RC6 XE_REG(0x138108)
#define GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) #define GT_INTR_DW(x) XE_REG(0x190018 + ((x) * 4))
#define GUC_SG_INTR_ENABLE _MMIO(0x190038) #define GUC_SG_INTR_ENABLE XE_REG(0x190038)
#define ENGINE1_MASK REG_GENMASK(31, 16) #define ENGINE1_MASK REG_GENMASK(31, 16)
#define ENGINE0_MASK REG_GENMASK(15, 0) #define ENGINE0_MASK REG_GENMASK(15, 0)
#define GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c) #define GPM_WGBOXPERF_INTR_ENABLE XE_REG(0x19003c)
#define INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4)) #define INTR_IDENTITY_REG(x) XE_REG(0x190060 + ((x) * 4))
#define INTR_DATA_VALID REG_BIT(31) #define INTR_DATA_VALID REG_BIT(31)
#define INTR_ENGINE_INSTANCE(x) REG_FIELD_GET(GENMASK(25, 20), x) #define INTR_ENGINE_INSTANCE(x) REG_FIELD_GET(GENMASK(25, 20), x)
#define INTR_ENGINE_CLASS(x) REG_FIELD_GET(GENMASK(18, 16), x) #define INTR_ENGINE_CLASS(x) REG_FIELD_GET(GENMASK(18, 16), x)
#define INTR_ENGINE_INTR(x) REG_FIELD_GET(GENMASK(15, 0), x) #define INTR_ENGINE_INTR(x) REG_FIELD_GET(GENMASK(15, 0), x)
#define OTHER_GUC_INSTANCE 0 #define OTHER_GUC_INSTANCE 0
#define RENDER_COPY_INTR_ENABLE _MMIO(0x190030) #define RENDER_COPY_INTR_ENABLE XE_REG(0x190030)
#define VCS_VECS_INTR_ENABLE _MMIO(0x190034) #define VCS_VECS_INTR_ENABLE XE_REG(0x190034)
#define CCS_RSVD_INTR_ENABLE _MMIO(0x190048) #define CCS_RSVD_INTR_ENABLE XE_REG(0x190048)
#define IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4)) #define IIR_REG_SELECTOR(x) XE_REG(0x190070 + ((x) * 4))
#define RCS0_RSVD_INTR_MASK _MMIO(0x190090) #define RCS0_RSVD_INTR_MASK XE_REG(0x190090)
#define BCS_RSVD_INTR_MASK _MMIO(0x1900a0) #define BCS_RSVD_INTR_MASK XE_REG(0x1900a0)
#define VCS0_VCS1_INTR_MASK _MMIO(0x1900a8) #define VCS0_VCS1_INTR_MASK XE_REG(0x1900a8)
#define VCS2_VCS3_INTR_MASK _MMIO(0x1900ac) #define VCS2_VCS3_INTR_MASK XE_REG(0x1900ac)
#define VECS0_VECS1_INTR_MASK _MMIO(0x1900d0) #define VECS0_VECS1_INTR_MASK XE_REG(0x1900d0)
#define GUC_SG_INTR_MASK _MMIO(0x1900e8) #define GUC_SG_INTR_MASK XE_REG(0x1900e8)
#define GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec) #define GPM_WGBOXPERF_INTR_MASK XE_REG(0x1900ec)
#define CCS0_CCS1_INTR_MASK _MMIO(0x190100) #define CCS0_CCS1_INTR_MASK XE_REG(0x190100)
#define CCS2_CCS3_INTR_MASK _MMIO(0x190104) #define CCS2_CCS3_INTR_MASK XE_REG(0x190104)
#define XEHPC_BCS1_BCS2_INTR_MASK _MMIO(0x190110) #define XEHPC_BCS1_BCS2_INTR_MASK XE_REG(0x190110)
#define XEHPC_BCS3_BCS4_INTR_MASK _MMIO(0x190114) #define XEHPC_BCS3_BCS4_INTR_MASK XE_REG(0x190114)
#define XEHPC_BCS5_BCS6_INTR_MASK _MMIO(0x190118) #define XEHPC_BCS5_BCS6_INTR_MASK XE_REG(0x190118)
#define XEHPC_BCS7_BCS8_INTR_MASK _MMIO(0x19011c) #define XEHPC_BCS7_BCS8_INTR_MASK XE_REG(0x19011c)
#endif #endif
drivers/gpu/drm/xe/regs/xe_guc_regs.h
View file @ 3512a78a
...@@ -13,7 +13,7 @@ ...@@ -13,7 +13,7 @@
/* Definitions of GuC H/W registers, bits, etc */ /* Definitions of GuC H/W registers, bits, etc */
#define GUC_STATUS _MMIO(0xc000) #define GUC_STATUS XE_REG(0xc000)
#define GS_AUTH_STATUS_MASK REG_GENMASK(31, 30) #define GS_AUTH_STATUS_MASK REG_GENMASK(31, 30)
#define GS_AUTH_STATUS_BAD REG_FIELD_PREP(GS_AUTH_STATUS_MASK, 0x1) #define GS_AUTH_STATUS_BAD REG_FIELD_PREP(GS_AUTH_STATUS_MASK, 0x1)
#define GS_AUTH_STATUS_GOOD REG_FIELD_PREP(GS_AUTH_STATUS_MASK, 0x2) #define GS_AUTH_STATUS_GOOD REG_FIELD_PREP(GS_AUTH_STATUS_MASK, 0x2)
...@@ -27,52 +27,52 @@ ...@@ -27,52 +27,52 @@
#define GS_BOOTROM_JUMP_PASSED REG_FIELD_PREP(GS_BOOTROM_MASK, 0x76) #define GS_BOOTROM_JUMP_PASSED REG_FIELD_PREP(GS_BOOTROM_MASK, 0x76)
#define GS_MIA_IN_RESET REG_BIT(0) #define GS_MIA_IN_RESET REG_BIT(0)
#define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4) #define SOFT_SCRATCH(n) XE_REG(0xc180 + (n) * 4)
#define SOFT_SCRATCH_COUNT 16 #define SOFT_SCRATCH_COUNT 16
#define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4) #define UOS_RSA_SCRATCH(i) XE_REG(0xc200 + (i) * 4)
#define UOS_RSA_SCRATCH_COUNT 64 #define UOS_RSA_SCRATCH_COUNT 64
#define DMA_ADDR_0_LOW _MMIO(0xc300) #define DMA_ADDR_0_LOW XE_REG(0xc300)
#define DMA_ADDR_0_HIGH _MMIO(0xc304) #define DMA_ADDR_0_HIGH XE_REG(0xc304)
#define DMA_ADDR_1_LOW _MMIO(0xc308) #define DMA_ADDR_1_LOW XE_REG(0xc308)
#define DMA_ADDR_1_HIGH _MMIO(0xc30c) #define DMA_ADDR_1_HIGH XE_REG(0xc30c)
#define DMA_ADDR_SPACE_MASK REG_GENMASK(20, 16) #define DMA_ADDR_SPACE_MASK REG_GENMASK(20, 16)
#define DMA_ADDRESS_SPACE_WOPCM REG_FIELD_PREP(DMA_ADDR_SPACE_MASK, 7) #define DMA_ADDRESS_SPACE_WOPCM REG_FIELD_PREP(DMA_ADDR_SPACE_MASK, 7)
#define DMA_COPY_SIZE _MMIO(0xc310) #define DMA_COPY_SIZE XE_REG(0xc310)
#define DMA_CTRL _MMIO(0xc314) #define DMA_CTRL XE_REG(0xc314)
#define HUC_UKERNEL REG_BIT(9) #define HUC_UKERNEL REG_BIT(9)
#define UOS_MOVE REG_BIT(4) #define UOS_MOVE REG_BIT(4)
#define START_DMA REG_BIT(0) #define START_DMA REG_BIT(0)
#define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340) #define DMA_GUC_WOPCM_OFFSET XE_REG(0xc340)
#define GUC_WOPCM_OFFSET_SHIFT 14 #define GUC_WOPCM_OFFSET_SHIFT 14
#define GUC_WOPCM_OFFSET_MASK REG_GENMASK(31, GUC_WOPCM_OFFSET_SHIFT) #define GUC_WOPCM_OFFSET_MASK REG_GENMASK(31, GUC_WOPCM_OFFSET_SHIFT)
#define HUC_LOADING_AGENT_GUC REG_BIT(1) #define HUC_LOADING_AGENT_GUC REG_BIT(1)
#define GUC_WOPCM_OFFSET_VALID REG_BIT(0) #define GUC_WOPCM_OFFSET_VALID REG_BIT(0)
#define GUC_MAX_IDLE_COUNT _MMIO(0xc3e4) #define GUC_MAX_IDLE_COUNT XE_REG(0xc3e4)
#define HUC_STATUS2 _MMIO(0xd3b0) #define HUC_STATUS2 XE_REG(0xd3b0)
#define HUC_FW_VERIFIED REG_BIT(7) #define HUC_FW_VERIFIED REG_BIT(7)
#define HUC_KERNEL_LOAD_INFO _MMIO(0xc1dc) #define HUC_KERNEL_LOAD_INFO XE_REG(0xc1dc)
#define HUC_LOAD_SUCCESSFUL REG_BIT(0) #define HUC_LOAD_SUCCESSFUL REG_BIT(0)
#define GUC_WOPCM_SIZE _MMIO(0xc050) #define GUC_WOPCM_SIZE XE_REG(0xc050)
#define GUC_WOPCM_SIZE_MASK REG_GENMASK(31, 12) #define GUC_WOPCM_SIZE_MASK REG_GENMASK(31, 12)
#define GUC_WOPCM_SIZE_LOCKED REG_BIT(0) #define GUC_WOPCM_SIZE_LOCKED REG_BIT(0)
#define GT_PM_CONFIG _MMIO(0x13816c) #define GT_PM_CONFIG XE_REG(0x13816c)
#define GT_DOORBELL_ENABLE REG_BIT(0) #define GT_DOORBELL_ENABLE REG_BIT(0)
#define GTCR _MMIO(0x4274) #define GTCR XE_REG(0x4274)
#define GTCR_INVALIDATE REG_BIT(0) #define GTCR_INVALIDATE REG_BIT(0)
#define GUC_TLB_INV_CR _MMIO(0xcee8) #define GUC_TLB_INV_CR XE_REG(0xcee8)
#define GUC_TLB_INV_CR_INVALIDATE REG_BIT(0) #define GUC_TLB_INV_CR_INVALIDATE REG_BIT(0)
#define GUC_ARAT_C6DIS _MMIO(0xa178) #define GUC_ARAT_C6DIS XE_REG(0xa178)
#define GUC_SHIM_CONTROL _MMIO(0xc064) #define GUC_SHIM_CONTROL XE_REG(0xc064)
#define PVC_GUC_MOCS_INDEX_MASK REG_GENMASK(25, 24) #define PVC_GUC_MOCS_INDEX_MASK REG_GENMASK(25, 24)
#define PVC_GUC_MOCS_UC_INDEX 1 #define PVC_GUC_MOCS_UC_INDEX 1
#define PVC_GUC_MOCS_INDEX(index) REG_FIELD_PREP(PVC_GUC_MOCS_INDEX_MASK, \ #define PVC_GUC_MOCS_INDEX(index) REG_FIELD_PREP(PVC_GUC_MOCS_INDEX_MASK, \
...@@ -87,9 +87,9 @@ ...@@ -87,9 +87,9 @@
#define GUC_DISABLE_SRAM_INIT_TO_ZEROES REG_BIT(0) #define GUC_DISABLE_SRAM_INIT_TO_ZEROES REG_BIT(0)
#define GUC_SEND_INTERRUPT _MMIO(0xc4c8) #define GUC_SEND_INTERRUPT XE_REG(0xc4c8)
#define GUC_SEND_TRIGGER REG_BIT(0) #define GUC_SEND_TRIGGER REG_BIT(0)
#define GUC_HOST_INTERRUPT _MMIO(0x1901f0) #define GUC_HOST_INTERRUPT XE_REG(0x1901f0)
#define GUC_NUM_DOORBELLS 256 #define GUC_NUM_DOORBELLS 256
...@@ -103,24 +103,24 @@ struct guc_doorbell_info { ...@@ -103,24 +103,24 @@ struct guc_doorbell_info {
u32 reserved[14]; u32 reserved[14];
} __packed; } __packed;
#define DRBREGL(x) _MMIO(0x1000 + (x) * 8) #define DRBREGL(x) XE_REG(0x1000 + (x) * 8)
#define DRB_VALID REG_BIT(0) #define DRB_VALID REG_BIT(0)
#define DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4) #define DRBREGU(x) XE_REG(0x1000 + (x) * 8 + 4)
#define DIST_DBS_POPULATED _MMIO(0xd08) #define DIST_DBS_POPULATED XE_REG(0xd08)
#define DOORBELLS_PER_SQIDI_MASK REG_GENMASK(23, 16) #define DOORBELLS_PER_SQIDI_MASK REG_GENMASK(23, 16)
#define SQIDIS_DOORBELL_EXIST_MASK REG_GENMASK(15, 0) #define SQIDIS_DOORBELL_EXIST_MASK REG_GENMASK(15, 0)
#define GUC_BCS_RCS_IER _MMIO(0xC550) #define GUC_BCS_RCS_IER XE_REG(0xC550)
#define GUC_VCS2_VCS1_IER _MMIO(0xC554) #define GUC_VCS2_VCS1_IER XE_REG(0xC554)
#define GUC_WD_VECS_IER _MMIO(0xC558) #define GUC_WD_VECS_IER XE_REG(0xC558)
#define GUC_PM_P24C_IER _MMIO(0xC55C) #define GUC_PM_P24C_IER XE_REG(0xC55C)
#define VF_SW_FLAG(n) _MMIO(0x190240 + (n) * 4) #define VF_SW_FLAG(n) XE_REG(0x190240 + (n) * 4)
#define VF_SW_FLAG_COUNT 4 #define VF_SW_FLAG_COUNT 4
#define MED_VF_SW_FLAG(n) _MMIO(0x190310 + (n) * 4) #define MED_VF_SW_FLAG(n) XE_REG(0x190310 + (n) * 4)
#define MED_VF_SW_FLAG_COUNT 4 #define MED_VF_SW_FLAG_COUNT 4
/* GuC Interrupt Vector */ /* GuC Interrupt Vector */
#define GUC_INTR_GUC2HOST BIT(15) #define GUC_INTR_GUC2HOST BIT(15)
......
drivers/gpu/drm/xe/regs/xe_reg_defs.h
View file @ 3512a78a
...@@ -94,13 +94,4 @@ struct xe_reg_mcr { ...@@ -94,13 +94,4 @@ struct xe_reg_mcr {
.__reg = XE_REG_INITIALIZER(r_, ##__VA_ARGS__, .mcr = 1) \ .__reg = XE_REG_INITIALIZER(r_, ##__VA_ARGS__, .mcr = 1) \
}) })
/*
* TODO: remove these once the register declarations are not using them anymore
*/
#undef _MMIO
#undef MCR_REG
#define _MMIO(r_) ((const struct xe_reg){ .reg = r_ })
#define MCR_REG(r_) ((const struct xe_reg_mcr){ .__reg.reg = r_, \
.__reg.mcr = 1 })
#endif #endif
drivers/gpu/drm/xe/regs/xe_regs.h
View file @ 3512a78a
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
#include "regs/xe_reg_defs.h" #include "regs/xe_reg_defs.h"
#define GU_CNTL _MMIO(0x101010) #define GU_CNTL XE_REG(0x101010)
#define LMEM_INIT REG_BIT(7) #define LMEM_INIT REG_BIT(7)
#define RENDER_RING_BASE 0x02000 #define RENDER_RING_BASE 0x02000
...@@ -42,18 +42,18 @@ ...@@ -42,18 +42,18 @@
#define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
#define GT_RENDER_USER_INTERRUPT REG_BIT(0) #define GT_RENDER_USER_INTERRUPT REG_BIT(0)
#define FF_THREAD_MODE _MMIO(0x20a0) #define FF_THREAD_MODE XE_REG(0x20a0)
#define FF_TESSELATION_DOP_GATE_DISABLE BIT(19) #define FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
#define PVC_RP_STATE_CAP _MMIO(0x281014) #define PVC_RP_STATE_CAP XE_REG(0x281014)
#define MTL_RP_STATE_CAP _MMIO(0x138000) #define MTL_RP_STATE_CAP XE_REG(0x138000)
#define MTL_MEDIAP_STATE_CAP _MMIO(0x138020) #define MTL_MEDIAP_STATE_CAP XE_REG(0x138020)
#define MTL_RP0_CAP_MASK REG_GENMASK(8, 0) #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
#define MTL_RPN_CAP_MASK REG_GENMASK(24, 16) #define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
#define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c) #define MTL_GT_RPE_FREQUENCY XE_REG(0x13800c)
#define MTL_MPE_FREQUENCY _MMIO(0x13802c) #define MTL_MPE_FREQUENCY XE_REG(0x13802c)
#define MTL_RPE_MASK REG_GENMASK(8, 0) #define MTL_RPE_MASK REG_GENMASK(8, 0)
#define TRANSCODER_A_OFFSET 0x60000 #define TRANSCODER_A_OFFSET 0x60000
...@@ -69,32 +69,32 @@ ...@@ -69,32 +69,32 @@
#define PIPE_DSI0_OFFSET 0x7b000 #define PIPE_DSI0_OFFSET 0x7b000
#define PIPE_DSI1_OFFSET 0x7b800 #define PIPE_DSI1_OFFSET 0x7b800
#define SOFTWARE_FLAGS_SPR33 _MMIO(0x4f084) #define SOFTWARE_FLAGS_SPR33 XE_REG(0x4f084)
#define PCU_IRQ_OFFSET 0x444e0 #define PCU_IRQ_OFFSET 0x444e0
#define GU_MISC_IRQ_OFFSET 0x444f0 #define GU_MISC_IRQ_OFFSET 0x444f0
#define GU_MISC_GSE REG_BIT(27) #define GU_MISC_GSE REG_BIT(27)
#define GFX_MSTR_IRQ _MMIO(0x190010) #define GFX_MSTR_IRQ XE_REG(0x190010)
#define MASTER_IRQ REG_BIT(31) #define MASTER_IRQ REG_BIT(31)
#define GU_MISC_IRQ REG_BIT(29) #define GU_MISC_IRQ REG_BIT(29)
#define DISPLAY_IRQ REG_BIT(16) #define DISPLAY_IRQ REG_BIT(16)
#define GT_DW_IRQ(x) REG_BIT(x) #define GT_DW_IRQ(x) REG_BIT(x)
#define DG1_MSTR_TILE_INTR _MMIO(0x190008) #define DG1_MSTR_TILE_INTR XE_REG(0x190008)
#define DG1_MSTR_IRQ REG_BIT(31) #define DG1_MSTR_IRQ REG_BIT(31)
#define DG1_MSTR_TILE(t) REG_BIT(t) #define DG1_MSTR_TILE(t) REG_BIT(t)
#define TIMESTAMP_OVERRIDE _MMIO(0x44074) #define TIMESTAMP_OVERRIDE XE_REG(0x44074)
#define TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK REG_GENMASK(15, 12) #define TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK REG_GENMASK(15, 12)
#define TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK REG_GENMASK(9, 0) #define TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK REG_GENMASK(9, 0)
#define GGC _MMIO(0x108040) #define GGC XE_REG(0x108040)
#define GMS_MASK REG_GENMASK(15, 8) #define GMS_MASK REG_GENMASK(15, 8)
#define GGMS_MASK REG_GENMASK(7, 6) #define GGMS_MASK REG_GENMASK(7, 6)
#define GSMBASE _MMIO(0x108100) #define GSMBASE XE_REG(0x108100)
#define DSMBASE _MMIO(0x1080C0) #define DSMBASE XE_REG(0x1080C0)
#define BDSM_MASK REG_GENMASK64(63, 20) #define BDSM_MASK REG_GENMASK64(63, 20)
#endif #endif
drivers/gpu/drm/xe/tests/xe_rtp_test.c
View file @ 3512a78a
...@@ -18,17 +18,17 @@ ...@@ -18,17 +18,17 @@
#include "xe_reg_sr.h" #include "xe_reg_sr.h"
#include "xe_rtp.h" #include "xe_rtp.h"
#undef _MMIO #undef XE_REG
#undef MCR_REG #undef XE_REG_MCR
#define _MMIO(x) _XE_RTP_REG(x) #define XE_REG(x, ...) _XE_RTP_REG(x)
#define MCR_REG(x) _XE_RTP_MCR_REG(x) #define XE_REG_MCR(x, ...) _XE_RTP_MCR_REG(x)
#define REGULAR_REG1 _MMIO(1) #define REGULAR_REG1 XE_REG(1)
#define REGULAR_REG2 _MMIO(2) #define REGULAR_REG2 XE_REG(2)
#define REGULAR_REG3 _MMIO(3) #define REGULAR_REG3 XE_REG(3)
#define MCR_REG1 MCR_REG(1) #define MCR_REG1 XE_REG_MCR(1)
#define MCR_REG2 MCR_REG(2) #define MCR_REG2 XE_REG_MCR(2)
#define MCR_REG3 MCR_REG(3) #define MCR_REG3 XE_REG_MCR(3)
struct rtp_test_case { struct rtp_test_case {
const char *name; const char *name;
......
drivers/gpu/drm/xe/xe_ggtt.c
View file @ 3512a78a
...@@ -185,11 +185,11 @@ int xe_ggtt_init(struct xe_gt *gt, struct xe_ggtt *ggtt) ...@@ -185,11 +185,11 @@ int xe_ggtt_init(struct xe_gt *gt, struct xe_ggtt *ggtt)
return err; return err;
} }
#define GUC_TLB_INV_CR _MMIO(0xcee8) #define GUC_TLB_INV_CR XE_REG(0xcee8)
#define GUC_TLB_INV_CR_INVALIDATE REG_BIT(0) #define GUC_TLB_INV_CR_INVALIDATE REG_BIT(0)
#define PVC_GUC_TLB_INV_DESC0 _MMIO(0xcf7c) #define PVC_GUC_TLB_INV_DESC0 XE_REG(0xcf7c)
#define PVC_GUC_TLB_INV_DESC0_VALID REG_BIT(0) #define PVC_GUC_TLB_INV_DESC0_VALID REG_BIT(0)
#define PVC_GUC_TLB_INV_DESC1 _MMIO(0xcf80) #define PVC_GUC_TLB_INV_DESC1 XE_REG(0xcf80)
#define PVC_GUC_TLB_INV_DESC1_INVALIDATE REG_BIT(6) #define PVC_GUC_TLB_INV_DESC1_INVALIDATE REG_BIT(6)
void xe_ggtt_invalidate(struct xe_gt *gt) void xe_ggtt_invalidate(struct xe_gt *gt)
......
drivers/gpu/drm/xe/xe_guc.c
View file @ 3512a78a
...@@ -22,6 +22,8 @@ ...@@ -22,6 +22,8 @@
#include "xe_uc_fw.h" #include "xe_uc_fw.h"
#include "xe_wopcm.h" #include "xe_wopcm.h"
#define MEDIA_GUC_HOST_INTERRUPT XE_REG(0x190304)
static struct xe_gt * static struct xe_gt *
guc_to_gt(struct xe_guc *guc) guc_to_gt(struct xe_guc *guc)
{ {
...@@ -244,8 +246,6 @@ static void guc_write_params(struct xe_guc *guc) ...@@ -244,8 +246,6 @@ static void guc_write_params(struct xe_guc *guc)
xe_mmio_write32(gt, SOFT_SCRATCH(1 + i).reg, guc->params[i]); xe_mmio_write32(gt, SOFT_SCRATCH(1 + i).reg, guc->params[i]);
} }
#define MEDIA_GUC_HOST_INTERRUPT _MMIO(0x190304)
int xe_guc_init(struct xe_guc *guc) int xe_guc_init(struct xe_guc *guc)
{ {
struct xe_device *xe = guc_to_xe(guc); struct xe_device *xe = guc_to_xe(guc);
......
drivers/gpu/drm/xe/xe_guc_pc.c
View file @ 3512a78a
...@@ -23,18 +23,18 @@ ...@@ -23,18 +23,18 @@
#define MCHBAR_MIRROR_BASE_SNB 0x140000 #define MCHBAR_MIRROR_BASE_SNB 0x140000
#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998) #define GEN6_RP_STATE_CAP XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5998)
#define RP0_MASK REG_GENMASK(7, 0) #define RP0_MASK REG_GENMASK(7, 0)
#define RP1_MASK REG_GENMASK(15, 8) #define RP1_MASK REG_GENMASK(15, 8)
#define RPN_MASK REG_GENMASK(23, 16) #define RPN_MASK REG_GENMASK(23, 16)
#define GEN10_FREQ_INFO_REC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5ef0) #define GEN10_FREQ_INFO_REC XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
#define RPE_MASK REG_GENMASK(15, 8) #define RPE_MASK REG_GENMASK(15, 8)
#define GEN12_RPSTAT1 _MMIO(0x1381b4) #define GEN12_RPSTAT1 XE_REG(0x1381b4)
#define GEN12_CAGF_MASK REG_GENMASK(19, 11) #define GEN12_CAGF_MASK REG_GENMASK(19, 11)
#define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60) #define MTL_MIRROR_TARGET_WP1 XE_REG(0xc60)
#define MTL_CAGF_MASK REG_GENMASK(8, 0) #define MTL_CAGF_MASK REG_GENMASK(8, 0)
#define GT_FREQUENCY_MULTIPLIER 50 #define GT_FREQUENCY_MULTIPLIER 50
......
drivers/gpu/drm/xe/xe_irq.c
View file @ 3512a78a
...@@ -22,9 +22,9 @@ ...@@ -22,9 +22,9 @@
* Interrupt registers for a unit are always consecutive and ordered * Interrupt registers for a unit are always consecutive and ordered
* ISR, IMR, IIR, IER. * ISR, IMR, IIR, IER.
*/ */
#define IMR(offset) _MMIO(offset + 0x4) #define IMR(offset) XE_REG(offset + 0x4)
#define IIR(offset) _MMIO(offset + 0x8) #define IIR(offset) XE_REG(offset + 0x8)
#define IER(offset) _MMIO(offset + 0xc) #define IER(offset) XE_REG(offset + 0xc)
static void assert_iir_is_zero(struct xe_gt *gt, struct xe_reg reg) static void assert_iir_is_zero(struct xe_gt *gt, struct xe_reg reg)
{ {
......
drivers/gpu/drm/xe/xe_mmio.c
View file @ 3512a78a
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
#include "xe_macros.h" #include "xe_macros.h"
#include "xe_module.h" #include "xe_module.h"
#define XEHP_MTCFG_ADDR _MMIO(0x101800) #define XEHP_MTCFG_ADDR XE_REG(0x101800)
#define TILE_COUNT REG_GENMASK(15, 8) #define TILE_COUNT REG_GENMASK(15, 8)
#define GEN12_LMEM_BAR 2 #define GEN12_LMEM_BAR 2
......
drivers/gpu/drm/xe/xe_mocs.c
View file @ 3512a78a
...@@ -477,8 +477,8 @@ static void __init_mocs_table(struct xe_gt *gt, ...@@ -477,8 +477,8 @@ static void __init_mocs_table(struct xe_gt *gt,
for (i = 0; for (i = 0;
i < info->n_entries ? (mocs = get_entry_control(info, i)), 1 : 0; i < info->n_entries ? (mocs = get_entry_control(info, i)), 1 : 0;
i++) { i++) {
mocs_dbg(&gt->xe->drm, "%d 0x%x 0x%x\n", i, _MMIO(addr + i * 4).reg, mocs); mocs_dbg(&gt->xe->drm, "%d 0x%x 0x%x\n", i, XE_REG(addr + i * 4).reg, mocs);
xe_mmio_write32(gt, _MMIO(addr + i * 4).reg, mocs); xe_mmio_write32(gt, XE_REG(addr + i * 4).reg, mocs);
} }
} }
......
drivers/gpu/drm/xe/xe_pat.c
View file @ 3512a78a
...@@ -71,7 +71,7 @@ static void program_pat(struct xe_gt *gt, const u32 table[], int n_entries) ...@@ -71,7 +71,7 @@ static void program_pat(struct xe_gt *gt, const u32 table[], int n_entries)
static void program_pat_mcr(struct xe_gt *gt, const u32 table[], int n_entries) static void program_pat_mcr(struct xe_gt *gt, const u32 table[], int n_entries)
{ {
for (int i = 0; i < n_entries; i++) for (int i = 0; i < n_entries; i++)
xe_gt_mcr_multicast_write(gt, MCR_REG(_PAT_INDEX(i)), table[i]); xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_INDEX(i)), table[i]);
} }
void xe_pat_init(struct xe_gt *gt) void xe_pat_init(struct xe_gt *gt)
......
drivers/gpu/drm/xe/xe_pcode_api.h
View file @ 3512a78a
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
#include "regs/xe_reg_defs.h" #include "regs/xe_reg_defs.h"
#define PCODE_MAILBOX _MMIO(0x138124) #define PCODE_MAILBOX XE_REG(0x138124)
#define PCODE_READY REG_BIT(31) #define PCODE_READY REG_BIT(31)
#define PCODE_MB_PARAM2 REG_GENMASK(23, 16) #define PCODE_MB_PARAM2 REG_GENMASK(23, 16)
#define PCODE_MB_PARAM1 REG_GENMASK(15, 8) #define PCODE_MB_PARAM1 REG_GENMASK(15, 8)
...@@ -22,8 +22,8 @@ ...@@ -22,8 +22,8 @@
#define PCODE_GT_RATIO_OUT_OF_RANGE 0x10 #define PCODE_GT_RATIO_OUT_OF_RANGE 0x10
#define PCODE_REJECTED 0x11 #define PCODE_REJECTED 0x11
#define PCODE_DATA0 _MMIO(0x138128) #define PCODE_DATA0 XE_REG(0x138128)
#define PCODE_DATA1 _MMIO(0x13812C) #define PCODE_DATA1 XE_REG(0x13812C)
/* Min Freq QOS Table */ /* Min Freq QOS Table */
#define PCODE_WRITE_MIN_FREQ_TABLE 0x8 #define PCODE_WRITE_MIN_FREQ_TABLE 0x8
......
drivers/gpu/drm/xe/xe_reg_sr.c
View file @ 3512a78a
...@@ -151,7 +151,7 @@ static void apply_one_mmio(struct xe_gt *gt, u32 reg, ...@@ -151,7 +151,7 @@ static void apply_one_mmio(struct xe_gt *gt, u32 reg,
val = (entry->clr_bits ?: entry->set_bits) << 16; val = (entry->clr_bits ?: entry->set_bits) << 16;
else if (entry->clr_bits + 1) else if (entry->clr_bits + 1)
val = (entry->reg_type == XE_RTP_REG_MCR ? val = (entry->reg_type == XE_RTP_REG_MCR ?
xe_gt_mcr_unicast_read_any(gt, MCR_REG(reg)) : xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(reg)) :
xe_mmio_read32(gt, reg)) & (~entry->clr_bits); xe_mmio_read32(gt, reg)) & (~entry->clr_bits);
else else
val = 0; val = 0;
...@@ -166,7 +166,7 @@ static void apply_one_mmio(struct xe_gt *gt, u32 reg, ...@@ -166,7 +166,7 @@ static void apply_one_mmio(struct xe_gt *gt, u32 reg,
drm_dbg(&xe->drm, "REG[0x%x] = 0x%08x", reg, val); drm_dbg(&xe->drm, "REG[0x%x] = 0x%08x", reg, val);
if (entry->reg_type == XE_RTP_REG_MCR) if (entry->reg_type == XE_RTP_REG_MCR)
xe_gt_mcr_multicast_write(gt, MCR_REG(reg), val); xe_gt_mcr_multicast_write(gt, XE_REG_MCR(reg), val);
else else
xe_mmio_write32(gt, reg, val); xe_mmio_write32(gt, reg, val);
} }
......
drivers/gpu/drm/xe/xe_reg_whitelist.c
View file @ 3512a78a
...@@ -11,10 +11,10 @@ ...@@ -11,10 +11,10 @@
#include "xe_platform_types.h" #include "xe_platform_types.h"
#include "xe_rtp.h" #include "xe_rtp.h"
#undef _MMIO #undef XE_REG
#undef MCR_REG #undef XE_REG_MCR
#define _MMIO(x) _XE_RTP_REG(x) #define XE_REG(x, ...) _XE_RTP_REG(x)
#define MCR_REG(x) _XE_RTP_MCR_REG(x) #define XE_REG_MCR(x, ...) _XE_RTP_MCR_REG(x)
static bool match_not_render(const struct xe_gt *gt, static bool match_not_render(const struct xe_gt *gt,
const struct xe_hw_engine *hwe) const struct xe_hw_engine *hwe)
...@@ -45,10 +45,10 @@ static const struct xe_rtp_entry register_whitelist[] = { ...@@ -45,10 +45,10 @@ static const struct xe_rtp_entry register_whitelist[] = {
}, },
{ XE_RTP_NAME("16014440446"), { XE_RTP_NAME("16014440446"),
XE_RTP_RULES(PLATFORM(PVC)), XE_RTP_RULES(PLATFORM(PVC)),
XE_RTP_ACTIONS(WHITELIST(_MMIO(0x4400), XE_RTP_ACTIONS(WHITELIST(XE_REG(0x4400),
RING_FORCE_TO_NONPRIV_DENY | RING_FORCE_TO_NONPRIV_DENY |
RING_FORCE_TO_NONPRIV_RANGE_64), RING_FORCE_TO_NONPRIV_RANGE_64),
WHITELIST(_MMIO(0x4500), WHITELIST(XE_REG(0x4500),
RING_FORCE_TO_NONPRIV_DENY | RING_FORCE_TO_NONPRIV_DENY |
RING_FORCE_TO_NONPRIV_RANGE_64)) RING_FORCE_TO_NONPRIV_RANGE_64))
}, },
......
drivers/gpu/drm/xe/xe_rtp.h
View file @ 3512a78a
...@@ -197,7 +197,7 @@ struct xe_reg_sr; ...@@ -197,7 +197,7 @@ struct xe_reg_sr;
* XE_RTP_ACTION_WR - Helper to write a value to the register, overriding all * XE_RTP_ACTION_WR - Helper to write a value to the register, overriding all
* the bits * the bits
* @reg_: Register * @reg_: Register
* @reg_type_: Register type - automatically expanded by MCR_REG/_MMIO * @reg_type_: Register type - automatically expanded by XE_REG
* @val_: Value to set * @val_: Value to set
* @...: Additional fields to override in the struct xe_rtp_action entry * @...: Additional fields to override in the struct xe_rtp_action entry
* *
...@@ -213,7 +213,7 @@ struct xe_reg_sr; ...@@ -213,7 +213,7 @@ struct xe_reg_sr;
/** /**
* XE_RTP_ACTION_SET - Set bits from @val_ in the register. * XE_RTP_ACTION_SET - Set bits from @val_ in the register.
* @reg_: Register * @reg_: Register
* @reg_type_: Register type - automatically expanded by MCR_REG/_MMIO * @reg_type_: Register type - automatically expanded by XE_REG
* @val_: Bits to set in the register * @val_: Bits to set in the register
* @...: Additional fields to override in the struct xe_rtp_action entry * @...: Additional fields to override in the struct xe_rtp_action entry
* *
...@@ -232,7 +232,7 @@ struct xe_reg_sr; ...@@ -232,7 +232,7 @@ struct xe_reg_sr;
/** /**
* XE_RTP_ACTION_CLR: Clear bits from @val_ in the register. * XE_RTP_ACTION_CLR: Clear bits from @val_ in the register.
* @reg_: Register * @reg_: Register
* @reg_type_: Register type - automatically expanded by MCR_REG/_MMIO * @reg_type_: Register type - automatically expanded by XE_REG
* @val_: Bits to clear in the register * @val_: Bits to clear in the register
* @...: Additional fields to override in the struct xe_rtp_action entry * @...: Additional fields to override in the struct xe_rtp_action entry
* *
...@@ -251,7 +251,7 @@ struct xe_reg_sr; ...@@ -251,7 +251,7 @@ struct xe_reg_sr;
/** /**
* XE_RTP_ACTION_FIELD_SET: Set a bit range * XE_RTP_ACTION_FIELD_SET: Set a bit range
* @reg_: Register * @reg_: Register
* @reg_type_: Register type - automatically expanded by MCR_REG/_MMIO * @reg_type_: Register type - automatically expanded by XE_REG
* @mask_bits_: Mask of bits to be changed in the register, forming a field * @mask_bits_: Mask of bits to be changed in the register, forming a field
* @val_: Value to set in the field denoted by @mask_bits_ * @val_: Value to set in the field denoted by @mask_bits_
* @...: Additional fields to override in the struct xe_rtp_action entry * @...: Additional fields to override in the struct xe_rtp_action entry
...@@ -274,7 +274,7 @@ struct xe_reg_sr; ...@@ -274,7 +274,7 @@ struct xe_reg_sr;
/** /**
* XE_RTP_ACTION_WHITELIST - Add register to userspace whitelist * XE_RTP_ACTION_WHITELIST - Add register to userspace whitelist
* @reg_: Register * @reg_: Register
* @reg_type_: Register type - automatically expanded by MCR_REG/_MMIO * @reg_type_: Register type - automatically expanded by XE_REG
* @val_: Whitelist-specific flags to set * @val_: Whitelist-specific flags to set
* @...: Additional fields to override in the struct xe_rtp_action entry * @...: Additional fields to override in the struct xe_rtp_action entry
* *
......
drivers/gpu/drm/xe/xe_tuning.c
View file @ 3512a78a
...@@ -12,10 +12,10 @@ ...@@ -12,10 +12,10 @@
#include "xe_platform_types.h" #include "xe_platform_types.h"
#include "xe_rtp.h" #include "xe_rtp.h"
#undef _MMIO #undef XE_REG
#undef MCR_REG #undef XE_REG_MCR
#define _MMIO(x) _XE_RTP_REG(x) #define XE_REG(x, ...) _XE_RTP_REG(x)
#define MCR_REG(x) _XE_RTP_MCR_REG(x) #define XE_REG_MCR(x, ...) _XE_RTP_MCR_REG(x)
static const struct xe_rtp_entry gt_tunings[] = { static const struct xe_rtp_entry gt_tunings[] = {
{ XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"), { XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"),
......
drivers/gpu/drm/xe/xe_wa.c
View file @ 3512a78a
...@@ -87,10 +87,10 @@ ...@@ -87,10 +87,10 @@
* a more declarative approach rather than procedural. * a more declarative approach rather than procedural.
*/ */
#undef _MMIO #undef XE_REG
#undef MCR_REG #undef XE_REG_MCR
#define _MMIO(x) _XE_RTP_REG(x) #define XE_REG(x, ...) _XE_RTP_REG(x)
#define MCR_REG(x) _XE_RTP_MCR_REG(x) #define XE_REG_MCR(x, ...) _XE_RTP_MCR_REG(x)
__diag_push(); __diag_push();
__diag_ignore_all("-Woverride-init", "Allow field overrides in table"); __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
......
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