Commit 3ac5fa3f authored by Dave Airlie's avatar Dave Airlie

Merge tag 'drm-intel-next-2023-10-19' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

- Add new DG2 PCI IDs (Shekhar)
- Remove watchdog timers for PSR on Lunar Lake (Mika Kahola)
- DSB changes for proper handling of LUT programming (Ville)
- Store DSC DPCD capabilities in the connector (Imre)
- Clean up zero initializers (Ville)
- Remove Meteor Lake force_probe protection (RK)
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZTFW4g6duLtp+Wy0@intel.com
parents 27442758 213c4367
......@@ -153,7 +153,7 @@ static acpi_handle intel_dsm_pci_probe(struct pci_dev *pdev)
static bool intel_dsm_detect(void)
{
acpi_handle dhandle = NULL;
char acpi_method_name[255] = { 0 };
char acpi_method_name[255] = {};
struct acpi_buffer buffer = {sizeof(acpi_method_name), acpi_method_name};
struct pci_dev *pdev = NULL;
int vga_count = 0;
......
......@@ -1895,9 +1895,6 @@ void intel_color_prepare_commit(struct intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
/* FIXME DSB has issues loading LUTs, disable it for now */
return;
if (!crtc_state->hw.active ||
intel_crtc_needs_modeset(crtc_state))
return;
......
......@@ -3009,7 +3009,7 @@ void intel_c10pll_state_verify(struct intel_atomic_state *state,
struct drm_i915_private *i915 = to_i915(state->base.dev);
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_c10pll_state mpllb_hw_state = { 0 };
struct intel_c10pll_state mpllb_hw_state = {};
const struct intel_c10pll_state *mpllb_sw_state = &new_crtc_state->cx0pll_state.c10;
struct intel_encoder *encoder;
enum phy phy;
......
......@@ -1191,8 +1191,8 @@ DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability);
static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
{
struct drm_connector *connector = m->private;
struct drm_device *dev = connector->dev;
struct intel_connector *connector = to_intel_connector(m->private);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct drm_crtc *crtc;
struct intel_dp *intel_dp;
struct drm_modeset_acquire_ctx ctx;
......@@ -1204,7 +1204,7 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
do {
try_again = false;
ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
ret = drm_modeset_lock(&i915->drm.mode_config.connection_mutex,
&ctx);
if (ret) {
if (ret == -EDEADLK && !drm_modeset_backoff(&ctx)) {
......@@ -1213,8 +1213,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
}
break;
}
crtc = connector->state->crtc;
if (connector->status != connector_status_connected || !crtc) {
crtc = connector->base.state->crtc;
if (connector->base.status != connector_status_connected || !crtc) {
ret = -ENODEV;
break;
}
......@@ -1229,24 +1229,24 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
} else if (ret) {
break;
}
intel_dp = intel_attached_dp(to_intel_connector(connector));
intel_dp = intel_attached_dp(connector);
crtc_state = to_intel_crtc_state(crtc->state);
seq_printf(m, "DSC_Enabled: %s\n",
str_yes_no(crtc_state->dsc.compression_enable));
seq_printf(m, "DSC_Sink_Support: %s\n",
str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
str_yes_no(drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)));
seq_printf(m, "DSC_Output_Format_Sink_Support: RGB: %s YCBCR420: %s YCBCR444: %s\n",
str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
str_yes_no(drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd,
DP_DSC_RGB)),
str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
str_yes_no(drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd,
DP_DSC_YCbCr420_Native)),
str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
str_yes_no(drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd,
DP_DSC_YCbCr444)));
seq_printf(m, "Force_DSC_Enable: %s\n",
str_yes_no(intel_dp->force_dsc_en));
if (!intel_dp_is_edp(intel_dp))
seq_printf(m, "FEC_Sink_Support: %s\n",
str_yes_no(drm_dp_sink_supports_fec(intel_dp->fec_capable)));
str_yes_no(drm_dp_sink_supports_fec(connector->dp.fec_capability)));
} while (try_again);
drm_modeset_drop_locks(&ctx);
......
......@@ -620,6 +620,12 @@ struct intel_connector {
struct intel_dp *mst_port;
struct {
struct drm_dp_aux *dsc_decompression_aux;
u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
u8 fec_capability;
} dp;
/* Work struct to schedule a uevent on link train failure */
struct work_struct modeset_retry_work;
......@@ -1719,10 +1725,8 @@ struct intel_dp {
u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
u8 fec_capable;
u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
/* source rates */
int num_source_rates;
......
This diff is collapsed.
......@@ -116,7 +116,8 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
unsigned int type);
bool intel_digital_port_connected(struct intel_encoder *encoder);
int intel_dp_dsc_compute_max_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
u8 dsc_max_bpc);
u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
......@@ -124,7 +125,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
enum intel_output_format output_format,
u32 pipe_bpp,
u32 timeslots);
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
int mode_clock, int mode_hdisplay,
bool bigjoiner);
bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
......@@ -162,4 +163,6 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
bool dsc,
struct link_config_limits *limits);
void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector);
#endif /* __INTEL_DP_H__ */
......@@ -169,7 +169,7 @@ intel_dp_aux_hdr_get_backlight(struct intel_connector *connector, enum pipe pipe
struct intel_panel *panel = &connector->panel;
struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
u8 tmp;
u8 buf[2] = { 0 };
u8 buf[2] = {};
if (drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &tmp) != 1) {
drm_err(&i915->drm, "[CONNECTOR:%d:%s] Failed to read current backlight mode from DPCD\n",
......@@ -204,7 +204,7 @@ intel_dp_aux_hdr_set_aux_backlight(const struct drm_connector_state *conn_state,
struct intel_connector *connector = to_intel_connector(conn_state->connector);
struct drm_device *dev = connector->base.dev;
struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
u8 buf[4] = { 0 };
u8 buf[4] = {};
buf[0] = level & 0xFF;
buf[1] = (level & 0xFF00) >> 8;
......
......@@ -185,8 +185,6 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
struct drm_connector_state *conn_state,
struct link_config_limits *limits)
{
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
struct intel_dp *intel_dp = &intel_mst->primary->dp;
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
......@@ -194,7 +192,7 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
&crtc_state->hw.adjusted_mode;
int slots = -EINVAL;
int i, num_bpc;
u8 dsc_bpc[3] = {0};
u8 dsc_bpc[3] = {};
int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
u8 dsc_max_bpc;
bool need_timeslot_recalc = false;
......@@ -209,7 +207,7 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
max_bpp = min_t(u8, dsc_max_bpc * 3, limits->pipe.max_bpp);
min_bpp = limits->pipe.min_bpp;
num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
dsc_bpc);
drm_dbg_kms(&i915->drm, "DSC Source supported min bpp %d max bpp %d\n",
......@@ -998,14 +996,14 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
}
if (DISPLAY_VER(dev_priv) >= 10 &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
drm_dp_sink_supports_dsc(intel_connector->dp.dsc_dpcd)) {
/*
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be picked
*/
int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, U8_MAX);
int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_connector, U8_MAX);
if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
if (drm_dp_sink_supports_fec(intel_connector->dp.fec_capability)) {
dsc_max_compressed_bpp =
intel_dp_dsc_get_max_compressed_bpp(dev_priv,
max_link_clock,
......@@ -1016,7 +1014,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
INTEL_OUTPUT_FORMAT_RGB,
pipe_bpp, 64);
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
intel_dp_dsc_get_slice_count(intel_connector,
target_clock,
mode->hdisplay,
bigjoiner);
......@@ -1126,6 +1124,21 @@ static int intel_dp_mst_add_properties(struct intel_dp *intel_dp,
return drm_connector_set_path_property(connector, pathprop);
}
static void
intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
struct intel_connector *connector)
{
u8 dpcd_caps[DP_RECEIVER_CAP_SIZE];
if (!connector->dp.dsc_decompression_aux)
return;
if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd_caps) < 0)
return;
intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV], connector);
}
static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
struct drm_dp_mst_port *port,
const char *pathprop)
......@@ -1159,6 +1172,14 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs);
/*
* TODO: set the AUX for the actual MST port decompressing the stream.
* At the moment the driver only supports enabling this globally in the
* first downstream MST branch, via intel_dp's (root port) AUX.
*/
intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector);
for_each_pipe(dev_priv, pipe) {
struct drm_encoder *enc =
&intel_dp->mst_encoders[pipe]->base.base;
......
......@@ -5,6 +5,7 @@
*/
#include "gem/i915_gem_internal.h"
#include "gem/i915_gem_lmem.h"
#include "i915_drv.h"
#include "i915_irq.h"
......@@ -315,6 +316,8 @@ void intel_dsb_finish(struct intel_dsb *dsb)
DSB_FORCE_DEWAKE, 0);
intel_dsb_align_tail(dsb);
i915_gem_object_flush_map(dsb->vma->obj);
}
static int intel_dsb_dewake_scanline(const struct intel_crtc_state *crtc_state)
......@@ -461,10 +464,19 @@ struct intel_dsb *intel_dsb_prepare(const struct intel_crtc_state *crtc_state,
/* ~1 qword per instruction, full cachelines */
size = ALIGN(max_cmds * 8, CACHELINE_BYTES);
if (HAS_LMEM(i915)) {
obj = i915_gem_object_create_lmem(i915, PAGE_ALIGN(size),
I915_BO_ALLOC_CONTIGUOUS);
if (IS_ERR(obj))
goto out_put_rpm;
} else {
obj = i915_gem_object_create_internal(i915, PAGE_ALIGN(size));
if (IS_ERR(obj))
goto out_put_rpm;
i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
}
vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
if (IS_ERR(vma)) {
i915_gem_object_put(obj);
......
......@@ -781,7 +781,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
struct intel_gmbus *bus = to_intel_gmbus(adapter);
struct drm_i915_private *i915 = bus->i915;
u8 cmd = DRM_HDCP_DDC_AKSV;
u8 buf[DRM_HDCP_KSV_LEN] = { 0 };
u8 buf[DRM_HDCP_KSV_LEN] = {};
struct i2c_msg msgs[] = {
{
.addr = DRM_HDCP_DDC_ADDR,
......
......@@ -13,9 +13,8 @@ int
intel_hdcp_gsc_initiate_session(struct device *dev, struct hdcp_port_data *data,
struct hdcp2_ake_init *ake_data)
{
struct wired_cmd_initiate_hdcp2_session_in session_init_in = { { 0 } };
struct wired_cmd_initiate_hdcp2_session_out
session_init_out = { { 0 } };
struct wired_cmd_initiate_hdcp2_session_in session_init_in = {};
struct wired_cmd_initiate_hdcp2_session_out session_init_out = {};
struct drm_i915_private *i915;
ssize_t byte;
......@@ -71,8 +70,8 @@ intel_hdcp_gsc_verify_receiver_cert_prepare_km(struct device *dev,
*ek_pub_km,
size_t *msg_sz)
{
struct wired_cmd_verify_receiver_cert_in verify_rxcert_in = { { 0 } };
struct wired_cmd_verify_receiver_cert_out verify_rxcert_out = { { 0 } };
struct wired_cmd_verify_receiver_cert_in verify_rxcert_in = {};
struct wired_cmd_verify_receiver_cert_out verify_rxcert_out = {};
struct drm_i915_private *i915;
ssize_t byte;
......@@ -134,8 +133,8 @@ int
intel_hdcp_gsc_verify_hprime(struct device *dev, struct hdcp_port_data *data,
struct hdcp2_ake_send_hprime *rx_hprime)
{
struct wired_cmd_ake_send_hprime_in send_hprime_in = { { 0 } };
struct wired_cmd_ake_send_hprime_out send_hprime_out = { { 0 } };
struct wired_cmd_ake_send_hprime_in send_hprime_in = {};
struct wired_cmd_ake_send_hprime_out send_hprime_out = {};
struct drm_i915_private *i915;
ssize_t byte;
......@@ -182,8 +181,8 @@ int
intel_hdcp_gsc_store_pairing_info(struct device *dev, struct hdcp_port_data *data,
struct hdcp2_ake_send_pairing_info *pairing_info)
{
struct wired_cmd_ake_send_pairing_info_in pairing_info_in = { { 0 } };
struct wired_cmd_ake_send_pairing_info_out pairing_info_out = { { 0 } };
struct wired_cmd_ake_send_pairing_info_in pairing_info_in = {};
struct wired_cmd_ake_send_pairing_info_out pairing_info_out = {};
struct drm_i915_private *i915;
ssize_t byte;
......@@ -233,8 +232,8 @@ intel_hdcp_gsc_initiate_locality_check(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_lc_init *lc_init_data)
{
struct wired_cmd_init_locality_check_in lc_init_in = { { 0 } };
struct wired_cmd_init_locality_check_out lc_init_out = { { 0 } };
struct wired_cmd_init_locality_check_in lc_init_in = {};
struct wired_cmd_init_locality_check_out lc_init_out = {};
struct drm_i915_private *i915;
ssize_t byte;
......@@ -279,8 +278,8 @@ int
intel_hdcp_gsc_verify_lprime(struct device *dev, struct hdcp_port_data *data,
struct hdcp2_lc_send_lprime *rx_lprime)
{
struct wired_cmd_validate_locality_in verify_lprime_in = { { 0 } };
struct wired_cmd_validate_locality_out verify_lprime_out = { { 0 } };
struct wired_cmd_validate_locality_in verify_lprime_in = {};
struct wired_cmd_validate_locality_out verify_lprime_out = {};
struct drm_i915_private *i915;
ssize_t byte;
......@@ -329,8 +328,8 @@ int intel_hdcp_gsc_get_session_key(struct device *dev,
struct hdcp_port_data *data,
struct hdcp2_ske_send_eks *ske_data)
{
struct wired_cmd_get_session_key_in get_skey_in = { { 0 } };
struct wired_cmd_get_session_key_out get_skey_out = { { 0 } };
struct wired_cmd_get_session_key_in get_skey_in = {};
struct wired_cmd_get_session_key_out get_skey_out = {};
struct drm_i915_private *i915;
ssize_t byte;
......@@ -381,8 +380,8 @@ intel_hdcp_gsc_repeater_check_flow_prepare_ack(struct device *dev,
struct hdcp2_rep_send_ack
*rep_send_ack)
{
struct wired_cmd_verify_repeater_in verify_repeater_in = { { 0 } };
struct wired_cmd_verify_repeater_out verify_repeater_out = { { 0 } };
struct wired_cmd_verify_repeater_in verify_repeater_in = {};
struct wired_cmd_verify_repeater_out verify_repeater_out = {};
struct drm_i915_private *i915;
ssize_t byte;
......@@ -442,8 +441,7 @@ int intel_hdcp_gsc_verify_mprime(struct device *dev,
struct hdcp2_rep_stream_ready *stream_ready)
{
struct wired_cmd_repeater_auth_stream_req_in *verify_mprime_in;
struct wired_cmd_repeater_auth_stream_req_out
verify_mprime_out = { { 0 } };
struct wired_cmd_repeater_auth_stream_req_out verify_mprime_out = {};
struct drm_i915_private *i915;
ssize_t byte;
size_t cmd_size;
......@@ -504,8 +502,8 @@ int intel_hdcp_gsc_verify_mprime(struct device *dev,
int intel_hdcp_gsc_enable_authentication(struct device *dev,
struct hdcp_port_data *data)
{
struct wired_cmd_enable_auth_in enable_auth_in = { { 0 } };
struct wired_cmd_enable_auth_out enable_auth_out = { { 0 } };
struct wired_cmd_enable_auth_in enable_auth_in = {};
struct wired_cmd_enable_auth_out enable_auth_out = {};
struct drm_i915_private *i915;
ssize_t byte;
......@@ -549,8 +547,8 @@ int intel_hdcp_gsc_enable_authentication(struct device *dev,
int
intel_hdcp_gsc_close_session(struct device *dev, struct hdcp_port_data *data)
{
struct wired_cmd_close_session_in session_close_in = { { 0 } };
struct wired_cmd_close_session_out session_close_out = { { 0 } };
struct wired_cmd_close_session_in session_close_in = {};
struct wired_cmd_close_session_out session_close_out = {};
struct drm_i915_private *i915;
ssize_t byte;
......
......@@ -166,7 +166,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_mode_fb_cmd2 mode_cmd = { 0 };
struct drm_mode_fb_cmd2 mode_cmd = {};
struct drm_framebuffer *fb = &plane_config->fb->base;
struct i915_vma *vma;
......
......@@ -676,7 +676,9 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
val |= EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
if (DISPLAY_VER(dev_priv) < 20)
val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time);
if (IS_HASWELL(dev_priv))
val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
......@@ -1400,8 +1402,10 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
*/
mask = EDP_PSR_DEBUG_MASK_MEMUP |
EDP_PSR_DEBUG_MASK_HPD |
EDP_PSR_DEBUG_MASK_LPSP |
EDP_PSR_DEBUG_MASK_MAX_SLEEP;
EDP_PSR_DEBUG_MASK_LPSP;
if (DISPLAY_VER(dev_priv) < 20)
mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP;
/*
* No separate pipe reg write mask on hsw/bdw, so have to unmask all
......
......@@ -649,7 +649,7 @@ intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len
static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
{
struct intel_sdvo_set_target_input_args targets = {0};
struct intel_sdvo_set_target_input_args targets = {};
return intel_sdvo_set_value(intel_sdvo,
SDVO_CMD_SET_TARGET_INPUT,
&targets, sizeof(targets));
......
......@@ -1998,7 +1998,7 @@ void intel_mpllb_state_verify(struct intel_atomic_state *state,
struct drm_i915_private *i915 = to_i915(state->base.dev);
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_mpllb_state mpllb_hw_state = { 0 };
struct intel_mpllb_state mpllb_hw_state = {};
const struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state;
struct intel_encoder *encoder;
......
......@@ -290,7 +290,7 @@ static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
{
struct seq_file *m = file->private_data;
struct drm_i915_private *dev_priv = m->private;
u16 new[8] = { 0 };
u16 new[8] = {};
int level;
int ret;
char tmp[32];
......
......@@ -836,7 +836,6 @@ static const struct intel_device_info mtl_info = {
.has_pxp = 1,
.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
.require_force_probe = 1,
MTL_CACHELEVEL,
};
......@@ -923,7 +922,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_DG2_IDS(&dg2_info),
INTEL_ATS_M_IDS(&ats_m_info),
INTEL_MTL_IDS(&mtl_info),
{0, 0, 0}
{}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
......
......@@ -718,7 +718,11 @@
INTEL_VGA_DEVICE(0x56A5, info), \
INTEL_VGA_DEVICE(0x56A6, info), \
INTEL_VGA_DEVICE(0x56B0, info), \
INTEL_VGA_DEVICE(0x56B1, info)
INTEL_VGA_DEVICE(0x56B1, info), \
INTEL_VGA_DEVICE(0x56BA, info), \
INTEL_VGA_DEVICE(0x56BB, info), \
INTEL_VGA_DEVICE(0x56BC, info), \
INTEL_VGA_DEVICE(0x56BD, info)
#define INTEL_DG2_G12_IDS(info) \
INTEL_VGA_DEVICE(0x5696, info), \
......
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