Commit 3f408fa0 authored by Haojian Zhuang's avatar Haojian Zhuang Committed by Eric Miao

ARM: mmp: select CPU_PJ4

Since CPU_PJ4 is shared between PXA95x and MMP2, select CPU_PJ4 in MMP2
configuration.
Signed-off-by: default avatarHaojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: default avatarEric Miao <eric.y.miao@gmail.com>
parent c9b5ef47
...@@ -50,6 +50,7 @@ config MACH_BROWNSTONE ...@@ -50,6 +50,7 @@ config MACH_BROWNSTONE
config MACH_FLINT config MACH_FLINT
bool "Marvell's Flint Development Platform" bool "Marvell's Flint Development Platform"
depends on !CPU_MOHAWK
select CPU_MMP2 select CPU_MMP2
help help
Say 'Y' here if you want to support the Marvell MMP2-based Say 'Y' here if you want to support the Marvell MMP2-based
...@@ -60,6 +61,7 @@ config MACH_FLINT ...@@ -60,6 +61,7 @@ config MACH_FLINT
config MACH_MARVELL_JASPER config MACH_MARVELL_JASPER
bool "Marvell's Jasper Development Platform" bool "Marvell's Jasper Development Platform"
depends on !CPU_MOHAWK
select CPU_MMP2 select CPU_MMP2
help help
Say 'Y' here if you want to support the Marvell MMP2-base Say 'Y' here if you want to support the Marvell MMP2-base
...@@ -91,8 +93,7 @@ config CPU_PXA910 ...@@ -91,8 +93,7 @@ config CPU_PXA910
config CPU_MMP2 config CPU_MMP2
bool bool
select CPU_V6 select CPU_PJ4
select CPU_32v6K
help help
Select code specific to MMP2. MMP2 is ARMv6 compatible. Select code specific to MMP2. MMP2 is ARMv7 compatible.
endif endif
...@@ -795,7 +795,7 @@ config CACHE_PL310 ...@@ -795,7 +795,7 @@ config CACHE_PL310
config CACHE_TAUROS2 config CACHE_TAUROS2
bool "Enable the Tauros2 L2 cache controller" bool "Enable the Tauros2 L2 cache controller"
depends on (ARCH_DOVE || ARCH_MMP) depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
default y default y
select OUTER_CACHE select OUTER_CACHE
help help
......
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