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Commit 446fe5e2 authored by Mark Brown's avatar Mark Brown
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Merge remote-tracking branches 'spi/topic/adi', 'spi/topic/atmel' and... 

Merge remote-tracking branches 'spi/topic/adi', 'spi/topic/atmel' and 'spi/topic/cadence' into spi-next
parents f54645d1 c34cc248 b112f058 25dbe04a
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Documentation/devicetree/bindings/spi/spi-cadence.txt 0 → 100644
View file @ 446fe5e2
Cadence SPI controller Device Tree Bindings
-------------------------------------------
Required properties:
- compatible : Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6".
- reg : Physical base address and size of SPI registers map.
- interrupts : Property with a value describing the interrupt
number.
- interrupt-parent : Must be core interrupt controller
- clock-names : List of input clock names - "ref_clk", "pclk"
(See clock bindings for details).
- clocks : Clock phandles (see clock bindings for details).
Optional properties:
- num-cs : Number of chip selects used.
If a decoder is used, this will be the number of
chip selects after the decoder.
- is-decoded-cs : Flag to indicate whether decoder is used or not.
Example:
spi@e0007000 {
compatible = "xlnx,zynq-spi-r1p6";
clock-names = "ref_clk", "pclk";
clocks = <&clkc 26>, <&clkc 35>;
interrupt-parent = <&intc>;
interrupts = <0 49 4>;
num-cs = <4>;
is-decoded-cs = <0>;
reg = <0xe0007000 0x1000>;
} ;
arch/blackfin/mach-bf609/boards/ezkit.c
View file @ 446fe5e2
...@@ -20,7 +20,7 @@ ...@@ -20,7 +20,7 @@
#include <linux/pinctrl/machine.h> #include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_data/pinctrl-adi2.h> #include <linux/platform_data/pinctrl-adi2.h>
#include <asm/bfin_spi3.h> #include <linux/spi/adi_spi3.h>
#include <asm/dma.h> #include <asm/dma.h>
#include <asm/gpio.h> #include <asm/gpio.h>
#include <asm/nand.h> #include <asm/nand.h>
...@@ -767,13 +767,13 @@ static struct flash_platform_data bfin_spi_flash_data = { ...@@ -767,13 +767,13 @@ static struct flash_platform_data bfin_spi_flash_data = {
.type = "w25q32", .type = "w25q32",
}; };
static struct bfin_spi3_chip spi_flash_chip_info = { static struct adi_spi3_chip spi_flash_chip_info = {
.enable_dma = true, /* use dma transfer with this chip*/ .enable_dma = true, /* use dma transfer with this chip*/
}; };
#endif #endif
#if IS_ENABLED(CONFIG_SPI_SPIDEV) #if IS_ENABLED(CONFIG_SPI_SPIDEV)
static struct bfin_spi3_chip spidev_chip_info = { static struct adi_spi3_chip spidev_chip_info = {
.enable_dma = true, .enable_dma = true,
}; };
#endif #endif
...@@ -1736,7 +1736,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { ...@@ -1736,7 +1736,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
}, },
#endif #endif
}; };
#if IS_ENABLED(CONFIG_SPI_BFIN_V3) #if IS_ENABLED(CONFIG_SPI_ADI_V3)
/* SPI (0) */ /* SPI (0) */
static struct resource bfin_spi0_resource[] = { static struct resource bfin_spi0_resource[] = {
{ {
...@@ -1777,13 +1777,13 @@ static struct resource bfin_spi1_resource[] = { ...@@ -1777,13 +1777,13 @@ static struct resource bfin_spi1_resource[] = {
}; };
/* SPI controller data */ /* SPI controller data */
static struct bfin_spi3_master bf60x_spi_master_info0 = { static struct adi_spi3_master bf60x_spi_master_info0 = {
.num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
}; };
static struct platform_device bf60x_spi_master0 = { static struct platform_device bf60x_spi_master0 = {
.name = "bfin-spi3", .name = "adi-spi3",
.id = 0, /* Bus number */ .id = 0, /* Bus number */
.num_resources = ARRAY_SIZE(bfin_spi0_resource), .num_resources = ARRAY_SIZE(bfin_spi0_resource),
.resource = bfin_spi0_resource, .resource = bfin_spi0_resource,
...@@ -1792,13 +1792,13 @@ static struct platform_device bf60x_spi_master0 = { ...@@ -1792,13 +1792,13 @@ static struct platform_device bf60x_spi_master0 = {
}, },
}; };
static struct bfin_spi3_master bf60x_spi_master_info1 = { static struct adi_spi3_master bf60x_spi_master_info1 = {
.num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
.pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
}; };
static struct platform_device bf60x_spi_master1 = { static struct platform_device bf60x_spi_master1 = {
.name = "bfin-spi3", .name = "adi-spi3",
.id = 1, /* Bus number */ .id = 1, /* Bus number */
.num_resources = ARRAY_SIZE(bfin_spi1_resource), .num_resources = ARRAY_SIZE(bfin_spi1_resource),
.resource = bfin_spi1_resource, .resource = bfin_spi1_resource,
...@@ -1990,7 +1990,7 @@ static struct platform_device *ezkit_devices[] __initdata = { ...@@ -1990,7 +1990,7 @@ static struct platform_device *ezkit_devices[] __initdata = {
&bfin_sdh_device, &bfin_sdh_device,
#endif #endif
#if IS_ENABLED(CONFIG_SPI_BFIN_V3) #if IS_ENABLED(CONFIG_SPI_ADI_V3)
&bf60x_spi_master0, &bf60x_spi_master0,
&bf60x_spi_master1, &bf60x_spi_master1,
#endif #endif
...@@ -2051,8 +2051,8 @@ static struct pinctrl_map __initdata bfin_pinmux_map[] = { ...@@ -2051,8 +2051,8 @@ static struct pinctrl_map __initdata bfin_pinmux_map[] = {
PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"), PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"), PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0", "pinctrl-adi2.0", NULL, "eth0"), PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0", "pinctrl-adi2.0", NULL, "eth0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.0", "pinctrl-adi2.0", NULL, "spi0"), PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.0", "pinctrl-adi2.0", NULL, "spi0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.1", "pinctrl-adi2.0", NULL, "spi1"), PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.1", "pinctrl-adi2.0", NULL, "spi1"),
PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"), PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"), PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"), PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
......
arch/blackfin/mach-bf609/clock.c
View file @ 446fe5e2
...@@ -363,6 +363,12 @@ static struct clk ethclk = { ...@@ -363,6 +363,12 @@ static struct clk ethclk = {
.ops = &dummy_clk_ops, .ops = &dummy_clk_ops,
}; };
static struct clk spiclk = {
.name = "spi",
.parent = &sclk1,
.ops = &dummy_clk_ops,
};
static struct clk_lookup bf609_clks[] = { static struct clk_lookup bf609_clks[] = {
CLK(sys_clkin, NULL, "SYS_CLKIN"), CLK(sys_clkin, NULL, "SYS_CLKIN"),
CLK(pll_clk, NULL, "PLLCLK"), CLK(pll_clk, NULL, "PLLCLK"),
...@@ -375,6 +381,7 @@ static struct clk_lookup bf609_clks[] = { ...@@ -375,6 +381,7 @@ static struct clk_lookup bf609_clks[] = {
CLK(dclk, NULL, "DCLK"), CLK(dclk, NULL, "DCLK"),
CLK(oclk, NULL, "OCLK"), CLK(oclk, NULL, "OCLK"),
CLK(ethclk, NULL, "stmmaceth"), CLK(ethclk, NULL, "stmmaceth"),
CLK(spiclk, NULL, "spi"),
}; };
int __init clk_init(void) int __init clk_init(void)
......
drivers/spi/Kconfig
View file @ 446fe5e2
...@@ -91,8 +91,8 @@ config SPI_BFIN5XX ...@@ -91,8 +91,8 @@ config SPI_BFIN5XX
help help
This is the SPI controller master driver for Blackfin 5xx processor. This is the SPI controller master driver for Blackfin 5xx processor.
config SPI_BFIN_V3 config SPI_ADI_V3
tristate "SPI controller v3 for Blackfin" tristate "SPI controller v3 for ADI"
depends on BF60x depends on BF60x
help help
This is the SPI controller v3 master driver This is the SPI controller v3 master driver
...@@ -148,6 +148,13 @@ config SPI_BUTTERFLY ...@@ -148,6 +148,13 @@ config SPI_BUTTERFLY
inexpensive battery powered microcontroller evaluation board. inexpensive battery powered microcontroller evaluation board.
This same cable can be used to flash new firmware. This same cable can be used to flash new firmware.
config SPI_CADENCE
tristate "Cadence SPI controller"
depends on ARM
help
This selects the Cadence SPI controller master driver
used by Xilinx Zynq.
config SPI_CLPS711X config SPI_CLPS711X
tristate "CLPS711X host SPI controller" tristate "CLPS711X host SPI controller"
depends on ARCH_CLPS711X || COMPILE_TEST depends on ARCH_CLPS711X || COMPILE_TEST
......
drivers/spi/Makefile
View file @ 446fe5e2
...@@ -18,10 +18,11 @@ obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o ...@@ -18,10 +18,11 @@ obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o
obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o
obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o
obj-$(CONFIG_SPI_BFIN_V3) += spi-bfin-v3.o obj-$(CONFIG_SPI_ADI_V3) += spi-adi-v3.o
obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o
obj-$(CONFIG_SPI_CADENCE) += spi-cadence.o
obj-$(CONFIG_SPI_CLPS711X) += spi-clps711x.o obj-$(CONFIG_SPI_CLPS711X) += spi-clps711x.o
obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o
obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o
......
drivers/spi/spi-bfin-v3.c → drivers/spi/spi-adi-v3.c
View file @ 446fe5e2
/* /*
* Analog Devices SPI3 controller driver * Analog Devices SPI3 controller driver
* *
* Copyright (c) 2013 Analog Devices Inc. * Copyright (c) 2014 Analog Devices Inc.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
...@@ -13,6 +13,7 @@ ...@@ -13,6 +13,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <linux/clk.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/device.h> #include <linux/device.h>
#include <linux/dma-mapping.h> #include <linux/dma-mapping.h>
...@@ -26,35 +27,34 @@ ...@@ -26,35 +27,34 @@
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/spi/spi.h> #include <linux/spi/spi.h>
#include <linux/spi/adi_spi3.h>
#include <linux/types.h> #include <linux/types.h>
#include <asm/bfin_spi3.h>
#include <asm/cacheflush.h>
#include <asm/dma.h> #include <asm/dma.h>
#include <asm/portmux.h> #include <asm/portmux.h>
enum bfin_spi_state { enum adi_spi_state {
START_STATE, START_STATE,
RUNNING_STATE, RUNNING_STATE,
DONE_STATE, DONE_STATE,
ERROR_STATE ERROR_STATE
}; };
struct bfin_spi_master; struct adi_spi_master;
struct bfin_spi_transfer_ops { struct adi_spi_transfer_ops {
void (*write) (struct bfin_spi_master *); void (*write) (struct adi_spi_master *);
void (*read) (struct bfin_spi_master *); void (*read) (struct adi_spi_master *);
void (*duplex) (struct bfin_spi_master *); void (*duplex) (struct adi_spi_master *);
}; };
/* runtime info for spi master */ /* runtime info for spi master */
struct bfin_spi_master { struct adi_spi_master {
/* SPI framework hookup */ /* SPI framework hookup */
struct spi_master *master; struct spi_master *master;
/* Regs base of SPI controller */ /* Regs base of SPI controller */
struct bfin_spi_regs __iomem *regs; struct adi_spi_regs __iomem *regs;
/* Pin request list */ /* Pin request list */
u16 *pin_req; u16 *pin_req;
...@@ -65,7 +65,7 @@ struct bfin_spi_master { ...@@ -65,7 +65,7 @@ struct bfin_spi_master {
/* Current message transfer state info */ /* Current message transfer state info */
struct spi_message *cur_msg; struct spi_message *cur_msg;
struct spi_transfer *cur_transfer; struct spi_transfer *cur_transfer;
struct bfin_spi_device *cur_chip; struct adi_spi_device *cur_chip;
unsigned transfer_len; unsigned transfer_len;
/* transfer buffer */ /* transfer buffer */
...@@ -90,12 +90,12 @@ struct bfin_spi_master { ...@@ -90,12 +90,12 @@ struct bfin_spi_master {
u32 ssel; u32 ssel;
unsigned long sclk; unsigned long sclk;
enum bfin_spi_state state; enum adi_spi_state state;
const struct bfin_spi_transfer_ops *ops; const struct adi_spi_transfer_ops *ops;
}; };
struct bfin_spi_device { struct adi_spi_device {
u32 control; u32 control;
u32 clock; u32 clock;
u32 ssel; u32 ssel;
...@@ -105,17 +105,25 @@ struct bfin_spi_device { ...@@ -105,17 +105,25 @@ struct bfin_spi_device {
u32 cs_gpio; u32 cs_gpio;
u32 tx_dummy_val; /* tx value for rx only transfer */ u32 tx_dummy_val; /* tx value for rx only transfer */
bool enable_dma; bool enable_dma;
const struct bfin_spi_transfer_ops *ops; const struct adi_spi_transfer_ops *ops;
}; };
static void bfin_spi_enable(struct bfin_spi_master *drv_data) static void adi_spi_enable(struct adi_spi_master *drv_data)
{ {
bfin_write_or(&drv_data->regs->control, SPI_CTL_EN); u32 ctl;
ctl = ioread32(&drv_data->regs->control);
ctl |= SPI_CTL_EN;
iowrite32(ctl, &drv_data->regs->control);
} }
static void bfin_spi_disable(struct bfin_spi_master *drv_data) static void adi_spi_disable(struct adi_spi_master *drv_data)
{ {
bfin_write_and(&drv_data->regs->control, ~SPI_CTL_EN); u32 ctl;
ctl = ioread32(&drv_data->regs->control);
ctl &= ~SPI_CTL_EN;
iowrite32(ctl, &drv_data->regs->control);
} }
/* Caculate the SPI_CLOCK register value based on input HZ */ /* Caculate the SPI_CLOCK register value based on input HZ */
...@@ -128,35 +136,43 @@ static u32 hz_to_spi_clock(u32 sclk, u32 speed_hz) ...@@ -128,35 +136,43 @@ static u32 hz_to_spi_clock(u32 sclk, u32 speed_hz)
return spi_clock; return spi_clock;
} }
static int bfin_spi_flush(struct bfin_spi_master *drv_data) static int adi_spi_flush(struct adi_spi_master *drv_data)
{ {
unsigned long limit = loops_per_jiffy << 1; unsigned long limit = loops_per_jiffy << 1;
/* wait for stop and clear stat */ /* wait for stop and clear stat */
while (!(bfin_read(&drv_data->regs->status) & SPI_STAT_SPIF) && --limit) while (!(ioread32(&drv_data->regs->status) & SPI_STAT_SPIF) && --limit)
cpu_relax(); cpu_relax();
bfin_write(&drv_data->regs->status, 0xFFFFFFFF); iowrite32(0xFFFFFFFF, &drv_data->regs->status);
return limit; return limit;
} }
/* Chip select operation functions for cs_change flag */ /* Chip select operation functions for cs_change flag */
static void bfin_spi_cs_active(struct bfin_spi_master *drv_data, struct bfin_spi_device *chip) static void adi_spi_cs_active(struct adi_spi_master *drv_data, struct adi_spi_device *chip)
{ {
if (likely(chip->cs < MAX_CTRL_CS)) if (likely(chip->cs < MAX_CTRL_CS)) {
bfin_write_and(&drv_data->regs->ssel, ~chip->ssel); u32 reg;
else reg = ioread32(&drv_data->regs->ssel);
reg &= ~chip->ssel;
iowrite32(reg, &drv_data->regs->ssel);
} else {
gpio_set_value(chip->cs_gpio, 0); gpio_set_value(chip->cs_gpio, 0);
}
} }
static void bfin_spi_cs_deactive(struct bfin_spi_master *drv_data, static void adi_spi_cs_deactive(struct adi_spi_master *drv_data,
struct bfin_spi_device *chip) struct adi_spi_device *chip)
{ {
if (likely(chip->cs < MAX_CTRL_CS)) if (likely(chip->cs < MAX_CTRL_CS)) {
bfin_write_or(&drv_data->regs->ssel, chip->ssel); u32 reg;
else reg = ioread32(&drv_data->regs->ssel);
reg |= chip->ssel;
iowrite32(reg, &drv_data->regs->ssel);
} else {
gpio_set_value(chip->cs_gpio, 1); gpio_set_value(chip->cs_gpio, 1);
}
/* Move delay here for consistency */ /* Move delay here for consistency */
if (chip->cs_chg_udelay) if (chip->cs_chg_udelay)
...@@ -164,187 +180,192 @@ static void bfin_spi_cs_deactive(struct bfin_spi_master *drv_data, ...@@ -164,187 +180,192 @@ static void bfin_spi_cs_deactive(struct bfin_spi_master *drv_data,
} }
/* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */ /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
static inline void bfin_spi_cs_enable(struct bfin_spi_master *drv_data, static inline void adi_spi_cs_enable(struct adi_spi_master *drv_data,
struct bfin_spi_device *chip) struct adi_spi_device *chip)
{ {
if (chip->cs < MAX_CTRL_CS) if (chip->cs < MAX_CTRL_CS) {
bfin_write_or(&drv_data->regs->ssel, chip->ssel >> 8); u32 reg;
reg = ioread32(&drv_data->regs->ssel);
reg |= chip->ssel >> 8;
iowrite32(reg, &drv_data->regs->ssel);
}
} }
static inline void bfin_spi_cs_disable(struct bfin_spi_master *drv_data, static inline void adi_spi_cs_disable(struct adi_spi_master *drv_data,
struct bfin_spi_device *chip) struct adi_spi_device *chip)
{ {
if (chip->cs < MAX_CTRL_CS) if (chip->cs < MAX_CTRL_CS) {
bfin_write_and(&drv_data->regs->ssel, ~(chip->ssel >> 8)); u32 reg;
reg = ioread32(&drv_data->regs->ssel);
reg &= ~(chip->ssel >> 8);
iowrite32(reg, &drv_data->regs->ssel);
}
} }
/* stop controller and re-config current chip*/ /* stop controller and re-config current chip*/
static void bfin_spi_restore_state(struct bfin_spi_master *drv_data) static void adi_spi_restore_state(struct adi_spi_master *drv_data)
{ {
struct bfin_spi_device *chip = drv_data->cur_chip; struct adi_spi_device *chip = drv_data->cur_chip;
/* Clear status and disable clock */ /* Clear status and disable clock */
bfin_write(&drv_data->regs->status, 0xFFFFFFFF); iowrite32(0xFFFFFFFF, &drv_data->regs->status);
bfin_write(&drv_data->regs->rx_control, 0x0); iowrite32(0x0, &drv_data->regs->rx_control);
bfin_write(&drv_data->regs->tx_control, 0x0); iowrite32(0x0, &drv_data->regs->tx_control);
bfin_spi_disable(drv_data); adi_spi_disable(drv_data);
SSYNC();
/* Load the registers */ /* Load the registers */
bfin_write(&drv_data->regs->control, chip->control); iowrite32(chip->control, &drv_data->regs->control);
bfin_write(&drv_data->regs->clock, chip->clock); iowrite32(chip->clock, &drv_data->regs->clock);
bfin_spi_enable(drv_data); adi_spi_enable(drv_data);
drv_data->tx_num = drv_data->rx_num = 0; drv_data->tx_num = drv_data->rx_num = 0;
/* we always choose tx transfer initiate */ /* we always choose tx transfer initiate */
bfin_write(&drv_data->regs->rx_control, SPI_RXCTL_REN); iowrite32(SPI_RXCTL_REN, &drv_data->regs->rx_control);
bfin_write(&drv_data->regs->tx_control, iowrite32(SPI_TXCTL_TEN | SPI_TXCTL_TTI, &drv_data->regs->tx_control);
SPI_TXCTL_TEN | SPI_TXCTL_TTI); adi_spi_cs_active(drv_data, chip);
bfin_spi_cs_active(drv_data, chip);
} }
/* discard invalid rx data and empty rfifo */ /* discard invalid rx data and empty rfifo */
static inline void dummy_read(struct bfin_spi_master *drv_data) static inline void dummy_read(struct adi_spi_master *drv_data)
{ {
while (!(bfin_read(&drv_data->regs->status) & SPI_STAT_RFE)) while (!(ioread32(&drv_data->regs->status) & SPI_STAT_RFE))
bfin_read(&drv_data->regs->rfifo); ioread32(&drv_data->regs->rfifo);
} }
static void bfin_spi_u8_write(struct bfin_spi_master *drv_data) static void adi_spi_u8_write(struct adi_spi_master *drv_data)
{ {
dummy_read(drv_data); dummy_read(drv_data);
while (drv_data->tx < drv_data->tx_end) { while (drv_data->tx < drv_data->tx_end) {
bfin_write(&drv_data->regs->tfifo, (*(u8 *)(drv_data->tx++))); iowrite32(*(u8 *)(drv_data->tx++), &drv_data->regs->tfifo);
while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE) while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
cpu_relax(); cpu_relax();
bfin_read(&drv_data->regs->rfifo); ioread32(&drv_data->regs->rfifo);
} }
} }
static void bfin_spi_u8_read(struct bfin_spi_master *drv_data) static void adi_spi_u8_read(struct adi_spi_master *drv_data)
{ {
u32 tx_val = drv_data->cur_chip->tx_dummy_val; u32 tx_val = drv_data->cur_chip->tx_dummy_val;
dummy_read(drv_data); dummy_read(drv_data);
while (drv_data->rx < drv_data->rx_end) { while (drv_data->rx < drv_data->rx_end) {
bfin_write(&drv_data->regs->tfifo, tx_val); iowrite32(tx_val, &drv_data->regs->tfifo);
while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE) while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
cpu_relax(); cpu_relax();
*(u8 *)(drv_data->rx++) = bfin_read(&drv_data->regs->rfifo); *(u8 *)(drv_data->rx++) = ioread32(&drv_data->regs->rfifo);
} }
} }
static void bfin_spi_u8_duplex(struct bfin_spi_master *drv_data) static void adi_spi_u8_duplex(struct adi_spi_master *drv_data)
{ {
dummy_read(drv_data); dummy_read(drv_data);
while (drv_data->rx < drv_data->rx_end) { while (drv_data->rx < drv_data->rx_end) {
bfin_write(&drv_data->regs->tfifo, (*(u8 *)(drv_data->tx++))); iowrite32(*(u8 *)(drv_data->tx++), &drv_data->regs->tfifo);
while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE) while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
cpu_relax(); cpu_relax();
*(u8 *)(drv_data->rx++) = bfin_read(&drv_data->regs->rfifo); *(u8 *)(drv_data->rx++) = ioread32(&drv_data->regs->rfifo);
} }
} }
static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u8 = { static const struct adi_spi_transfer_ops adi_spi_transfer_ops_u8 = {
.write = bfin_spi_u8_write, .write = adi_spi_u8_write,
.read = bfin_spi_u8_read, .read = adi_spi_u8_read,
.duplex = bfin_spi_u8_duplex, .duplex = adi_spi_u8_duplex,
}; };
static void bfin_spi_u16_write(struct bfin_spi_master *drv_data) static void adi_spi_u16_write(struct adi_spi_master *drv_data)
{ {
dummy_read(drv_data); dummy_read(drv_data);
while (drv_data->tx < drv_data->tx_end) { while (drv_data->tx < drv_data->tx_end) {
bfin_write(&drv_data->regs->tfifo, (*(u16 *)drv_data->tx)); iowrite32(*(u16 *)drv_data->tx, &drv_data->regs->tfifo);
drv_data->tx += 2; drv_data->tx += 2;
while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE) while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
cpu_relax(); cpu_relax();
bfin_read(&drv_data->regs->rfifo); ioread32(&drv_data->regs->rfifo);
} }
} }
static void bfin_spi_u16_read(struct bfin_spi_master *drv_data) static void adi_spi_u16_read(struct adi_spi_master *drv_data)
{ {
u32 tx_val = drv_data->cur_chip->tx_dummy_val; u32 tx_val = drv_data->cur_chip->tx_dummy_val;
dummy_read(drv_data); dummy_read(drv_data);
while (drv_data->rx < drv_data->rx_end) { while (drv_data->rx < drv_data->rx_end) {
bfin_write(&drv_data->regs->tfifo, tx_val); iowrite32(tx_val, &drv_data->regs->tfifo);
while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE) while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
cpu_relax(); cpu_relax();
*(u16 *)drv_data->rx = bfin_read(&drv_data->regs->rfifo); *(u16 *)drv_data->rx = ioread32(&drv_data->regs->rfifo);
drv_data->rx += 2; drv_data->rx += 2;
} }
} }
static void bfin_spi_u16_duplex(struct bfin_spi_master *drv_data) static void adi_spi_u16_duplex(struct adi_spi_master *drv_data)
{ {
dummy_read(drv_data); dummy_read(drv_data);
while (drv_data->rx < drv_data->rx_end) { while (drv_data->rx < drv_data->rx_end) {
bfin_write(&drv_data->regs->tfifo, (*(u16 *)drv_data->tx)); iowrite32(*(u16 *)drv_data->tx, &drv_data->regs->tfifo);
drv_data->tx += 2; drv_data->tx += 2;
while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE) while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
cpu_relax(); cpu_relax();
*(u16 *)drv_data->rx = bfin_read(&drv_data->regs->rfifo); *(u16 *)drv_data->rx = ioread32(&drv_data->regs->rfifo);
drv_data->rx += 2; drv_data->rx += 2;
} }
} }
static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u16 = { static const struct adi_spi_transfer_ops adi_spi_transfer_ops_u16 = {
.write = bfin_spi_u16_write, .write = adi_spi_u16_write,
.read = bfin_spi_u16_read, .read = adi_spi_u16_read,
.duplex = bfin_spi_u16_duplex, .duplex = adi_spi_u16_duplex,
}; };
static void bfin_spi_u32_write(struct bfin_spi_master *drv_data) static void adi_spi_u32_write(struct adi_spi_master *drv_data)
{ {
dummy_read(drv_data); dummy_read(drv_data);
while (drv_data->tx < drv_data->tx_end) { while (drv_data->tx < drv_data->tx_end) {
bfin_write(&drv_data->regs->tfifo, (*(u32 *)drv_data->tx)); iowrite32(*(u32 *)drv_data->tx, &drv_data->regs->tfifo);
drv_data->tx += 4; drv_data->tx += 4;
while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE) while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
cpu_relax(); cpu_relax();
bfin_read(&drv_data->regs->rfifo); ioread32(&drv_data->regs->rfifo);
} }
} }
static void bfin_spi_u32_read(struct bfin_spi_master *drv_data) static void adi_spi_u32_read(struct adi_spi_master *drv_data)
{ {
u32 tx_val = drv_data->cur_chip->tx_dummy_val; u32 tx_val = drv_data->cur_chip->tx_dummy_val;
dummy_read(drv_data); dummy_read(drv_data);
while (drv_data->rx < drv_data->rx_end) { while (drv_data->rx < drv_data->rx_end) {
bfin_write(&drv_data->regs->tfifo, tx_val); iowrite32(tx_val, &drv_data->regs->tfifo);
while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE) while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
cpu_relax(); cpu_relax();
*(u32 *)drv_data->rx = bfin_read(&drv_data->regs->rfifo); *(u32 *)drv_data->rx = ioread32(&drv_data->regs->rfifo);
drv_data->rx += 4; drv_data->rx += 4;
} }
} }
static void bfin_spi_u32_duplex(struct bfin_spi_master *drv_data) static void adi_spi_u32_duplex(struct adi_spi_master *drv_data)
{ {
dummy_read(drv_data); dummy_read(drv_data);
while (drv_data->rx < drv_data->rx_end) { while (drv_data->rx < drv_data->rx_end) {
bfin_write(&drv_data->regs->tfifo, (*(u32 *)drv_data->tx)); iowrite32(*(u32 *)drv_data->tx, &drv_data->regs->tfifo);
drv_data->tx += 4; drv_data->tx += 4;
while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE) while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
cpu_relax(); cpu_relax();
*(u32 *)drv_data->rx = bfin_read(&drv_data->regs->rfifo); *(u32 *)drv_data->rx = ioread32(&drv_data->regs->rfifo);
drv_data->rx += 4; drv_data->rx += 4;
} }
} }
static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u32 = { static const struct adi_spi_transfer_ops adi_spi_transfer_ops_u32 = {
.write = bfin_spi_u32_write, .write = adi_spi_u32_write,
.read = bfin_spi_u32_read, .read = adi_spi_u32_read,
.duplex = bfin_spi_u32_duplex, .duplex = adi_spi_u32_duplex,
}; };
/* test if there is more transfer to be done */ /* test if there is more transfer to be done */
static void bfin_spi_next_transfer(struct bfin_spi_master *drv) static void adi_spi_next_transfer(struct adi_spi_master *drv)
{ {
struct spi_message *msg = drv->cur_msg; struct spi_message *msg = drv->cur_msg;
struct spi_transfer *t = drv->cur_transfer; struct spi_transfer *t = drv->cur_transfer;
...@@ -360,15 +381,15 @@ static void bfin_spi_next_transfer(struct bfin_spi_master *drv) ...@@ -360,15 +381,15 @@ static void bfin_spi_next_transfer(struct bfin_spi_master *drv)
} }
} }
static void bfin_spi_giveback(struct bfin_spi_master *drv_data) static void adi_spi_giveback(struct adi_spi_master *drv_data)
{ {
struct bfin_spi_device *chip = drv_data->cur_chip; struct adi_spi_device *chip = drv_data->cur_chip;
bfin_spi_cs_deactive(drv_data, chip); adi_spi_cs_deactive(drv_data, chip);
spi_finalize_current_message(drv_data->master); spi_finalize_current_message(drv_data->master);
} }
static int bfin_spi_setup_transfer(struct bfin_spi_master *drv) static int adi_spi_setup_transfer(struct adi_spi_master *drv)
{ {
struct spi_transfer *t = drv->cur_transfer; struct spi_transfer *t = drv->cur_transfer;
u32 cr, cr_width; u32 cr, cr_width;
...@@ -393,34 +414,33 @@ static int bfin_spi_setup_transfer(struct bfin_spi_master *drv) ...@@ -393,34 +414,33 @@ static int bfin_spi_setup_transfer(struct bfin_spi_master *drv)
switch (t->bits_per_word) { switch (t->bits_per_word) {
case 8: case 8:
cr_width = SPI_CTL_SIZE08; cr_width = SPI_CTL_SIZE08;
drv->ops = &bfin_bfin_spi_transfer_ops_u8; drv->ops = &adi_spi_transfer_ops_u8;
break; break;
case 16: case 16:
cr_width = SPI_CTL_SIZE16; cr_width = SPI_CTL_SIZE16;
drv->ops = &bfin_bfin_spi_transfer_ops_u16; drv->ops = &adi_spi_transfer_ops_u16;
break; break;
case 32: case 32:
cr_width = SPI_CTL_SIZE32; cr_width = SPI_CTL_SIZE32;
drv->ops = &bfin_bfin_spi_transfer_ops_u32; drv->ops = &adi_spi_transfer_ops_u32;
break; break;
default: default:
return -EINVAL; return -EINVAL;
} }
cr = bfin_read(&drv->regs->control) & ~SPI_CTL_SIZE; cr = ioread32(&drv->regs->control) & ~SPI_CTL_SIZE;
cr |= cr_width; cr |= cr_width;
bfin_write(&drv->regs->control, cr); iowrite32(cr, &drv->regs->control);
/* speed setup */ /* speed setup */
bfin_write(&drv->regs->clock, iowrite32(hz_to_spi_clock(drv->sclk, t->speed_hz), &drv->regs->clock);
hz_to_spi_clock(drv->sclk, t->speed_hz));
return 0; return 0;
} }
static int bfin_spi_dma_xfer(struct bfin_spi_master *drv_data) static int adi_spi_dma_xfer(struct adi_spi_master *drv_data)
{ {
struct spi_transfer *t = drv_data->cur_transfer; struct spi_transfer *t = drv_data->cur_transfer;
struct spi_message *msg = drv_data->cur_msg; struct spi_message *msg = drv_data->cur_msg;
struct bfin_spi_device *chip = drv_data->cur_chip; struct adi_spi_device *chip = drv_data->cur_chip;
u32 dma_config; u32 dma_config;
unsigned long word_count, word_size; unsigned long word_count, word_size;
void *tx_buf, *rx_buf; void *tx_buf, *rx_buf;
...@@ -498,17 +518,16 @@ static int bfin_spi_dma_xfer(struct bfin_spi_master *drv_data) ...@@ -498,17 +518,16 @@ static int bfin_spi_dma_xfer(struct bfin_spi_master *drv_data)
set_dma_config(drv_data->rx_dma, dma_config | WNR); set_dma_config(drv_data->rx_dma, dma_config | WNR);
enable_dma(drv_data->tx_dma); enable_dma(drv_data->tx_dma);
enable_dma(drv_data->rx_dma); enable_dma(drv_data->rx_dma);
SSYNC();
bfin_write(&drv_data->regs->rx_control, SPI_RXCTL_REN | SPI_RXCTL_RDR_NE); iowrite32(SPI_RXCTL_REN | SPI_RXCTL_RDR_NE,
SSYNC(); &drv_data->regs->rx_control);
bfin_write(&drv_data->regs->tx_control, iowrite32(SPI_TXCTL_TEN | SPI_TXCTL_TTI | SPI_TXCTL_TDR_NF,
SPI_TXCTL_TEN | SPI_TXCTL_TTI | SPI_TXCTL_TDR_NF); &drv_data->regs->tx_control);
return 0; return 0;
} }
static int bfin_spi_pio_xfer(struct bfin_spi_master *drv_data) static int adi_spi_pio_xfer(struct adi_spi_master *drv_data)
{ {
struct spi_message *msg = drv_data->cur_msg; struct spi_message *msg = drv_data->cur_msg;
...@@ -529,19 +548,19 @@ static int bfin_spi_pio_xfer(struct bfin_spi_master *drv_data) ...@@ -529,19 +548,19 @@ static int bfin_spi_pio_xfer(struct bfin_spi_master *drv_data)
return -EIO; return -EIO;
} }
if (!bfin_spi_flush(drv_data)) if (!adi_spi_flush(drv_data))
return -EIO; return -EIO;
msg->actual_length += drv_data->transfer_len; msg->actual_length += drv_data->transfer_len;
tasklet_schedule(&drv_data->pump_transfers); tasklet_schedule(&drv_data->pump_transfers);
return 0; return 0;
} }
static void bfin_spi_pump_transfers(unsigned long data) static void adi_spi_pump_transfers(unsigned long data)
{ {
struct bfin_spi_master *drv_data = (struct bfin_spi_master *)data; struct adi_spi_master *drv_data = (struct adi_spi_master *)data;
struct spi_message *msg = NULL; struct spi_message *msg = NULL;
struct spi_transfer *t = NULL; struct spi_transfer *t = NULL;
struct bfin_spi_device *chip = NULL; struct adi_spi_device *chip = NULL;
int ret; int ret;
/* Get current state information */ /* Get current state information */
...@@ -552,7 +571,7 @@ static void bfin_spi_pump_transfers(unsigned long data) ...@@ -552,7 +571,7 @@ static void bfin_spi_pump_transfers(unsigned long data)
/* Handle for abort */ /* Handle for abort */
if (drv_data->state == ERROR_STATE) { if (drv_data->state == ERROR_STATE) {
msg->status = -EIO; msg->status = -EIO;
bfin_spi_giveback(drv_data); adi_spi_giveback(drv_data);
return; return;
} }
...@@ -560,14 +579,14 @@ static void bfin_spi_pump_transfers(unsigned long data) ...@@ -560,14 +579,14 @@ static void bfin_spi_pump_transfers(unsigned long data)
if (t->delay_usecs) if (t->delay_usecs)
udelay(t->delay_usecs); udelay(t->delay_usecs);
if (t->cs_change) if (t->cs_change)
bfin_spi_cs_deactive(drv_data, chip); adi_spi_cs_deactive(drv_data, chip);
bfin_spi_next_transfer(drv_data); adi_spi_next_transfer(drv_data);
t = drv_data->cur_transfer; t = drv_data->cur_transfer;
} }
/* Handle end of message */ /* Handle end of message */
if (drv_data->state == DONE_STATE) { if (drv_data->state == DONE_STATE) {
msg->status = 0; msg->status = 0;
bfin_spi_giveback(drv_data); adi_spi_giveback(drv_data);
return; return;
} }
...@@ -577,34 +596,34 @@ static void bfin_spi_pump_transfers(unsigned long data) ...@@ -577,34 +596,34 @@ static void bfin_spi_pump_transfers(unsigned long data)
return; return;
} }
ret = bfin_spi_setup_transfer(drv_data); ret = adi_spi_setup_transfer(drv_data);
if (ret) { if (ret) {
msg->status = ret; msg->status = ret;
bfin_spi_giveback(drv_data); adi_spi_giveback(drv_data);
} }
bfin_write(&drv_data->regs->status, 0xFFFFFFFF); iowrite32(0xFFFFFFFF, &drv_data->regs->status);
bfin_spi_cs_active(drv_data, chip); adi_spi_cs_active(drv_data, chip);
drv_data->state = RUNNING_STATE; drv_data->state = RUNNING_STATE;
if (chip->enable_dma) if (chip->enable_dma)
ret = bfin_spi_dma_xfer(drv_data); ret = adi_spi_dma_xfer(drv_data);
else else
ret = bfin_spi_pio_xfer(drv_data); ret = adi_spi_pio_xfer(drv_data);
if (ret) { if (ret) {
msg->status = ret; msg->status = ret;
bfin_spi_giveback(drv_data); adi_spi_giveback(drv_data);
} }
} }
static int bfin_spi_transfer_one_message(struct spi_master *master, static int adi_spi_transfer_one_message(struct spi_master *master,
struct spi_message *m) struct spi_message *m)
{ {
struct bfin_spi_master *drv_data = spi_master_get_devdata(master); struct adi_spi_master *drv_data = spi_master_get_devdata(master);
drv_data->cur_msg = m; drv_data->cur_msg = m;
drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
bfin_spi_restore_state(drv_data); adi_spi_restore_state(drv_data);
drv_data->state = START_STATE; drv_data->state = START_STATE;
drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
...@@ -630,15 +649,15 @@ static const u16 ssel[][MAX_SPI_SSEL] = { ...@@ -630,15 +649,15 @@ static const u16 ssel[][MAX_SPI_SSEL] = {
P_SPI2_SSEL6, P_SPI2_SSEL7}, P_SPI2_SSEL6, P_SPI2_SSEL7},
}; };
static int bfin_spi_setup(struct spi_device *spi) static int adi_spi_setup(struct spi_device *spi)
{ {
struct bfin_spi_master *drv_data = spi_master_get_devdata(spi->master); struct adi_spi_master *drv_data = spi_master_get_devdata(spi->master);
struct bfin_spi_device *chip = spi_get_ctldata(spi); struct adi_spi_device *chip = spi_get_ctldata(spi);
u32 bfin_ctl_reg = SPI_CTL_ODM | SPI_CTL_PSSE; u32 ctl_reg = SPI_CTL_ODM | SPI_CTL_PSSE;
int ret = -EINVAL; int ret = -EINVAL;
if (!chip) { if (!chip) {
struct bfin_spi3_chip *chip_info = spi->controller_data; struct adi_spi3_chip *chip_info = spi->controller_data;
chip = kzalloc(sizeof(*chip), GFP_KERNEL); chip = kzalloc(sizeof(*chip), GFP_KERNEL);
if (!chip) { if (!chip) {
...@@ -646,7 +665,7 @@ static int bfin_spi_setup(struct spi_device *spi) ...@@ -646,7 +665,7 @@ static int bfin_spi_setup(struct spi_device *spi)
return -ENOMEM; return -ENOMEM;
} }
if (chip_info) { if (chip_info) {
if (chip_info->control & ~bfin_ctl_reg) { if (chip_info->control & ~ctl_reg) {
dev_err(&spi->dev, dev_err(&spi->dev,
"do not set bits that the SPI framework manages\n"); "do not set bits that the SPI framework manages\n");
goto error; goto error;
...@@ -657,6 +676,7 @@ static int bfin_spi_setup(struct spi_device *spi) ...@@ -657,6 +676,7 @@ static int bfin_spi_setup(struct spi_device *spi)
chip->enable_dma = chip_info->enable_dma; chip->enable_dma = chip_info->enable_dma;
} }
chip->cs = spi->chip_select; chip->cs = spi->chip_select;
if (chip->cs < MAX_CTRL_CS) { if (chip->cs < MAX_CTRL_CS) {
chip->ssel = (1 << chip->cs) << 8; chip->ssel = (1 << chip->cs) << 8;
ret = peripheral_request(ssel[spi->master->bus_num] ret = peripheral_request(ssel[spi->master->bus_num]
...@@ -678,7 +698,7 @@ static int bfin_spi_setup(struct spi_device *spi) ...@@ -678,7 +698,7 @@ static int bfin_spi_setup(struct spi_device *spi)
} }
/* force a default base state */ /* force a default base state */
chip->control &= bfin_ctl_reg; chip->control &= ctl_reg;
if (spi->mode & SPI_CPOL) if (spi->mode & SPI_CPOL)
chip->control |= SPI_CTL_CPOL; chip->control |= SPI_CTL_CPOL;
...@@ -692,8 +712,8 @@ static int bfin_spi_setup(struct spi_device *spi) ...@@ -692,8 +712,8 @@ static int bfin_spi_setup(struct spi_device *spi)
chip->clock = hz_to_spi_clock(drv_data->sclk, spi->max_speed_hz); chip->clock = hz_to_spi_clock(drv_data->sclk, spi->max_speed_hz);
bfin_spi_cs_enable(drv_data, chip); adi_spi_cs_enable(drv_data, chip);
bfin_spi_cs_deactive(drv_data, chip); adi_spi_cs_deactive(drv_data, chip);
return 0; return 0;
error: error:
...@@ -705,10 +725,10 @@ static int bfin_spi_setup(struct spi_device *spi) ...@@ -705,10 +725,10 @@ static int bfin_spi_setup(struct spi_device *spi)
return ret; return ret;
} }
static void bfin_spi_cleanup(struct spi_device *spi) static void adi_spi_cleanup(struct spi_device *spi)
{ {
struct bfin_spi_device *chip = spi_get_ctldata(spi); struct adi_spi_device *chip = spi_get_ctldata(spi);
struct bfin_spi_master *drv_data = spi_master_get_devdata(spi->master); struct adi_spi_master *drv_data = spi_master_get_devdata(spi->master);
if (!chip) if (!chip)
return; return;
...@@ -716,7 +736,7 @@ static void bfin_spi_cleanup(struct spi_device *spi) ...@@ -716,7 +736,7 @@ static void bfin_spi_cleanup(struct spi_device *spi)
if (chip->cs < MAX_CTRL_CS) { if (chip->cs < MAX_CTRL_CS) {
peripheral_free(ssel[spi->master->bus_num] peripheral_free(ssel[spi->master->bus_num]
[chip->cs-1]); [chip->cs-1]);
bfin_spi_cs_disable(drv_data, chip); adi_spi_cs_disable(drv_data, chip);
} else { } else {
gpio_free(chip->cs_gpio); gpio_free(chip->cs_gpio);
} }
...@@ -725,10 +745,11 @@ static void bfin_spi_cleanup(struct spi_device *spi) ...@@ -725,10 +745,11 @@ static void bfin_spi_cleanup(struct spi_device *spi)
spi_set_ctldata(spi, NULL); spi_set_ctldata(spi, NULL);
} }
static irqreturn_t bfin_spi_tx_dma_isr(int irq, void *dev_id) static irqreturn_t adi_spi_tx_dma_isr(int irq, void *dev_id)
{ {
struct bfin_spi_master *drv_data = dev_id; struct adi_spi_master *drv_data = dev_id;
u32 dma_stat = get_dma_curr_irqstat(drv_data->tx_dma); u32 dma_stat = get_dma_curr_irqstat(drv_data->tx_dma);
u32 tx_ctl;
clear_dma_irqstat(drv_data->tx_dma); clear_dma_irqstat(drv_data->tx_dma);
if (dma_stat & DMA_DONE) { if (dma_stat & DMA_DONE) {
...@@ -739,13 +760,15 @@ static irqreturn_t bfin_spi_tx_dma_isr(int irq, void *dev_id) ...@@ -739,13 +760,15 @@ static irqreturn_t bfin_spi_tx_dma_isr(int irq, void *dev_id)
if (drv_data->tx) if (drv_data->tx)
drv_data->state = ERROR_STATE; drv_data->state = ERROR_STATE;
} }
bfin_write_and(&drv_data->regs->tx_control, ~SPI_TXCTL_TDR_NF); tx_ctl = ioread32(&drv_data->regs->tx_control);
tx_ctl &= ~SPI_TXCTL_TDR_NF;
iowrite32(tx_ctl, &drv_data->regs->tx_control);
return IRQ_HANDLED; return IRQ_HANDLED;
} }
static irqreturn_t bfin_spi_rx_dma_isr(int irq, void *dev_id) static irqreturn_t adi_spi_rx_dma_isr(int irq, void *dev_id)
{ {
struct bfin_spi_master *drv_data = dev_id; struct adi_spi_master *drv_data = dev_id;
struct spi_message *msg = drv_data->cur_msg; struct spi_message *msg = drv_data->cur_msg;
u32 dma_stat = get_dma_curr_irqstat(drv_data->rx_dma); u32 dma_stat = get_dma_curr_irqstat(drv_data->rx_dma);
...@@ -760,8 +783,8 @@ static irqreturn_t bfin_spi_rx_dma_isr(int irq, void *dev_id) ...@@ -760,8 +783,8 @@ static irqreturn_t bfin_spi_rx_dma_isr(int irq, void *dev_id)
dev_err(&drv_data->master->dev, dev_err(&drv_data->master->dev,
"spi rx dma error: %d\n", dma_stat); "spi rx dma error: %d\n", dma_stat);
} }
bfin_write(&drv_data->regs->tx_control, 0); iowrite32(0, &drv_data->regs->tx_control);
bfin_write(&drv_data->regs->rx_control, 0); iowrite32(0, &drv_data->regs->rx_control);
if (drv_data->rx_num != drv_data->tx_num) if (drv_data->rx_num != drv_data->tx_num)
dev_dbg(&drv_data->master->dev, dev_dbg(&drv_data->master->dev,
"dma interrupt missing: tx=%d,rx=%d\n", "dma interrupt missing: tx=%d,rx=%d\n",
...@@ -770,15 +793,15 @@ static irqreturn_t bfin_spi_rx_dma_isr(int irq, void *dev_id) ...@@ -770,15 +793,15 @@ static irqreturn_t bfin_spi_rx_dma_isr(int irq, void *dev_id)
return IRQ_HANDLED; return IRQ_HANDLED;
} }
static int bfin_spi_probe(struct platform_device *pdev) static int adi_spi_probe(struct platform_device *pdev)
{ {
struct device *dev = &pdev->dev; struct device *dev = &pdev->dev;
struct bfin_spi3_master *info = dev_get_platdata(dev); struct adi_spi3_master *info = dev_get_platdata(dev);
struct spi_master *master; struct spi_master *master;
struct bfin_spi_master *drv_data; struct adi_spi_master *drv_data;
struct resource *mem, *res; struct resource *mem, *res;
unsigned int tx_dma, rx_dma; unsigned int tx_dma, rx_dma;
unsigned long sclk; struct clk *sclk;
int ret; int ret;
if (!info) { if (!info) {
...@@ -786,10 +809,10 @@ static int bfin_spi_probe(struct platform_device *pdev) ...@@ -786,10 +809,10 @@ static int bfin_spi_probe(struct platform_device *pdev)
return -ENODEV; return -ENODEV;
} }
sclk = get_sclk1(); sclk = devm_clk_get(dev, "spi");
if (!sclk) { if (IS_ERR(sclk)) {
dev_err(dev, "can not get sclk1\n"); dev_err(dev, "can not get spi clock\n");
return -ENXIO; return PTR_ERR(sclk);
} }
res = platform_get_resource(pdev, IORESOURCE_DMA, 0); res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
...@@ -819,9 +842,9 @@ static int bfin_spi_probe(struct platform_device *pdev) ...@@ -819,9 +842,9 @@ static int bfin_spi_probe(struct platform_device *pdev)
master->bus_num = pdev->id; master->bus_num = pdev->id;
master->num_chipselect = info->num_chipselect; master->num_chipselect = info->num_chipselect;
master->cleanup = bfin_spi_cleanup; master->cleanup = adi_spi_cleanup;
master->setup = bfin_spi_setup; master->setup = adi_spi_setup;
master->transfer_one_message = bfin_spi_transfer_one_message; master->transfer_one_message = adi_spi_transfer_one_message;
master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
SPI_BPW_MASK(8); SPI_BPW_MASK(8);
...@@ -830,7 +853,7 @@ static int bfin_spi_probe(struct platform_device *pdev) ...@@ -830,7 +853,7 @@ static int bfin_spi_probe(struct platform_device *pdev)
drv_data->tx_dma = tx_dma; drv_data->tx_dma = tx_dma;
drv_data->rx_dma = rx_dma; drv_data->rx_dma = rx_dma;
drv_data->pin_req = info->pin_req; drv_data->pin_req = info->pin_req;
drv_data->sclk = sclk; drv_data->sclk = clk_get_rate(sclk);
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
drv_data->regs = devm_ioremap_resource(dev, mem); drv_data->regs = devm_ioremap_resource(dev, mem);
...@@ -845,28 +868,28 @@ static int bfin_spi_probe(struct platform_device *pdev) ...@@ -845,28 +868,28 @@ static int bfin_spi_probe(struct platform_device *pdev)
dev_err(dev, "can not request SPI TX DMA channel\n"); dev_err(dev, "can not request SPI TX DMA channel\n");
goto err_put_master; goto err_put_master;
} }
set_dma_callback(tx_dma, bfin_spi_tx_dma_isr, drv_data); set_dma_callback(tx_dma, adi_spi_tx_dma_isr, drv_data);
ret = request_dma(rx_dma, "SPI_RX_DMA"); ret = request_dma(rx_dma, "SPI_RX_DMA");
if (ret) { if (ret) {
dev_err(dev, "can not request SPI RX DMA channel\n"); dev_err(dev, "can not request SPI RX DMA channel\n");
goto err_free_tx_dma; goto err_free_tx_dma;
} }
set_dma_callback(drv_data->rx_dma, bfin_spi_rx_dma_isr, drv_data); set_dma_callback(drv_data->rx_dma, adi_spi_rx_dma_isr, drv_data);
/* request CLK, MOSI and MISO */ /* request CLK, MOSI and MISO */
ret = peripheral_request_list(drv_data->pin_req, "bfin-spi3"); ret = peripheral_request_list(drv_data->pin_req, "adi-spi3");
if (ret < 0) { if (ret < 0) {
dev_err(dev, "can not request spi pins\n"); dev_err(dev, "can not request spi pins\n");
goto err_free_rx_dma; goto err_free_rx_dma;
} }
bfin_write(&drv_data->regs->control, SPI_CTL_MSTR | SPI_CTL_CPHA); iowrite32(SPI_CTL_MSTR | SPI_CTL_CPHA, &drv_data->regs->control);
bfin_write(&drv_data->regs->ssel, 0x0000FE00); iowrite32(0x0000FE00, &drv_data->regs->ssel);
bfin_write(&drv_data->regs->delay, 0x0); iowrite32(0x0, &drv_data->regs->delay);
tasklet_init(&drv_data->pump_transfers, tasklet_init(&drv_data->pump_transfers,
bfin_spi_pump_transfers, (unsigned long)drv_data); adi_spi_pump_transfers, (unsigned long)drv_data);
/* register with the SPI framework */ /* register with the SPI framework */
ret = devm_spi_register_master(dev, master); ret = devm_spi_register_master(dev, master);
if (ret) { if (ret) {
...@@ -888,43 +911,41 @@ static int bfin_spi_probe(struct platform_device *pdev) ...@@ -888,43 +911,41 @@ static int bfin_spi_probe(struct platform_device *pdev)
return ret; return ret;
} }
static int bfin_spi_remove(struct platform_device *pdev) static int adi_spi_remove(struct platform_device *pdev)
{ {
struct spi_master *master = platform_get_drvdata(pdev); struct spi_master *master = platform_get_drvdata(pdev);
struct bfin_spi_master *drv_data = spi_master_get_devdata(master); struct adi_spi_master *drv_data = spi_master_get_devdata(master);
bfin_spi_disable(drv_data);
adi_spi_disable(drv_data);
peripheral_free_list(drv_data->pin_req); peripheral_free_list(drv_data->pin_req);
free_dma(drv_data->rx_dma); free_dma(drv_data->rx_dma);
free_dma(drv_data->tx_dma); free_dma(drv_data->tx_dma);
return 0; return 0;
} }
#ifdef CONFIG_PM #ifdef CONFIG_PM
static int bfin_spi_suspend(struct device *dev) static int adi_spi_suspend(struct device *dev)
{ {
struct spi_master *master = dev_get_drvdata(dev); struct spi_master *master = dev_get_drvdata(dev);
struct bfin_spi_master *drv_data = spi_master_get_devdata(master); struct adi_spi_master *drv_data = spi_master_get_devdata(master);
spi_master_suspend(master); spi_master_suspend(master);
drv_data->control = bfin_read(&drv_data->regs->control); drv_data->control = ioread32(&drv_data->regs->control);
drv_data->ssel = bfin_read(&drv_data->regs->ssel); drv_data->ssel = ioread32(&drv_data->regs->ssel);
bfin_write(&drv_data->regs->control, SPI_CTL_MSTR | SPI_CTL_CPHA); iowrite32(SPI_CTL_MSTR | SPI_CTL_CPHA, &drv_data->regs->control);
bfin_write(&drv_data->regs->ssel, 0x0000FE00); iowrite32(0x0000FE00, &drv_data->regs->ssel);
dma_disable_irq(drv_data->rx_dma); dma_disable_irq(drv_data->rx_dma);
dma_disable_irq(drv_data->tx_dma); dma_disable_irq(drv_data->tx_dma);
return 0; return 0;
} }
static int bfin_spi_resume(struct device *dev) static int adi_spi_resume(struct device *dev)
{ {
struct spi_master *master = dev_get_drvdata(dev); struct spi_master *master = dev_get_drvdata(dev);
struct bfin_spi_master *drv_data = spi_master_get_devdata(master); struct adi_spi_master *drv_data = spi_master_get_devdata(master);
int ret = 0; int ret = 0;
/* bootrom may modify spi and dma status when resume in spi boot mode */ /* bootrom may modify spi and dma status when resume in spi boot mode */
...@@ -932,8 +953,8 @@ static int bfin_spi_resume(struct device *dev) ...@@ -932,8 +953,8 @@ static int bfin_spi_resume(struct device *dev)
dma_enable_irq(drv_data->rx_dma); dma_enable_irq(drv_data->rx_dma);
dma_enable_irq(drv_data->tx_dma); dma_enable_irq(drv_data->tx_dma);
bfin_write(&drv_data->regs->control, drv_data->control); iowrite32(drv_data->control, &drv_data->regs->control);
bfin_write(&drv_data->regs->ssel, drv_data->ssel); iowrite32(drv_data->ssel, &drv_data->regs->ssel);
ret = spi_master_resume(master); ret = spi_master_resume(master);
if (ret) { if (ret) {
...@@ -944,21 +965,21 @@ static int bfin_spi_resume(struct device *dev) ...@@ -944,21 +965,21 @@ static int bfin_spi_resume(struct device *dev)
return ret; return ret;
} }
#endif #endif
static const struct dev_pm_ops bfin_spi_pm_ops = { static const struct dev_pm_ops adi_spi_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(bfin_spi_suspend, bfin_spi_resume) SET_SYSTEM_SLEEP_PM_OPS(adi_spi_suspend, adi_spi_resume)
}; };
MODULE_ALIAS("platform:bfin-spi3"); MODULE_ALIAS("platform:adi-spi3");
static struct platform_driver bfin_spi_driver = { static struct platform_driver adi_spi_driver = {
.driver = { .driver = {
.name = "bfin-spi3", .name = "adi-spi3",
.owner = THIS_MODULE, .owner = THIS_MODULE,
.pm = &bfin_spi_pm_ops, .pm = &adi_spi_pm_ops,
}, },
.remove = bfin_spi_remove, .remove = adi_spi_remove,
}; };
module_platform_driver_probe(bfin_spi_driver, bfin_spi_probe); module_platform_driver_probe(adi_spi_driver, adi_spi_probe);
MODULE_DESCRIPTION("Analog Devices SPI3 controller driver"); MODULE_DESCRIPTION("Analog Devices SPI3 controller driver");
MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>"); MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>");
......
drivers/spi/spi-atmel.c
View file @ 446fe5e2
...@@ -224,7 +224,7 @@ struct atmel_spi { ...@@ -224,7 +224,7 @@ struct atmel_spi {
struct platform_device *pdev; struct platform_device *pdev;
struct spi_transfer *current_transfer; struct spi_transfer *current_transfer;
unsigned long current_remaining_bytes; int current_remaining_bytes;
int done_status; int done_status;
struct completion xfer_completion; struct completion xfer_completion;
...@@ -874,8 +874,9 @@ atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer) ...@@ -874,8 +874,9 @@ atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
spi_readl(as, RDR); spi_readl(as, RDR);
} }
if (xfer->bits_per_word > 8) { if (xfer->bits_per_word > 8) {
as->current_remaining_bytes -= 2; if (as->current_remaining_bytes > 2)
if (as->current_remaining_bytes < 0) as->current_remaining_bytes -= 2;
else
as->current_remaining_bytes = 0; as->current_remaining_bytes = 0;
} else { } else {
as->current_remaining_bytes--; as->current_remaining_bytes--;
...@@ -1110,6 +1111,8 @@ static int atmel_spi_one_transfer(struct spi_master *master, ...@@ -1110,6 +1111,8 @@ static int atmel_spi_one_transfer(struct spi_master *master,
atmel_spi_next_xfer_pio(master, xfer); atmel_spi_next_xfer_pio(master, xfer);
} else { } else {
as->current_remaining_bytes -= len; as->current_remaining_bytes -= len;
if (as->current_remaining_bytes < 0)
as->current_remaining_bytes = 0;
} }
} else { } else {
atmel_spi_next_xfer_pio(master, xfer); atmel_spi_next_xfer_pio(master, xfer);
......
drivers/spi/spi-cadence.c 0 → 100644
View file @ 446fe5e2
/*
* Cadence SPI controller driver (master mode only)
*
* Copyright (C) 2008 - 2014 Xilinx, Inc.
*
* based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
/* Name of this driver */
#define CDNS_SPI_NAME "cdns-spi"
/* Register offset definitions */
#define CDNS_SPI_CR_OFFSET 0x00 /* Configuration Register, RW */
#define CDNS_SPI_ISR_OFFSET 0x04 /* Interrupt Status Register, RO */
#define CDNS_SPI_IER_OFFSET 0x08 /* Interrupt Enable Register, WO */
#define CDNS_SPI_IDR_OFFSET 0x0c /* Interrupt Disable Register, WO */
#define CDNS_SPI_IMR_OFFSET 0x10 /* Interrupt Enabled Mask Register, RO */
#define CDNS_SPI_ER_OFFSET 0x14 /* Enable/Disable Register, RW */
#define CDNS_SPI_DR_OFFSET 0x18 /* Delay Register, RW */
#define CDNS_SPI_TXD_OFFSET 0x1C /* Data Transmit Register, WO */
#define CDNS_SPI_RXD_OFFSET 0x20 /* Data Receive Register, RO */
#define CDNS_SPI_SICR_OFFSET 0x24 /* Slave Idle Count Register, RW */
#define CDNS_SPI_THLD_OFFSET 0x28 /* Transmit FIFO Watermark Register,RW */
/*
* SPI Configuration Register bit Masks
*
* This register contains various control bits that affect the operation
* of the SPI controller
*/
#define CDNS_SPI_CR_MANSTRT_MASK 0x00010000 /* Manual TX Start */
#define CDNS_SPI_CR_CPHA_MASK 0x00000004 /* Clock Phase Control */
#define CDNS_SPI_CR_CPOL_MASK 0x00000002 /* Clock Polarity Control */
#define CDNS_SPI_CR_SSCTRL_MASK 0x00003C00 /* Slave Select Mask */
#define CDNS_SPI_CR_BAUD_DIV_MASK 0x00000038 /* Baud Rate Divisor Mask */
#define CDNS_SPI_CR_MSTREN_MASK 0x00000001 /* Master Enable Mask */
#define CDNS_SPI_CR_MANSTRTEN_MASK 0x00008000 /* Manual TX Enable Mask */
#define CDNS_SPI_CR_SSFORCE_MASK 0x00004000 /* Manual SS Enable Mask */
#define CDNS_SPI_CR_BAUD_DIV_4_MASK 0x00000008 /* Default Baud Div Mask */
#define CDNS_SPI_CR_DEFAULT_MASK (CDNS_SPI_CR_MSTREN_MASK | \
CDNS_SPI_CR_SSCTRL_MASK | \
CDNS_SPI_CR_SSFORCE_MASK | \
CDNS_SPI_CR_BAUD_DIV_4_MASK)
/*
* SPI Configuration Register - Baud rate and slave select
*
* These are the values used in the calculation of baud rate divisor and
* setting the slave select.
*/
#define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
#define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */
#define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */
#define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */
#define CDNS_SPI_SS0 0x1 /* Slave Select zero */
/*
* SPI Interrupt Registers bit Masks
*
* All the four interrupt registers (Status/Mask/Enable/Disable) have the same
* bit definitions.
*/
#define CDNS_SPI_IXR_TXOW_MASK 0x00000004 /* SPI TX FIFO Overwater */
#define CDNS_SPI_IXR_MODF_MASK 0x00000002 /* SPI Mode Fault */
#define CDNS_SPI_IXR_RXNEMTY_MASK 0x00000010 /* SPI RX FIFO Not Empty */
#define CDNS_SPI_IXR_DEFAULT_MASK (CDNS_SPI_IXR_TXOW_MASK | \
CDNS_SPI_IXR_MODF_MASK)
#define CDNS_SPI_IXR_TXFULL_MASK 0x00000008 /* SPI TX Full */
#define CDNS_SPI_IXR_ALL_MASK 0x0000007F /* SPI all interrupts */
/*
* SPI Enable Register bit Masks
*
* This register is used to enable or disable the SPI controller
*/
#define CDNS_SPI_ER_ENABLE_MASK 0x00000001 /* SPI Enable Bit Mask */
#define CDNS_SPI_ER_DISABLE_MASK 0x0 /* SPI Disable Bit Mask */
/* SPI FIFO depth in bytes */
#define CDNS_SPI_FIFO_DEPTH 128
/* Default number of chip select lines */
#define CDNS_SPI_DEFAULT_NUM_CS 4
/**
* struct cdns_spi - This definition defines spi driver instance
* @regs: Virtual address of the SPI controller registers
* @ref_clk: Pointer to the peripheral clock
* @pclk: Pointer to the APB clock
* @speed_hz: Current SPI bus clock speed in Hz
* @txbuf: Pointer to the TX buffer
* @rxbuf: Pointer to the RX buffer
* @tx_bytes: Number of bytes left to transfer
* @rx_bytes: Number of bytes requested
* @dev_busy: Device busy flag
* @is_decoded_cs: Flag for decoder property set or not
*/
struct cdns_spi {
void __iomem *regs;
struct clk *ref_clk;
struct clk *pclk;
u32 speed_hz;
const u8 *txbuf;
u8 *rxbuf;
int tx_bytes;
int rx_bytes;
u8 dev_busy;
u32 is_decoded_cs;
};
/* Macros for the SPI controller read/write */
static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
{
return readl_relaxed(xspi->regs + offset);
}
static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
{
writel_relaxed(val, xspi->regs + offset);
}
/**
* cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
* @xspi: Pointer to the cdns_spi structure
*
* On reset the SPI controller is configured to be in master mode, baud rate
* divisor is set to 4, threshold value for TX FIFO not full interrupt is set
* to 1 and size of the word to be transferred as 8 bit.
* This function initializes the SPI controller to disable and clear all the
* interrupts, enable manual slave select and manual start, deselect all the
* chip select lines, and enable the SPI controller.
*/
static void cdns_spi_init_hw(struct cdns_spi *xspi)
{
cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
CDNS_SPI_ER_DISABLE_MASK);
cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET,
CDNS_SPI_IXR_ALL_MASK);
/* Clear the RX FIFO */
while (cdns_spi_read(xspi, CDNS_SPI_ISR_OFFSET) &
CDNS_SPI_IXR_RXNEMTY_MASK)
cdns_spi_read(xspi, CDNS_SPI_RXD_OFFSET);
cdns_spi_write(xspi, CDNS_SPI_ISR_OFFSET,
CDNS_SPI_IXR_ALL_MASK);
cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET,
CDNS_SPI_CR_DEFAULT_MASK);
cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
CDNS_SPI_ER_ENABLE_MASK);
}
/**
* cdns_spi_chipselect - Select or deselect the chip select line
* @spi: Pointer to the spi_device structure
* @is_on: Select(0) or deselect (1) the chip select line
*/
static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
{
struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
u32 ctrl_reg;
ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR_OFFSET);
if (is_high) {
/* Deselect the slave */
ctrl_reg |= CDNS_SPI_CR_SSCTRL_MASK;
} else {
/* Select the slave */
ctrl_reg &= ~CDNS_SPI_CR_SSCTRL_MASK;
if (!(xspi->is_decoded_cs))
ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) <<
CDNS_SPI_SS_SHIFT) &
CDNS_SPI_CR_SSCTRL_MASK;
else
ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) &
CDNS_SPI_CR_SSCTRL_MASK;
}
cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg);
}
/**
* cdns_spi_config_clock_mode - Sets clock polarity and phase
* @spi: Pointer to the spi_device structure
*
* Sets the requested clock polarity and phase.
*/
static void cdns_spi_config_clock_mode(struct spi_device *spi)
{
struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
u32 ctrl_reg;
ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR_OFFSET);
/* Set the SPI clock phase and clock polarity */
ctrl_reg &= ~(CDNS_SPI_CR_CPHA_MASK | CDNS_SPI_CR_CPOL_MASK);
if (spi->mode & SPI_CPHA)
ctrl_reg |= CDNS_SPI_CR_CPHA_MASK;
if (spi->mode & SPI_CPOL)
ctrl_reg |= CDNS_SPI_CR_CPOL_MASK;
cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg);
}
/**
* cdns_spi_config_clock_freq - Sets clock frequency
* @spi: Pointer to the spi_device structure
* @transfer: Pointer to the spi_transfer structure which provides
* information about next transfer setup parameters
*
* Sets the requested clock frequency.
* Note: If the requested frequency is not an exact match with what can be
* obtained using the prescalar value the driver sets the clock frequency which
* is lower than the requested frequency (maximum lower) for the transfer. If
* the requested frequency is higher or lower than that is supported by the SPI
* controller the driver will set the highest or lowest frequency supported by
* controller.
*/
static void cdns_spi_config_clock_freq(struct spi_device *spi,
struct spi_transfer *transfer)
{
struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
u32 ctrl_reg, baud_rate_val;
unsigned long frequency;
frequency = clk_get_rate(xspi->ref_clk);
ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR_OFFSET);
/* Set the clock frequency */
if (xspi->speed_hz != transfer->speed_hz) {
/* first valid value is 1 */
baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
(frequency / (2 << baud_rate_val)) > transfer->speed_hz)
baud_rate_val++;
ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV_MASK;
ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
xspi->speed_hz = frequency / (2 << baud_rate_val);
}
cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg);
}
/**
* cdns_spi_setup_transfer - Configure SPI controller for specified transfer
* @spi: Pointer to the spi_device structure
* @transfer: Pointer to the spi_transfer structure which provides
* information about next transfer setup parameters
*
* Sets the operational mode of SPI controller for the next SPI transfer and
* sets the requested clock frequency.
*
* Return: Always 0
*/
static int cdns_spi_setup_transfer(struct spi_device *spi,
struct spi_transfer *transfer)
{
struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
cdns_spi_config_clock_freq(spi, transfer);
dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
__func__, spi->mode, spi->bits_per_word,
xspi->speed_hz);
return 0;
}
/**
* cdns_spi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
* @xspi: Pointer to the cdns_spi structure
*/
static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi)
{
unsigned long trans_cnt = 0;
while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&
(xspi->tx_bytes > 0)) {
if (xspi->txbuf)
cdns_spi_write(xspi, CDNS_SPI_TXD_OFFSET,
*xspi->txbuf++);
else
cdns_spi_write(xspi, CDNS_SPI_TXD_OFFSET, 0);
xspi->tx_bytes--;
trans_cnt++;
}
}
/**
* cdns_spi_irq - Interrupt service routine of the SPI controller
* @irq: IRQ number
* @dev_id: Pointer to the xspi structure
*
* This function handles TX empty and Mode Fault interrupts only.
* On TX empty interrupt this function reads the received data from RX FIFO and
* fills the TX FIFO if there is any data remaining to be transferred.
* On Mode Fault interrupt this function indicates that transfer is completed,
* the SPI subsystem will identify the error as the remaining bytes to be
* transferred is non-zero.
*
* Return: IRQ_HANDLED when handled; IRQ_NONE otherwise.
*/
static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
{
struct spi_master *master = dev_id;
struct cdns_spi *xspi = spi_master_get_devdata(master);
u32 intr_status, status;
status = IRQ_NONE;
intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR_OFFSET);
cdns_spi_write(xspi, CDNS_SPI_ISR_OFFSET, intr_status);
if (intr_status & CDNS_SPI_IXR_MODF_MASK) {
/* Indicate that transfer is completed, the SPI subsystem will
* identify the error as the remaining bytes to be
* transferred is non-zero
*/
cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET,
CDNS_SPI_IXR_DEFAULT_MASK);
spi_finalize_current_transfer(master);
status = IRQ_HANDLED;
} else if (intr_status & CDNS_SPI_IXR_TXOW_MASK) {
unsigned long trans_cnt;
trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
/* Read out the data from the RX FIFO */
while (trans_cnt) {
u8 data;
data = cdns_spi_read(xspi, CDNS_SPI_RXD_OFFSET);
if (xspi->rxbuf)
*xspi->rxbuf++ = data;
xspi->rx_bytes--;
trans_cnt--;
}
if (xspi->tx_bytes) {
/* There is more data to send */
cdns_spi_fill_tx_fifo(xspi);
} else {
/* Transfer is completed */
cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET,
CDNS_SPI_IXR_DEFAULT_MASK);
spi_finalize_current_transfer(master);
}
status = IRQ_HANDLED;
}
return status;
}
/**
* cdns_transfer_one - Initiates the SPI transfer
* @master: Pointer to spi_master structure
* @spi: Pointer to the spi_device structure
* @transfer: Pointer to the spi_transfer structure which provides
* information about next transfer parameters
*
* This function fills the TX FIFO, starts the SPI transfer and
* returns a positive transfer count so that core will wait for completion.
*
* Return: Number of bytes transferred in the last transfer
*/
static int cdns_transfer_one(struct spi_master *master,
struct spi_device *spi,
struct spi_transfer *transfer)
{
struct cdns_spi *xspi = spi_master_get_devdata(master);
xspi->txbuf = transfer->tx_buf;
xspi->rxbuf = transfer->rx_buf;
xspi->tx_bytes = transfer->len;
xspi->rx_bytes = transfer->len;
cdns_spi_setup_transfer(spi, transfer);
cdns_spi_fill_tx_fifo(xspi);
cdns_spi_write(xspi, CDNS_SPI_IER_OFFSET,
CDNS_SPI_IXR_DEFAULT_MASK);
return transfer->len;
}
/**
* cdns_prepare_transfer_hardware - Prepares hardware for transfer.
* @master: Pointer to the spi_master structure which provides
* information about the controller.
*
* This function enables SPI master controller.
*
* Return: 0 always
*/
static int cdns_prepare_transfer_hardware(struct spi_master *master)
{
struct cdns_spi *xspi = spi_master_get_devdata(master);
cdns_spi_config_clock_mode(master->cur_msg->spi);
cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
CDNS_SPI_ER_ENABLE_MASK);
return 0;
}
/**
* cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
* @master: Pointer to the spi_master structure which provides
* information about the controller.
*
* This function disables the SPI master controller.
*
* Return: 0 always
*/
static int cdns_unprepare_transfer_hardware(struct spi_master *master)
{
struct cdns_spi *xspi = spi_master_get_devdata(master);
cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
CDNS_SPI_ER_DISABLE_MASK);
return 0;
}
/**
* cdns_spi_probe - Probe method for the SPI driver
* @pdev: Pointer to the platform_device structure
*
* This function initializes the driver data structures and the hardware.
*
* Return: 0 on success and error value on error
*/
static int cdns_spi_probe(struct platform_device *pdev)
{
int ret = 0, irq;
struct spi_master *master;
struct cdns_spi *xspi;
struct resource *res;
u32 num_cs;
master = spi_alloc_master(&pdev->dev, sizeof(*xspi));
if (master == NULL)
return -ENOMEM;
xspi = spi_master_get_devdata(master);
master->dev.of_node = pdev->dev.of_node;
platform_set_drvdata(pdev, master);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
xspi->regs = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(xspi->regs)) {
ret = PTR_ERR(xspi->regs);
goto remove_master;
}
xspi->pclk = devm_clk_get(&pdev->dev, "pclk");
if (IS_ERR(xspi->pclk)) {
dev_err(&pdev->dev, "pclk clock not found.\n");
ret = PTR_ERR(xspi->pclk);
goto remove_master;
}
xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
if (IS_ERR(xspi->ref_clk)) {
dev_err(&pdev->dev, "ref_clk clock not found.\n");
ret = PTR_ERR(xspi->ref_clk);
goto remove_master;
}
ret = clk_prepare_enable(xspi->pclk);
if (ret) {
dev_err(&pdev->dev, "Unable to enable APB clock.\n");
goto remove_master;
}
ret = clk_prepare_enable(xspi->ref_clk);
if (ret) {
dev_err(&pdev->dev, "Unable to enable device clock.\n");
goto clk_dis_apb;
}
/* SPI controller initializations */
cdns_spi_init_hw(xspi);
irq = platform_get_irq(pdev, 0);
if (irq <= 0) {
ret = -ENXIO;
dev_err(&pdev->dev, "irq number is invalid\n");
goto remove_master;
}
ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
0, pdev->name, master);
if (ret != 0) {
ret = -ENXIO;
dev_err(&pdev->dev, "request_irq failed\n");
goto remove_master;
}
ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
if (ret < 0)
master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
else
master->num_chipselect = num_cs;
ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
&xspi->is_decoded_cs);
if (ret < 0)
xspi->is_decoded_cs = 0;
master->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
master->transfer_one = cdns_transfer_one;
master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
master->set_cs = cdns_spi_chipselect;
master->mode_bits = SPI_CPOL | SPI_CPHA;
/* Set to default valid value */
master->max_speed_hz = clk_get_rate(xspi->ref_clk) / 4;
xspi->speed_hz = master->max_speed_hz;
master->bits_per_word_mask = SPI_BPW_MASK(8);
ret = spi_register_master(master);
if (ret) {
dev_err(&pdev->dev, "spi_register_master failed\n");
goto clk_dis_all;
}
return ret;
clk_dis_all:
clk_disable_unprepare(xspi->ref_clk);
clk_dis_apb:
clk_disable_unprepare(xspi->pclk);
remove_master:
spi_master_put(master);
return ret;
}
/**
* cdns_spi_remove - Remove method for the SPI driver
* @pdev: Pointer to the platform_device structure
*
* This function is called if a device is physically removed from the system or
* if the driver module is being unloaded. It frees all resources allocated to
* the device.
*
* Return: 0 on success and error value on error
*/
static int cdns_spi_remove(struct platform_device *pdev)
{
struct spi_master *master = platform_get_drvdata(pdev);
struct cdns_spi *xspi = spi_master_get_devdata(master);
cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
CDNS_SPI_ER_DISABLE_MASK);
clk_disable_unprepare(xspi->ref_clk);
clk_disable_unprepare(xspi->pclk);
spi_unregister_master(master);
return 0;
}
/**
* cdns_spi_suspend - Suspend method for the SPI driver
* @dev: Address of the platform_device structure
*
* This function disables the SPI controller and
* changes the driver state to "suspend"
*
* Return: Always 0
*/
static int __maybe_unused cdns_spi_suspend(struct device *dev)
{
struct platform_device *pdev = container_of(dev,
struct platform_device, dev);
struct spi_master *master = platform_get_drvdata(pdev);
struct cdns_spi *xspi = spi_master_get_devdata(master);
spi_master_suspend(master);
clk_disable_unprepare(xspi->ref_clk);
clk_disable_unprepare(xspi->pclk);
return 0;
}
/**
* cdns_spi_resume - Resume method for the SPI driver
* @dev: Address of the platform_device structure
*
* This function changes the driver state to "ready"
*
* Return: 0 on success and error value on error
*/
static int __maybe_unused cdns_spi_resume(struct device *dev)
{
struct platform_device *pdev = container_of(dev,
struct platform_device, dev);
struct spi_master *master = platform_get_drvdata(pdev);
struct cdns_spi *xspi = spi_master_get_devdata(master);
int ret = 0;
ret = clk_prepare_enable(xspi->pclk);
if (ret) {
dev_err(dev, "Cannot enable APB clock.\n");
return ret;
}
ret = clk_prepare_enable(xspi->ref_clk);
if (ret) {
dev_err(dev, "Cannot enable device clock.\n");
clk_disable(xspi->pclk);
return ret;
}
spi_master_resume(master);
return 0;
}
static SIMPLE_DEV_PM_OPS(cdns_spi_dev_pm_ops, cdns_spi_suspend,
cdns_spi_resume);
static struct of_device_id cdns_spi_of_match[] = {
{ .compatible = "xlnx,zynq-spi-r1p6" },
{ .compatible = "cdns,spi-r1p6" },
{ /* end of table */ }
};
MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
/* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
static struct platform_driver cdns_spi_driver = {
.probe = cdns_spi_probe,
.remove = cdns_spi_remove,
.driver = {
.name = CDNS_SPI_NAME,
.owner = THIS_MODULE,
.of_match_table = cdns_spi_of_match,
.pm = &cdns_spi_dev_pm_ops,
},
};
module_platform_driver(cdns_spi_driver);
MODULE_AUTHOR("Xilinx, Inc.");
MODULE_DESCRIPTION("Cadence SPI driver");
MODULE_LICENSE("GPL");
arch/blackfin/include/asm/bfin_spi3.h → include/linux/spi/adi_spi3.h
View file @ 446fe5e2
/* /*
* Analog Devices SPI3 controller driver * Analog Devices SPI3 controller driver
* *
* Copyright (c) 2011 Analog Devices Inc. * Copyright (c) 2014 Analog Devices Inc.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
...@@ -11,14 +11,10 @@ ...@@ -11,14 +11,10 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#ifndef _SPI_CHANNEL_H_ #ifndef _ADI_SPI3_H_
#define _SPI_CHANNEL_H_ #define _ADI_SPI3_H_
#include <linux/types.h> #include <linux/types.h>
...@@ -209,9 +205,9 @@ ...@@ -209,9 +205,9 @@
#define SPI_ILAT_CLR_TFI 0x00000800 /* Transmit Finish Indication */ #define SPI_ILAT_CLR_TFI 0x00000800 /* Transmit Finish Indication */
/* /*
* bfin spi3 registers layout * adi spi3 registers layout
*/ */
struct bfin_spi_regs { struct adi_spi_regs {
u32 revid; u32 revid;
u32 control; u32 control;
u32 rx_control; u32 rx_control;
...@@ -240,7 +236,7 @@ struct bfin_spi_regs { ...@@ -240,7 +236,7 @@ struct bfin_spi_regs {
#define MAX_CTRL_CS 8 /* cs in spi controller */ #define MAX_CTRL_CS 8 /* cs in spi controller */
/* device.platform_data for SSP controller devices */ /* device.platform_data for SSP controller devices */
struct bfin_spi3_master { struct adi_spi3_master {
u16 num_chipselect; u16 num_chipselect;
u16 pin_req[7]; u16 pin_req[7];
}; };
...@@ -248,11 +244,11 @@ struct bfin_spi3_master { ...@@ -248,11 +244,11 @@ struct bfin_spi3_master {
/* spi_board_info.controller_data for SPI slave devices, /* spi_board_info.controller_data for SPI slave devices,
* copied to spi_device.platform_data ... mostly for dma tuning * copied to spi_device.platform_data ... mostly for dma tuning
*/ */
struct bfin_spi3_chip { struct adi_spi3_chip {
u32 control; u32 control;
u16 cs_chg_udelay; /* Some devices require 16-bit delays */ u16 cs_chg_udelay; /* Some devices require 16-bit delays */
u32 tx_dummy_val; /* tx value for rx only transfer */ u32 tx_dummy_val; /* tx value for rx only transfer */
bool enable_dma; bool enable_dma;
}; };
#endif /* _SPI_CHANNEL_H_ */ #endif /* _ADI_SPI3_H_ */
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