Commit 467786c1 authored by Priit Laes's avatar Priit Laes Committed by Greg Kroah-Hartman

staging: fbtft: Use standard MIPI DCS command defines for ili9341

This patch makes use of the standard MIPI Display Command Set to remove
some of the magic constants found in source code.
Signed-off-by: default avatarPriit Laes <plaes@plaes.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 261a984c
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <video/mipi_display.h>
#include "fbtft.h" #include "fbtft.h"
...@@ -39,9 +40,9 @@ static int init_display(struct fbtft_par *par) ...@@ -39,9 +40,9 @@ static int init_display(struct fbtft_par *par)
par->fbtftops.reset(par); par->fbtftops.reset(par);
/* startup sequence for MI0283QT-9A */ /* startup sequence for MI0283QT-9A */
write_reg(par, 0x01); /* software reset */ write_reg(par, MIPI_DCS_SOFT_RESET);
mdelay(5); mdelay(5);
write_reg(par, 0x28); /* display off */ write_reg(par, MIPI_DCS_SET_DISPLAY_OFF);
/* --------------------------------------------------------- */ /* --------------------------------------------------------- */
write_reg(par, 0xCF, 0x00, 0x83, 0x30); write_reg(par, 0xCF, 0x00, 0x83, 0x30);
write_reg(par, 0xED, 0x64, 0x03, 0x12, 0x81); write_reg(par, 0xED, 0x64, 0x03, 0x12, 0x81);
...@@ -56,18 +57,18 @@ static int init_display(struct fbtft_par *par) ...@@ -56,18 +57,18 @@ static int init_display(struct fbtft_par *par)
write_reg(par, 0xC5, 0x35, 0x3E); write_reg(par, 0xC5, 0x35, 0x3E);
write_reg(par, 0xC7, 0xBE); write_reg(par, 0xC7, 0xBE);
/* ------------memory access control------------------------ */ /* ------------memory access control------------------------ */
write_reg(par, 0x3A, 0x55); /* 16bit pixel */ write_reg(par, MIPI_DCS_SET_PIXEL_FORMAT, 0x55); /* 16bit pixel */
/* ------------frame rate----------------------------------- */ /* ------------frame rate----------------------------------- */
write_reg(par, 0xB1, 0x00, 0x1B); write_reg(par, 0xB1, 0x00, 0x1B);
/* ------------Gamma---------------------------------------- */ /* ------------Gamma---------------------------------------- */
/* write_reg(par, 0xF2, 0x08); */ /* Gamma Function Disable */ /* write_reg(par, 0xF2, 0x08); */ /* Gamma Function Disable */
write_reg(par, 0x26, 0x01); write_reg(par, MIPI_DCS_SET_GAMMA_CURVE, 0x01);
/* ------------display-------------------------------------- */ /* ------------display-------------------------------------- */
write_reg(par, 0xB7, 0x07); /* entry mode set */ write_reg(par, 0xB7, 0x07); /* entry mode set */
write_reg(par, 0xB6, 0x0A, 0x82, 0x27, 0x00); write_reg(par, 0xB6, 0x0A, 0x82, 0x27, 0x00);
write_reg(par, 0x11); /* sleep out */ write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE);
mdelay(100); mdelay(100);
write_reg(par, 0x29); /* display on */ write_reg(par, MIPI_DCS_SET_DISPLAY_ON);
mdelay(20); mdelay(20);
return 0; return 0;
...@@ -75,40 +76,39 @@ static int init_display(struct fbtft_par *par) ...@@ -75,40 +76,39 @@ static int init_display(struct fbtft_par *par)
static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye) static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
{ {
/* Column address set */ write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS,
write_reg(par, 0x2A,
(xs >> 8) & 0xFF, xs & 0xFF, (xe >> 8) & 0xFF, xe & 0xFF); (xs >> 8) & 0xFF, xs & 0xFF, (xe >> 8) & 0xFF, xe & 0xFF);
/* Row address set */ write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS,
write_reg(par, 0x2B,
(ys >> 8) & 0xFF, ys & 0xFF, (ye >> 8) & 0xFF, ye & 0xFF); (ys >> 8) & 0xFF, ys & 0xFF, (ye >> 8) & 0xFF, ye & 0xFF);
/* Memory write */ write_reg(par, MIPI_DCS_WRITE_MEMORY_START);
write_reg(par, 0x2C);
} }
#define MEM_Y (7) /* MY row address order */ #define MEM_Y BIT(7) /* MY row address order */
#define MEM_X (6) /* MX column address order */ #define MEM_X BIT(6) /* MX column address order */
#define MEM_V (5) /* MV row / column exchange */ #define MEM_V BIT(5) /* MV row / column exchange */
#define MEM_L (4) /* ML vertical refresh order */ #define MEM_L BIT(4) /* ML vertical refresh order */
#define MEM_H (2) /* MH horizontal refresh order */ #define MEM_H BIT(2) /* MH horizontal refresh order */
#define MEM_BGR (3) /* RGB-BGR Order */ #define MEM_BGR (3) /* RGB-BGR Order */
static int set_var(struct fbtft_par *par) static int set_var(struct fbtft_par *par)
{ {
switch (par->info->var.rotate) { switch (par->info->var.rotate) {
case 0: case 0:
write_reg(par, 0x36, (1 << MEM_X) | (par->bgr << MEM_BGR)); write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
MEM_X | (par->bgr << MEM_BGR));
break; break;
case 270: case 270:
write_reg(par, 0x36, write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
(1 << MEM_V) | (1 << MEM_L) | (par->bgr << MEM_BGR)); MEM_V | MEM_L | (par->bgr << MEM_BGR));
break; break;
case 180: case 180:
write_reg(par, 0x36, (1 << MEM_Y) | (par->bgr << MEM_BGR)); write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
MEM_Y | (par->bgr << MEM_BGR));
break; break;
case 90: case 90:
write_reg(par, 0x36, (1 << MEM_Y) | (1 << MEM_X) | write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
(1 << MEM_V) | (par->bgr << MEM_BGR)); MEM_Y | MEM_X | MEM_V | (par->bgr << MEM_BGR));
break; break;
} }
......
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