Commit 4d4dce31 authored by Grygorii Strashko's avatar Grygorii Strashko Committed by David S. Miller

net: ethernet: ti: am65-cpts: fix i2083 genf (and estf) Reconfiguration Issue

The new bit TX_GENF_CLR_EN has been added in AM65x SR2.0 to fix i2083
errata, which can be just set unconditionally for all SoCs.
Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 31b143e5
...@@ -83,6 +83,8 @@ struct am65_cpts_regs { ...@@ -83,6 +83,8 @@ struct am65_cpts_regs {
#define AM65_CPTS_CONTROL_HW8_TS_PUSH_EN BIT(15) #define AM65_CPTS_CONTROL_HW8_TS_PUSH_EN BIT(15)
#define AM65_CPTS_CONTROL_HW1_TS_PUSH_OFFSET (8) #define AM65_CPTS_CONTROL_HW1_TS_PUSH_OFFSET (8)
#define AM65_CPTS_CONTROL_TX_GENF_CLR_EN BIT(17)
#define AM65_CPTS_CONTROL_TS_SYNC_SEL_MASK (0xF) #define AM65_CPTS_CONTROL_TS_SYNC_SEL_MASK (0xF)
#define AM65_CPTS_CONTROL_TS_SYNC_SEL_SHIFT (28) #define AM65_CPTS_CONTROL_TS_SYNC_SEL_SHIFT (28)
...@@ -986,7 +988,9 @@ struct am65_cpts *am65_cpts_create(struct device *dev, void __iomem *regs, ...@@ -986,7 +988,9 @@ struct am65_cpts *am65_cpts_create(struct device *dev, void __iomem *regs,
am65_cpts_set_add_val(cpts); am65_cpts_set_add_val(cpts);
am65_cpts_write32(cpts, AM65_CPTS_CONTROL_EN | AM65_CPTS_CONTROL_64MODE, am65_cpts_write32(cpts, AM65_CPTS_CONTROL_EN |
AM65_CPTS_CONTROL_64MODE |
AM65_CPTS_CONTROL_TX_GENF_CLR_EN,
control); control);
am65_cpts_write32(cpts, AM65_CPTS_INT_ENABLE_TS_PEND_EN, int_enable); am65_cpts_write32(cpts, AM65_CPTS_INT_ENABLE_TS_PEND_EN, int_enable);
......
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