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Commit 572c61b3 authored by Kumar Gala's avatar Kumar Gala Committed by Linus Torvalds
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[PATCH] ppc32: fix whitespace for 85xx CDS common platform 

Fix whitespace in arch/ppc/platforms/85xx/mpc85xx_cds_common.c
Signed-off-by: default avatarKumar Gala <kumar.gala@freescale.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent fddaeff6
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Showing with 145 additions and 145 deletions
arch/ppc/platforms/85xx/mpc85xx_cds_common.c
View file @ 572c61b3
...@@ -73,60 +73,60 @@ static volatile u8 * cadmus; ...@@ -73,60 +73,60 @@ static volatile u8 * cadmus;
/* Internal interrupts are all Level Sensitive, and Positive Polarity */ /* Internal interrupts are all Level Sensitive, and Positive Polarity */
static u_char mpc85xx_cds_openpic_initsenses[] __initdata = { static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
#if defined(CONFIG_PCI) #if defined(CONFIG_PCI)
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI1 slot */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI1 slot */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI1 slot */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI1 slot */
#else #else
0x0, /* External 0: */ 0x0, /* External 0: */
0x0, /* External 1: */ 0x0, /* External 1: */
0x0, /* External 2: */ 0x0, /* External 2: */
0x0, /* External 3: */ 0x0, /* External 3: */
#endif #endif
0x0, /* External 4: */ 0x0, /* External 4: */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
0x0, /* External 6: */ 0x0, /* External 6: */
0x0, /* External 7: */ 0x0, /* External 7: */
0x0, /* External 8: */ 0x0, /* External 8: */
0x0, /* External 9: */ 0x0, /* External 9: */
0x0, /* External 10: */ 0x0, /* External 10: */
#if defined(CONFIG_85xx_PCI2) && defined(CONFIG_PCI) #if defined(CONFIG_85xx_PCI2) && defined(CONFIG_PCI)
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 11: PCI2 slot 0 */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 11: PCI2 slot 0 */
#else #else
0x0, /* External 11: */ 0x0, /* External 11: */
#endif #endif
}; };
...@@ -134,31 +134,31 @@ static u_char mpc85xx_cds_openpic_initsenses[] __initdata = { ...@@ -134,31 +134,31 @@ static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
int int
mpc85xx_cds_show_cpuinfo(struct seq_file *m) mpc85xx_cds_show_cpuinfo(struct seq_file *m)
{ {
uint pvid, svid, phid1; uint pvid, svid, phid1;
uint memsize = total_memory; uint memsize = total_memory;
bd_t *binfo = (bd_t *) __res; bd_t *binfo = (bd_t *) __res;
unsigned int freq; unsigned int freq;
/* get the core frequency */ /* get the core frequency */
freq = binfo->bi_intfreq; freq = binfo->bi_intfreq;
pvid = mfspr(PVR); pvid = mfspr(PVR);
svid = mfspr(SVR); svid = mfspr(SVR);
seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n"); seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
seq_printf(m, "Machine\t\t: CDS (%x)\n", cadmus[CM_VER]); seq_printf(m, "Machine\t\t: CDS (%x)\n", cadmus[CM_VER]);
seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000); seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
seq_printf(m, "PVR\t\t: 0x%x\n", pvid); seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
seq_printf(m, "SVR\t\t: 0x%x\n", svid); seq_printf(m, "SVR\t\t: 0x%x\n", svid);
/* Display cpu Pll setting */ /* Display cpu Pll setting */
phid1 = mfspr(HID1); phid1 = mfspr(HID1);
seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f)); seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
/* Display the amount of memory */ /* Display the amount of memory */
seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024)); seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
return 0; return 0;
} }
#ifdef CONFIG_CPM2 #ifdef CONFIG_CPM2
...@@ -185,21 +185,21 @@ mpc85xx_cds_init_IRQ(void) ...@@ -185,21 +185,21 @@ mpc85xx_cds_init_IRQ(void)
int i; int i;
#endif #endif
/* Determine the Physical Address of the OpenPIC regs */ /* Determine the Physical Address of the OpenPIC regs */
phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET; phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE); OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
OpenPIC_InitSenses = mpc85xx_cds_openpic_initsenses; OpenPIC_InitSenses = mpc85xx_cds_openpic_initsenses;
OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses); OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses);
/* Skip reserved space and internal sources */ /* Skip reserved space and internal sources */
openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200); openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
/* Map PIC IRQs 0-11 */ /* Map PIC IRQs 0-11 */
openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000); openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);
/* we let openpic interrupts starting from an offset, to /* we let openpic interrupts starting from an offset, to
* leave space for cascading interrupts underneath. * leave space for cascading interrupts underneath.
*/ */
openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET); openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
#ifdef CONFIG_CPM2 #ifdef CONFIG_CPM2
/* disable all CPM interupts */ /* disable all CPM interupts */
...@@ -219,7 +219,7 @@ mpc85xx_cds_init_IRQ(void) ...@@ -219,7 +219,7 @@ mpc85xx_cds_init_IRQ(void)
setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction); setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
#endif #endif
return; return;
} }
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
...@@ -278,8 +278,8 @@ mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) ...@@ -278,8 +278,8 @@ mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
} }
} }
#define ARCADIA_HOST_BRIDGE_IDSEL 17 #define ARCADIA_HOST_BRIDGE_IDSEL 17
#define ARCADIA_2ND_BRIDGE_IDSEL 3 #define ARCADIA_2ND_BRIDGE_IDSEL 3
extern int mpc85xx_pci1_last_busno; extern int mpc85xx_pci1_last_busno;
...@@ -289,7 +289,7 @@ mpc85xx_exclude_device(u_char bus, u_char devfn) ...@@ -289,7 +289,7 @@ mpc85xx_exclude_device(u_char bus, u_char devfn)
if (bus == 0 && PCI_SLOT(devfn) == 0) if (bus == 0 && PCI_SLOT(devfn) == 0)
return PCIBIOS_DEVICE_NOT_FOUND; return PCIBIOS_DEVICE_NOT_FOUND;
#ifdef CONFIG_85xx_PCI2 #ifdef CONFIG_85xx_PCI2
if (mpc85xx_pci1_last_busno) if (mpc85xx_pci1_last_busno)
if (bus == (mpc85xx_pci1_last_busno + 1) && PCI_SLOT(devfn) == 0) if (bus == (mpc85xx_pci1_last_busno + 1) && PCI_SLOT(devfn) == 0)
return PCIBIOS_DEVICE_NOT_FOUND; return PCIBIOS_DEVICE_NOT_FOUND;
#endif #endif
...@@ -311,14 +311,14 @@ mpc85xx_exclude_device(u_char bus, u_char devfn) ...@@ -311,14 +311,14 @@ mpc85xx_exclude_device(u_char bus, u_char devfn)
static void __init static void __init
mpc85xx_cds_setup_arch(void) mpc85xx_cds_setup_arch(void)
{ {
bd_t *binfo = (bd_t *) __res; bd_t *binfo = (bd_t *) __res;
unsigned int freq; unsigned int freq;
struct gianfar_platform_data *pdata; struct gianfar_platform_data *pdata;
/* get the core frequency */ /* get the core frequency */
freq = binfo->bi_intfreq; freq = binfo->bi_intfreq;
printk("mpc85xx_cds_setup_arch\n"); printk("mpc85xx_cds_setup_arch\n");
#ifdef CONFIG_CPM2 #ifdef CONFIG_CPM2
cpm2_reset(); cpm2_reset();
...@@ -328,17 +328,17 @@ mpc85xx_cds_setup_arch(void) ...@@ -328,17 +328,17 @@ mpc85xx_cds_setup_arch(void)
cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1; cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
printk("CDS Version = %x in PCI slot %d\n", cadmus[CM_VER], cds_pci_slot); printk("CDS Version = %x in PCI slot %d\n", cadmus[CM_VER], cds_pci_slot);
/* Set loops_per_jiffy to a half-way reasonable value, /* Set loops_per_jiffy to a half-way reasonable value,
for use until calibrate_delay gets called. */ for use until calibrate_delay gets called. */
loops_per_jiffy = freq / HZ; loops_per_jiffy = freq / HZ;
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
/* setup PCI host bridges */ /* setup PCI host bridges */
mpc85xx_setup_hose(); mpc85xx_setup_hose();
#endif #endif
#ifdef CONFIG_SERIAL_8250 #ifdef CONFIG_SERIAL_8250
mpc85xx_early_serial_map(); mpc85xx_early_serial_map();
#endif #endif
#ifdef CONFIG_SERIAL_TEXT_DEBUG #ifdef CONFIG_SERIAL_TEXT_DEBUG
...@@ -366,14 +366,14 @@ mpc85xx_cds_setup_arch(void) ...@@ -366,14 +366,14 @@ mpc85xx_cds_setup_arch(void)
#ifdef CONFIG_BLK_DEV_INITRD #ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start) if (initrd_start)
ROOT_DEV = Root_RAM0; ROOT_DEV = Root_RAM0;
else else
#endif #endif
#ifdef CONFIG_ROOT_NFS #ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS; ROOT_DEV = Root_NFS;
#else #else
ROOT_DEV = Root_HDA1; ROOT_DEV = Root_HDA1;
#endif #endif
} }
...@@ -382,18 +382,18 @@ void __init ...@@ -382,18 +382,18 @@ void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5, platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7) unsigned long r6, unsigned long r7)
{ {
/* parse_bootinfo must always be called first */ /* parse_bootinfo must always be called first */
parse_bootinfo(find_bootinfo()); parse_bootinfo(find_bootinfo());
/* /*
* If we were passed in a board information, copy it into the * If we were passed in a board information, copy it into the
* residual data area. * residual data area.
*/ */
if (r3) { if (r3) {
memcpy((void *) __res, (void *) (r3 + KERNELBASE), memcpy((void *) __res, (void *) (r3 + KERNELBASE),
sizeof (bd_t)); sizeof (bd_t));
} }
#ifdef CONFIG_SERIAL_TEXT_DEBUG #ifdef CONFIG_SERIAL_TEXT_DEBUG
{ {
bd_t *binfo = (bd_t *) __res; bd_t *binfo = (bd_t *) __res;
...@@ -401,7 +401,7 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, ...@@ -401,7 +401,7 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
/* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */ /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
settlbcam(NUM_TLBCAMS - 1, binfo->bi_immr_base, settlbcam(NUM_TLBCAMS - 1, binfo->bi_immr_base,
binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0); binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
memset(&p, 0, sizeof (p)); memset(&p, 0, sizeof (p));
p.iotype = SERIAL_IO_MEM; p.iotype = SERIAL_IO_MEM;
...@@ -420,49 +420,49 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, ...@@ -420,49 +420,49 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
#endif #endif
#if defined(CONFIG_BLK_DEV_INITRD) #if defined(CONFIG_BLK_DEV_INITRD)
/* /*
* If the init RAM disk has been configured in, and there's a valid * If the init RAM disk has been configured in, and there's a valid
* starting address for it, set it up. * starting address for it, set it up.
*/ */
if (r4) { if (r4) {
initrd_start = r4 + KERNELBASE; initrd_start = r4 + KERNELBASE;
initrd_end = r5 + KERNELBASE; initrd_end = r5 + KERNELBASE;
} }
#endif /* CONFIG_BLK_DEV_INITRD */ #endif /* CONFIG_BLK_DEV_INITRD */
/* Copy the kernel command line arguments to a safe place. */ /* Copy the kernel command line arguments to a safe place. */
if (r6) { if (r6) {
*(char *) (r7 + KERNELBASE) = 0; *(char *) (r7 + KERNELBASE) = 0;
strcpy(cmd_line, (char *) (r6 + KERNELBASE)); strcpy(cmd_line, (char *) (r6 + KERNELBASE));
} }
identify_ppc_sys_by_id(mfspr(SVR)); identify_ppc_sys_by_id(mfspr(SVR));
/* setup the PowerPC module struct */ /* setup the PowerPC module struct */
ppc_md.setup_arch = mpc85xx_cds_setup_arch; ppc_md.setup_arch = mpc85xx_cds_setup_arch;
ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo; ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo;
ppc_md.init_IRQ = mpc85xx_cds_init_IRQ; ppc_md.init_IRQ = mpc85xx_cds_init_IRQ;
ppc_md.get_irq = openpic_get_irq; ppc_md.get_irq = openpic_get_irq;
ppc_md.restart = mpc85xx_restart; ppc_md.restart = mpc85xx_restart;
ppc_md.power_off = mpc85xx_power_off; ppc_md.power_off = mpc85xx_power_off;
ppc_md.halt = mpc85xx_halt; ppc_md.halt = mpc85xx_halt;
ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory; ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
ppc_md.time_init = NULL; ppc_md.time_init = NULL;
ppc_md.set_rtc_time = NULL; ppc_md.set_rtc_time = NULL;
ppc_md.get_rtc_time = NULL; ppc_md.get_rtc_time = NULL;
ppc_md.calibrate_decr = mpc85xx_calibrate_decr; ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG) #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
ppc_md.progress = gen550_progress; ppc_md.progress = gen550_progress;
#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */ #endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
if (ppc_md.progress) if (ppc_md.progress)
ppc_md.progress("mpc85xx_cds_init(): exit", 0); ppc_md.progress("mpc85xx_cds_init(): exit", 0);
return; return;
} }
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