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Commit 593c535b authored by Marcel Ziswiler's avatar Marcel Ziswiler Committed by Shawn Guo
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arm64: dts: imx8mm-verdin: re-order pinctrl groups 

Alphabetically re-order pinctrl groups.
Signed-off-by: default avatarMarcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 60f01b5b
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Showing with 46 additions and 46 deletions
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
View file @ 593c535b
...@@ -796,36 +796,36 @@ pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { ...@@ -796,36 +796,36 @@ pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
pinctrl_ecspi2: ecspi2grp { pinctrl_ecspi2: ecspi2grp {
fsl,pins = fsl,pins =
<MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */
<MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */
<MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */ <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */
<MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */
<MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */
<MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */ <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */
}; };
pinctrl_ecspi3: ecspi3grp { pinctrl_ecspi3: ecspi3grp {
fsl,pins = fsl,pins =
<MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */
<MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */ <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */
<MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */ <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */
<MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */ <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */
<MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>, /* CAN_1_SPI_CS_1.8V# */ <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */
<MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>; /* CAN_2_SPI_CS#_1.8V */
}; };
pinctrl_fec1: fec1grp { pinctrl_fec1: fec1grp {
fsl,pins = fsl,pins =
<MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
<MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
<MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>,
<MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>,
<MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>,
<MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>,
<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
<MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
<MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>, <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
<MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>,
<MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>,
<MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>,
<MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>,
<MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>,
<MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>, <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>,
<MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>; <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>;
}; };
...@@ -834,17 +834,17 @@ pinctrl_fec1_sleep: fec1-sleepgrp { ...@@ -834,17 +834,17 @@ pinctrl_fec1_sleep: fec1-sleepgrp {
fsl,pins = fsl,pins =
<MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
<MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
<MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>,
<MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>,
<MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>,
<MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>,
<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
<MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
<MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>, <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
<MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>,
<MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>,
<MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>,
<MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>,
<MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>,
<MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>, <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>,
<MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>; <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>;
}; };
...@@ -854,11 +854,11 @@ pinctrl_flexspi0: flexspi0grp { ...@@ -854,11 +854,11 @@ pinctrl_flexspi0: flexspi0grp {
<MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */ <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */
<MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */ <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */
<MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */ <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */
<MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>, /* SODIMM 66 */
<MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */ <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */
<MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */ <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */
<MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */ <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */
<MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>; /* SODIMM 62 */ <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */
<MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */
}; };
pinctrl_gpio1: gpio1grp { pinctrl_gpio1: gpio1grp {
...@@ -1063,9 +1063,9 @@ pinctrl_reg_usb2_en: regusb2engrp { ...@@ -1063,9 +1063,9 @@ pinctrl_reg_usb2_en: regusb2engrp {
pinctrl_sai2: sai2grp { pinctrl_sai2: sai2grp {
fsl,pins = fsl,pins =
<MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */
<MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */
<MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */ <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */
<MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */
<MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */
<MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */ <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */
<MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */ <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */
}; };
...@@ -1095,23 +1095,23 @@ pinctrl_tsp: tspgrp { ...@@ -1095,23 +1095,23 @@ pinctrl_tsp: tspgrp {
pinctrl_uart1: uart1grp { pinctrl_uart1: uart1grp {
fsl,pins = fsl,pins =
<MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>, /* SODIMM 149 */ <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */
<MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>; /* SODIMM 147 */ <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */
}; };
pinctrl_uart2: uart2grp { pinctrl_uart2: uart2grp {
fsl,pins = fsl,pins =
<MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>, /* SODIMM 129 */
<MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */
<MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */ <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */
<MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>; /* SODIMM 135 */ <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */
<MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */
<MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */
}; };
pinctrl_uart3: uart3grp { pinctrl_uart3: uart3grp {
fsl,pins = fsl,pins =
<MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */
<MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */
<MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */ <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */
<MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */
<MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */
<MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */ <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */
}; };
...@@ -1181,35 +1181,35 @@ pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { ...@@ -1181,35 +1181,35 @@ pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
pinctrl_usdhc2: usdhc2grp { pinctrl_usdhc2: usdhc2grp {
fsl,pins = fsl,pins =
<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */ <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */ <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */ <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */
<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */ <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */
<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */ <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */
<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>, /* SODIMM 72 */ <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */
<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>;
}; };
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = fsl,pins =
<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>, <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>,
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>, <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>,
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>, <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>,
<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>, <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>,
<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>, <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>,
<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>, <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>;
<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>;
}; };
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = fsl,pins =
<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>, <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>,
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>, <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>,
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>, <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>,
<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>, <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>,
<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>, <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>,
<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>, <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>;
<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>;
}; };
/* /*
...@@ -1218,32 +1218,32 @@ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { ...@@ -1218,32 +1218,32 @@ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
*/ */
pinctrl_usdhc3: usdhc3grp { pinctrl_usdhc3: usdhc3grp {
fsl,pins = fsl,pins =
<MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>,
<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>,
<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>, <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>,
<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>, <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>,
<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>, <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>,
<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>; <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>,
<MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>,
<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>;
}; };
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = fsl,pins =
<MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>,
<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>,
<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>, <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>,
<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>, <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>,
<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>, <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>,
<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>; <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>,
<MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>,
<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>;
}; };
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = fsl,pins =
<MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>,
<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>,
<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>, <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>,
<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>, <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>,
<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>, <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>,
<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>; <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>,
<MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>,
<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>;
}; };
pinctrl_wdog: wdoggrp { pinctrl_wdog: wdoggrp {
......
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