Commit 5f09237b authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher

drm/amdgpu: Add SDMA v4.4.2 golden settings

Add programming of SDMA golden settings for v4.4.2
Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 57a83b2d
...@@ -96,11 +96,22 @@ static int sdma_v4_4_2_irq_id_to_seq(unsigned client_id) ...@@ -96,11 +96,22 @@ static int sdma_v4_4_2_irq_id_to_seq(unsigned client_id)
static void sdma_v4_4_2_init_golden_registers(struct amdgpu_device *adev) static void sdma_v4_4_2_init_golden_registers(struct amdgpu_device *adev)
{ {
switch (adev->ip_versions[SDMA0_HWIP][0]) { u32 val;
case IP_VERSION(4, 4, 2): int i;
break;
default: for (i = 0; i < adev->sdma.num_instances; i++) {
break; val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG);
val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4);
val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG,
PIPE_INTERLEAVE_SIZE, 0);
WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val);
val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ);
val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS,
4);
val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ,
PIPE_INTERLEAVE_SIZE, 0);
WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val);
} }
} }
......
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