Commit 5fb4d2a7 authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu/gfx9: add ring reset callback

Add ring reset callback for compute.
Acked-by: default avatarVitaly Prosyak <vitaly.prosyak@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fb0a5834
...@@ -7118,6 +7118,43 @@ static void gfx_v9_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) ...@@ -7118,6 +7118,43 @@ static void gfx_v9_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)
amdgpu_ring_write(ring, ring->funcs->nop); amdgpu_ring_write(ring, ring->funcs->nop);
} }
static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring,
unsigned int vmid)
{
struct amdgpu_device *adev = ring->adev;
struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
struct amdgpu_ring *kiq_ring = &kiq->ring;
unsigned long flags;
int r;
if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
return -EINVAL;
spin_lock_irqsave(&kiq->ring_lock, flags);
if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
spin_unlock_irqrestore(&kiq->ring_lock, flags);
return -ENOMEM;
}
kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES,
0, 0);
amdgpu_ring_commit(kiq_ring);
spin_unlock_irqrestore(&kiq->ring_lock, flags);
r = amdgpu_ring_test_ring(kiq_ring);
if (r)
return r;
/* reset the ring */
ring->wptr = 0;
*ring->wptr_cpu_addr = 0;
amdgpu_ring_clear_ring(ring);
return amdgpu_ring_test_ring(ring);
}
static void gfx_v9_ip_print(void *handle, struct drm_printer *p) static void gfx_v9_ip_print(void *handle, struct drm_printer *p)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
...@@ -7364,6 +7401,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { ...@@ -7364,6 +7401,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
.soft_recovery = gfx_v9_0_ring_soft_recovery, .soft_recovery = gfx_v9_0_ring_soft_recovery,
.emit_mem_sync = gfx_v9_0_emit_mem_sync, .emit_mem_sync = gfx_v9_0_emit_mem_sync,
.emit_wave_limit = gfx_v9_0_emit_wave_limit, .emit_wave_limit = gfx_v9_0_emit_wave_limit,
.reset = gfx_v9_0_reset_kcq,
}; };
static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
......
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