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Kirill Smelkov
linux
Commits
5ff107df
Commit
5ff107df
authored
Sep 08, 2002
by
David S. Miller
Browse files
Options
Browse Files
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Plain Diff
[TIGON3] Initial TCP segmentation offload support.
parent
9bff8815
Changes
2
Show whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
409 additions
and
32 deletions
+409
-32
drivers/net/tg3.c
drivers/net/tg3.c
+408
-32
drivers/net/tg3.h
drivers/net/tg3.h
+1
-0
No files found.
drivers/net/tg3.c
View file @
5ff107df
...
...
@@ -2169,11 +2169,11 @@ static void tg3_set_txd_addr(struct tg3 *tp, int entry, dma_addr_t mapping)
}
#endif
static
void
tg3_set_txd
(
struct
tg3
*
,
int
,
dma_addr_t
,
int
,
u32
,
int
);
static
void
tg3_set_txd
(
struct
tg3
*
,
int
,
dma_addr_t
,
int
,
u32
,
u32
);
static
int
tigon3_4gb_hwbug_workaround
(
struct
tg3
*
tp
,
struct
sk_buff
*
skb
,
u32
guilty_entry
,
int
guilty_len
,
u32
last_plus_one
,
u32
*
start
)
u32
last_plus_one
,
u32
*
start
,
u32
mss
)
{
dma_addr_t
new_addr
;
u32
entry
=
*
start
;
...
...
@@ -2226,7 +2226,7 @@ static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
PCI_DMA_TODEVICE
);
tg3_set_txd
(
tp
,
entry
,
new_addr
,
new_skb
->
len
,
(
skb
->
ip_summed
==
CHECKSUM_HW
)
?
TXD_FLAG_TCPUDP_CSUM
:
0
,
1
);
TXD_FLAG_TCPUDP_CSUM
:
0
,
1
|
(
mss
<<
1
)
);
*
start
=
NEXT_TX
(
entry
);
/* Now clean up the sw ring entries. */
...
...
@@ -2258,29 +2258,26 @@ static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
static
void
tg3_set_txd
(
struct
tg3
*
tp
,
int
entry
,
dma_addr_t
mapping
,
int
len
,
u32
flags
,
int
is_end
)
u32
mss_and_
is_end
)
{
#if TG3_VLAN_TAG_USED
u
16
vlan_tag
=
0
;
#endif
int
is_end
=
(
mss_and_is_end
&
0x1
);
u
32
mss
=
(
mss_and_is_end
>>
1
)
;
u32
vlan_tag
=
0
;
if
(
is_end
)
flags
|=
TXD_FLAG_END
;
#if TG3_VLAN_TAG_USED
if
(
flags
&
TXD_FLAG_VLAN
)
{
vlan_tag
=
flags
>>
16
;
flags
&=
0xffff
;
}
#endif
vlan_tag
|=
(
mss
<<
TXD_MSS_SHIFT
);
if
(
tp
->
tg3_flags
&
TG3_FLAG_HOST_TXDS
)
{
struct
tg3_tx_buffer_desc
*
txd
=
&
tp
->
tx_ring
[
entry
];
txd
->
addr_hi
=
((
u64
)
mapping
>>
32
);
txd
->
addr_lo
=
((
u64
)
mapping
&
0xffffffff
);
txd
->
len_flags
=
(
len
<<
TXD_LEN_SHIFT
)
|
flags
;
#if TG3_VLAN_TAG_USED
txd
->
vlan_tag
=
vlan_tag
<<
TXD_VLAN_TAG_SHIFT
;
#endif
}
else
{
unsigned
long
txd
;
...
...
@@ -2297,9 +2294,7 @@ static void tg3_set_txd(struct tg3 *tp, int entry,
writel
(((
u64
)
mapping
&
0xffffffff
),
txd
+
TXD_ADDR
+
TG3_64BIT_REG_LOW
);
writel
(
len
<<
TXD_LEN_SHIFT
|
flags
,
txd
+
TXD_LEN_FLAGS
);
#if TG3_VLAN_TAG_USED
writel
(
vlan_tag
<<
TXD_VLAN_TAG_SHIFT
,
txd
+
TXD_VLAN_TAG
);
#endif
}
}
...
...
@@ -2317,7 +2312,7 @@ static int tg3_start_xmit_4gbug(struct sk_buff *skb, struct net_device *dev)
struct
tg3
*
tp
=
dev
->
priv
;
dma_addr_t
mapping
;
unsigned
int
i
;
u32
len
,
entry
,
base_flags
;
u32
len
,
entry
,
base_flags
,
mss
;
int
would_hit_hwbug
;
len
=
(
skb
->
len
-
skb
->
data_len
);
...
...
@@ -2341,6 +2336,13 @@ static int tg3_start_xmit_4gbug(struct sk_buff *skb, struct net_device *dev)
base_flags
=
0
;
if
(
skb
->
ip_summed
==
CHECKSUM_HW
)
base_flags
|=
TXD_FLAG_TCPUDP_CSUM
;
#ifdef NETIF_F_TSO
if
((
mss
=
skb_shinfo
(
skb
)
->
tso_size
)
!=
0
)
base_flags
|=
(
TXD_FLAG_CPU_PRE_DMA
|
TXD_FLAG_CPU_POST_DMA
);
#else
mss
=
0
;
#endif
#if TG3_VLAN_TAG_USED
if
(
tp
->
vlgrp
!=
NULL
&&
vlan_tx_tag_present
(
skb
))
base_flags
|=
(
TXD_FLAG_VLAN
|
...
...
@@ -2359,7 +2361,7 @@ static int tg3_start_xmit_4gbug(struct sk_buff *skb, struct net_device *dev)
would_hit_hwbug
=
entry
+
1
;
tg3_set_txd
(
tp
,
entry
,
mapping
,
len
,
base_flags
,
(
skb_shinfo
(
skb
)
->
nr_frags
==
0
));
(
skb_shinfo
(
skb
)
->
nr_frags
==
0
)
|
(
mss
<<
1
)
);
entry
=
NEXT_TX
(
entry
);
...
...
@@ -2388,7 +2390,7 @@ static int tg3_start_xmit_4gbug(struct sk_buff *skb, struct net_device *dev)
}
tg3_set_txd
(
tp
,
entry
,
mapping
,
len
,
base_flags
,
(
i
==
last
));
base_flags
,
(
i
==
last
)
|
(
mss
<<
1
)
);
entry
=
NEXT_TX
(
entry
);
}
...
...
@@ -2424,7 +2426,7 @@ static int tg3_start_xmit_4gbug(struct sk_buff *skb, struct net_device *dev)
if
(
tigon3_4gb_hwbug_workaround
(
tp
,
skb
,
entry
,
len
,
last_plus_one
,
&
start
))
&
start
,
mss
))
goto
out_unlock
;
entry
=
start
;
...
...
@@ -2476,7 +2478,7 @@ static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct
tg3
*
tp
=
dev
->
priv
;
dma_addr_t
mapping
;
u32
len
,
entry
,
base_flags
;
u32
len
,
entry
,
base_flags
,
mss
;
len
=
(
skb
->
len
-
skb
->
data_len
);
...
...
@@ -2499,6 +2501,13 @@ static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
base_flags
=
0
;
if
(
skb
->
ip_summed
==
CHECKSUM_HW
)
base_flags
|=
TXD_FLAG_TCPUDP_CSUM
;
#ifdef NETIF_F_TSO
if
((
mss
=
skb_shinfo
(
skb
)
->
tso_size
)
!=
0
)
base_flags
|=
(
TXD_FLAG_CPU_PRE_DMA
|
TXD_FLAG_CPU_POST_DMA
);
#else
mss
=
0
;
#endif
#if TG3_VLAN_TAG_USED
if
(
tp
->
vlgrp
!=
NULL
&&
vlan_tx_tag_present
(
skb
))
base_flags
|=
(
TXD_FLAG_VLAN
|
...
...
@@ -2512,7 +2521,7 @@ static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
pci_unmap_addr_set
(
&
tp
->
tx_buffers
[
entry
],
mapping
,
mapping
);
tg3_set_txd
(
tp
,
entry
,
mapping
,
len
,
base_flags
,
(
skb_shinfo
(
skb
)
->
nr_frags
==
0
));
(
skb_shinfo
(
skb
)
->
nr_frags
==
0
)
|
(
mss
<<
1
)
);
entry
=
NEXT_TX
(
entry
);
...
...
@@ -2535,7 +2544,7 @@ static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
pci_unmap_addr_set
(
&
tp
->
tx_buffers
[
entry
],
mapping
,
mapping
);
tg3_set_txd
(
tp
,
entry
,
mapping
,
len
,
base_flags
,
(
i
==
last
));
base_flags
,
(
i
==
last
)
|
(
mss
<<
1
)
);
entry
=
NEXT_TX
(
entry
);
}
...
...
@@ -3295,9 +3304,21 @@ static int tg3_reset_cpu(struct tg3 *tp, u32 offset)
return
0
;
}
struct
fw_info
{
unsigned
int
text_base
;
unsigned
int
text_len
;
u32
*
text_data
;
unsigned
int
rodata_base
;
unsigned
int
rodata_len
;
u32
*
rodata_data
;
unsigned
int
data_base
;
unsigned
int
data_len
;
u32
*
data_data
;
};
/* tp->lock is held. */
static
int
tg3_load_firmware_cpu
(
struct
tg3
*
tp
,
u32
cpu_base
,
u32
cpu_scratch_base
,
int
cpu_scratch_size
)
int
cpu_scratch_size
,
struct
fw_info
*
info
)
{
int
err
,
i
;
...
...
@@ -3309,21 +3330,24 @@ static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_b
tg3_write_indirect_reg32
(
tp
,
cpu_scratch_base
+
i
,
0
);
tw32
(
cpu_base
+
CPU_STATE
,
0xffffffff
);
tw32
(
cpu_base
+
CPU_MODE
,
tr32
(
cpu_base
+
CPU_MODE
)
|
CPU_MODE_HALT
);
for
(
i
=
0
;
i
<
(
TG3_FW_TEXT_LEN
/
sizeof
(
u32
));
i
++
)
for
(
i
=
0
;
i
<
(
info
->
text_len
/
sizeof
(
u32
));
i
++
)
tg3_write_indirect_reg32
(
tp
,
(
cpu_scratch_base
+
(
TG3_FW_TEXT_ADDR
&
0xffff
)
+
(
info
->
text_base
&
0xffff
)
+
(
i
*
sizeof
(
u32
))),
t3FwText
[
i
]);
for
(
i
=
0
;
i
<
(
TG3_FW_RODATA_LEN
/
sizeof
(
u32
));
i
++
)
(
info
->
text_data
?
info
->
text_data
[
i
]
:
0
));
for
(
i
=
0
;
i
<
(
info
->
rodata_len
/
sizeof
(
u32
));
i
++
)
tg3_write_indirect_reg32
(
tp
,
(
cpu_scratch_base
+
(
TG3_FW_RODATA_ADDR
&
0xffff
)
+
(
info
->
rodata_base
&
0xffff
)
+
(
i
*
sizeof
(
u32
))),
t3FwRodata
[
i
]);
for
(
i
=
0
;
i
<
(
TG3_FW_DATA_LEN
/
sizeof
(
u32
));
i
++
)
(
info
->
rodata_data
?
info
->
rodata_data
[
i
]
:
0
));
for
(
i
=
0
;
i
<
(
info
->
data_len
/
sizeof
(
u32
));
i
++
)
tg3_write_indirect_reg32
(
tp
,
(
cpu_scratch_base
+
(
TG3_FW_DATA_ADDR
&
0xffff
)
+
(
info
->
data_base
&
0xffff
)
+
(
i
*
sizeof
(
u32
))),
0
);
(
info
->
data_data
?
info
->
data_data
[
i
]
:
0
));
return
0
;
}
...
...
@@ -3331,15 +3355,28 @@ static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_b
/* tp->lock is held. */
static
int
tg3_load_5701_a0_firmware_fix
(
struct
tg3
*
tp
)
{
struct
fw_info
info
;
int
err
,
i
;
info
.
text_base
=
TG3_FW_TEXT_ADDR
;
info
.
text_len
=
TG3_FW_TEXT_LEN
;
info
.
text_data
=
&
tg3FwText
[
0
];
info
.
rodata_base
=
TG3_FW_RODATA_ADDR
;
info
.
rodata_len
=
TG3_FW_RODATA_LEN
;
info
.
rodata_data
=
&
tg3FwRodata
[
0
];
info
.
data_base
=
TG3_FW_DATA_ADDR
;
info
.
data_len
=
TG3_FW_DATA_LEN
;
info
.
data_data
=
NULL
;
err
=
tg3_load_firmware_cpu
(
tp
,
RX_CPU_BASE
,
RX_CPU_SCRATCH_BASE
,
RX_CPU_SCRATCH_SIZE
);
RX_CPU_SCRATCH_BASE
,
RX_CPU_SCRATCH_SIZE
,
&
info
);
if
(
err
)
return
err
;
err
=
tg3_load_firmware_cpu
(
tp
,
TX_CPU_BASE
,
TX_CPU_SCRATCH_BASE
,
TX_CPU_SCRATCH_SIZE
);
TX_CPU_SCRATCH_BASE
,
TX_CPU_SCRATCH_SIZE
,
&
info
);
if
(
err
)
return
err
;
...
...
@@ -3377,6 +3414,336 @@ static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
return
0
;
}
#ifdef NETIF_F_TSO
#define TG3_TSO_FW_RELEASE_MAJOR 0x1
#define TG3_TSO_FW_RELASE_MINOR 0x8
#define TG3_TSO_FW_RELEASE_FIX 0x0
#define TG3_TSO_FW_START_ADDR 0x08000000
#define TG3_TSO_FW_TEXT_ADDR 0x08000000
#define TG3_TSO_FW_TEXT_LEN 0x1650
#define TG3_TSO_FW_RODATA_ADDR 0x08001650
#define TG3_TSO_FW_RODATA_LEN 0x30
#define TG3_TSO_FW_DATA_ADDR 0x080016a0
#define TG3_TSO_FW_DATA_LEN 0x20
#define TG3_TSO_FW_SBSS_ADDR 0x080016c0
#define TG3_TSO_FW_SBSS_LEN 0x14
#define TG3_TSO_FW_BSS_ADDR 0x080016e0
#define TG3_TSO_FW_BSS_LEN 0x8fc
static
u32
tg3TsoFwText
[]
=
{
0x00000000
,
0x10000003
,
0x00000000
,
0x0000000d
,
0x0000000d
,
0x3c1d0800
,
0x37bd4000
,
0x03a0f021
,
0x3c100800
,
0x26100000
,
0x0e000010
,
0x00000000
,
0x0000000d
,
0x00000000
,
0x00000000
,
0x00000000
,
0x27bdffe0
,
0x3c1bc000
,
0xafbf0018
,
0x0e000058
,
0xaf60680c
,
0x3c040800
,
0x24841650
,
0x03602821
,
0x24060001
,
0x24070004
,
0xafa00010
,
0x0e00006c
,
0xafa00014
,
0x8f625c50
,
0x34420001
,
0xaf625c50
,
0x8f625c90
,
0x34420001
,
0xaf625c90
,
0x2402ffff
,
0x0e000098
,
0xaf625404
,
0x8fbf0018
,
0x03e00008
,
0x27bd0020
,
0x00000000
,
0x00000000
,
0x00000000
,
0x24030b60
,
0x24050fff
,
0xac000b50
,
0x00002021
,
0xac640000
,
0x24630004
,
0x0065102b
,
0x1440fffc
,
0x24840001
,
0x24030b60
,
0x0065102b
,
0x10400011
,
0x00002021
,
0x24090b54
,
0x3c06dead
,
0x34c6beef
,
0x24080b58
,
0x24070b5c
,
0x8c620000
,
0x50440006
,
0x24630004
,
0xad260000
,
0x8c620000
,
0xace40000
,
0xad020000
,
0x24630004
,
0x0065102b
,
0x1440fff6
,
0x24840001
,
0x03e00008
,
0x00000000
,
0x27bdfff8
,
0x18800009
,
0x00002821
,
0x8f63680c
,
0x8f62680c
,
0x1043fffe
,
0x00000000
,
0x24a50001
,
0x00a4102a
,
0x1440fff9
,
0x00000000
,
0x03e00008
,
0x27bd0008
,
0x3c020800
,
0x34423000
,
0x3c030800
,
0x34633000
,
0x3c040800
,
0x348437ff
,
0x3c010800
,
0xac2216c4
,
0x24020040
,
0x3c010800
,
0xac2216c8
,
0x3c010800
,
0xac2016c0
,
0xac600000
,
0x24630004
,
0x0083102b
,
0x5040fffd
,
0xac600000
,
0x03e00008
,
0x00000000
,
0x00804821
,
0x8faa0010
,
0x3c020800
,
0x8c4216c0
,
0x3c040800
,
0x8c8416c8
,
0x8fab0014
,
0x24430001
,
0x0044102b
,
0x3c010800
,
0xac2316c0
,
0x14400003
,
0x00004021
,
0x3c010800
,
0xac2016c0
,
0x3c020800
,
0x8c4216c0
,
0x3c030800
,
0x8c6316c4
,
0x91240000
,
0x00021140
,
0x00431021
,
0x00481021
,
0x25080001
,
0xa0440000
,
0x29020008
,
0x1440fff4
,
0x25290001
,
0x3c020800
,
0x8c4216c0
,
0x3c030800
,
0x8c6316c4
,
0x8f64680c
,
0x00021140
,
0x00431021
,
0xac440008
,
0xac45000c
,
0xac460010
,
0xac470014
,
0xac4a0018
,
0x03e00008
,
0xac4b001c
,
0x00000000
,
0x00000000
,
0x27bdffe0
,
0xafbf0018
,
0xafb10014
,
0x0e0000b6
,
0xafb00010
,
0x24110001
,
0x8f706820
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0x00442023
,
0x01603021
,
0x3082ffff
,
0xa4c00010
,
0x00621821
,
0x00021042
,
0x18400010
,
0x00a32821
,
0x00404021
,
0x94c20000
,
0x24c60002
,
0x00a22821
,
0x30c2007f
,
0x14400006
,
0x24e70001
,
0x8d430000
,
0x3c02007f
,
0x3442ff80
,
0x00625024
,
0x25460008
,
0x00e8102a
,
0x1440fff3
,
0x00000000
,
0x30820001
,
0x10400005
,
0x00051c02
,
0xa0c00001
,
0x94c20000
,
0x00a22821
,
0x00051c02
,
0x30a2ffff
,
0x00622821
,
0x00051402
,
0x00a22821
,
0x0a000415
,
0x30a5ffff
,
0x14c20063
,
0x00000000
,
0x3c090800
,
0x95291fb2
,
0x95030002
,
0x01a91023
,
0x1062005d
,
0x01003021
,
0x00003821
,
0x00002821
,
0x01a91023
,
0xa5020002
,
0x3082ffff
,
0x00021042
,
0x18400008
,
0xa500000a
,
0x00401821
,
0x94c20000
,
0x24e70001
,
0x00a22821
,
0x00e3102a
,
0x1440fffb
,
0x24c60002
,
0x00051c02
,
0x30a2ffff
,
0x00622821
,
0x00051402
,
0x00a22821
,
0x00a04821
,
0x00051027
,
0xa502000a
,
0x00002821
,
0x2506000c
,
0x00003821
,
0x94c20000
,
0x24e70001
,
0x00a22821
,
0x2ce20004
,
0x1440fffb
,
0x24c60002
,
0x95020002
,
0x00003821
,
0x91030009
,
0x00442023
,
0x01603021
,
0x3082ffff
,
0xa4c00010
,
0x3c040800
,
0x94841fb4
,
0x00621821
,
0x00a32821
,
0x00051c02
,
0x30a2ffff
,
0x00622821
,
0x00051c02
,
0x3c020800
,
0x94421fb0
,
0x00a34021
,
0x00441023
,
0x00021fc2
,
0x00431021
,
0x00021043
,
0x18400010
,
0x00002821
,
0x00402021
,
0x94c20000
,
0x24c60002
,
0x00a22821
,
0x30c2007f
,
0x14400006
,
0x24e70001
,
0x8d430000
,
0x3c02007f
,
0x3442ff80
,
0x00625024
,
0x25460008
,
0x00e4102a
,
0x1440fff3
,
0x00000000
,
0x3c020800
,
0x94421fcc
,
0x00a22821
,
0x00051c02
,
0x30a2ffff
,
0x00622821
,
0x00051402
,
0x00a22821
,
0x3102ffff
,
0x00a22821
,
0x00051c02
,
0x30a2ffff
,
0x00622821
,
0x00051402
,
0x00a22821
,
0x00a02021
,
0x00051027
,
0xa5620010
,
0xad800014
,
0x0a000435
,
0xad800000
,
0x8d830010
,
0x00602021
,
0x10a00007
,
0x00034c02
,
0x01252821
,
0x00051402
,
0x30a3ffff
,
0x00432821
,
0x00051402
,
0x00a24821
,
0x00091027
,
0xa502000a
,
0x3c030800
,
0x94631fb4
,
0x3082ffff
,
0x01a21021
,
0x00432823
,
0x00a72821
,
0x00051c02
,
0x30a2ffff
,
0x00622821
,
0x00051402
,
0x00a22821
,
0x00a02021
,
0x00051027
,
0xa5620010
,
0x3082ffff
,
0x00091c00
,
0x00431025
,
0xad820010
,
0x3c020800
,
0x8c421fd4
,
0x10400002
,
0x25a2fff2
,
0xa5820034
,
0x3c020800
,
0x8c421fc8
,
0x3c030800
,
0x8c631720
,
0x24420001
,
0x3c010800
,
0xac221fc8
,
0x3c020800
,
0x8c421fc4
,
0x31c4ffff
,
0x00641821
,
0x3c010800
,
0xac231720
,
0x00441021
,
0x3c010800
,
0xac221fc4
,
0x03e00008
,
0x27bd0020
,
0x27bdffc8
,
0x3c040800
,
0x248416f8
,
0xafbf0034
,
0xafbe0030
,
0xafb7002c
,
0xafb60028
,
0xafb50024
,
0xafb40020
,
0xafb3001c
,
0xafb20018
,
0xafb10014
,
0xafb00010
,
0x90830000
,
0x24020003
,
0x146200f4
,
0x00000000
,
0x3c020800
,
0x8c421710
,
0x3c030800
,
0x8c63170c
,
0x3c1e0800
,
0x97de16f6
,
0x0043102a
,
0x104000eb
,
0x3c168000
,
0x249708c4
,
0x33d5ffff
,
0x24920018
,
0x3c020800
,
0x8c421718
,
0x104000e4
,
0x00000000
,
0x3c140800
,
0x96941fb0
,
0x3282ffff
,
0x104000d6
,
0x00008021
,
0x00409821
,
0x00008821
,
0x8f634450
,
0x3c020800
,
0x8c4216e8
,
0x00031c02
,
0x0043102b
,
0x14400008
,
0x00000000
,
0x3c040800
,
0x8c8416ec
,
0x8f624450
,
0x00021c02
,
0x0083102b
,
0x1040fffc
,
0x00000000
,
0xaf764444
,
0x8f624444
,
0x00561024
,
0x10400006
,
0x00000000
,
0x3c038000
,
0x8f624444
,
0x00431024
,
0x1440fffd
,
0x00000000
,
0x8f624448
,
0x3046ffff
,
0x10c0005f
,
0x00000000
,
0x3c090800
,
0x01314821
,
0x8d291728
,
0x9528000a
,
0x31020040
,
0x10400004
,
0x2407180c
,
0x8d22000c
,
0x2407188c
,
0xacc20018
,
0x31021000
,
0x10400004
,
0x34e32000
,
0x00081040
,
0x3042c000
,
0x00623825
,
0x31020080
,
0x54400001
,
0x34e70010
,
0x3c020800
,
0x00511021
,
0x8c421730
,
0x3c030800
,
0x00711821
,
0x8c631734
,
0x00021500
,
0x00031c00
,
0x00431025
,
0xacc20014
,
0x95240008
,
0x3202ffff
,
0x00821021
,
0x0262102a
,
0x14400002
,
0x02902823
,
0x00802821
,
0x8d220000
,
0x02058021
,
0xacc20000
,
0x8d220004
,
0x00c02021
,
0x26310010
,
0xac820004
,
0x30e2ffff
,
0xac800008
,
0xa485000e
,
0xac820010
,
0x24020305
,
0x0e000560
,
0xa482000c
,
0x3202ffff
,
0x0053102b
,
0x1440ffaf
,
0x3202ffff
,
0x0a00054c
,
0x00000000
,
0x8e420000
,
0x8e43fffc
,
0x0043102a
,
0x10400084
,
0x00000000
,
0x8e45fff0
,
0x8f644450
,
0x3c030800
,
0x8c6316e8
,
0x00051100
,
0x3c090800
,
0x01224821
,
0x8d291728
,
0x00041402
,
0x0062182b
,
0x14600008
,
0x00000000
,
0x3c030800
,
0x8c6316ec
,
0x8f624450
,
0x00021402
,
0x0062102b
,
0x1040fffc
,
0x00000000
,
0xaf764444
,
0x8f624444
,
0x00561024
,
0x10400006
,
0x00000000
,
0x3c038000
,
0x8f624444
,
0x00431024
,
0x1440fffd
,
0x00000000
,
0x8f624448
,
0x3046ffff
,
0x14c00005
,
0x00000000
,
0x8ee20000
,
0x24420001
,
0x0a000554
,
0xaee20000
,
0x9528000a
,
0x31020040
,
0x10400004
,
0x2407180c
,
0x8d22000c
,
0x2407188c
,
0xacc20018
,
0x31021000
,
0x10400004
,
0x34e32000
,
0x00081040
,
0x3042c000
,
0x00623825
,
0x00051900
,
0x3c020800
,
0x00431021
,
0x8c421730
,
0x3c010800
,
0x00230821
,
0x8c231734
,
0x00021500
,
0x00031c00
,
0x00431025
,
0xacc20014
,
0x3c030800
,
0x8c631704
,
0x95220008
,
0x00432023
,
0x3202ffff
,
0x3083ffff
,
0x00431021
,
0x02a2102a
,
0x14400002
,
0x03d02823
,
0x00802821
,
0x8e420000
,
0x30a4ffff
,
0x00441021
,
0xae420000
,
0xa4c5000e
,
0x8d220000
,
0xacc20000
,
0x8d220004
,
0x8e43fff4
,
0x00431021
,
0xacc20004
,
0x8e43fff4
,
0x95220008
,
0x00641821
,
0x0062102a
,
0x14400006
,
0x02058021
,
0x8e42fff0
,
0xae40fff4
,
0x24420001
,
0x0a000530
,
0xae42fff0
,
0xae43fff4
,
0xacc00008
,
0x3202ffff
,
0x10550003
,
0x31020004
,
0x10400006
,
0x24020305
,
0x31020080
,
0x54400001
,
0x34e70010
,
0x34e70020
,
0x24020905
,
0xa4c2000c
,
0x30e2ffff
,
0xacc20010
,
0x3c030800
,
0x8c63170c
,
0x3c020800
,
0x8c421710
,
0x54620004
,
0x3c02b49a
,
0x3c024b65
,
0x0a000548
,
0x34427654
,
0x344289ab
,
0xacc2001c
,
0x0e000560
,
0x00c02021
,
0x3202ffff
,
0x0055102b
,
0x1440ff7e
,
0x00000000
,
0x8e420000
,
0x8e43fffc
,
0x0043102a
,
0x1440ff1a
,
0x00000000
,
0x8fbf0034
,
0x8fbe0030
,
0x8fb7002c
,
0x8fb60028
,
0x8fb50024
,
0x8fb40020
,
0x8fb3001c
,
0x8fb20018
,
0x8fb10014
,
0x8fb00010
,
0x03e00008
,
0x27bd0038
,
0x27bdffe8
,
0xafbf0014
,
0xafb00010
,
0x8f624450
,
0x8f634410
,
0x0a00056f
,
0x00808021
,
0x8f626820
,
0x30422000
,
0x10400003
,
0x00000000
,
0x0e00025a
,
0x00002021
,
0x8f624450
,
0x8f634410
,
0x3042ffff
,
0x0043102b
,
0x1440fff5
,
0x00000000
,
0x8f630c14
,
0x3063000f
,
0x2c620002
,
0x1440000b
,
0x00000000
,
0x8f630c14
,
0x3c020800
,
0x8c4216b4
,
0x3063000f
,
0x24420001
,
0x3c010800
,
0xac2216b4
,
0x2c620002
,
0x1040fff7
,
0x00000000
,
0xaf705c18
,
0x8f625c10
,
0x30420002
,
0x10400009
,
0x00000000
,
0x8f626820
,
0x30422000
,
0x1040fff8
,
0x00000000
,
0x0e00025a
,
0x00002021
,
0x0a000582
,
0x00000000
,
0x8fbf0014
,
0x8fb00010
,
0x03e00008
,
0x27bd0018
,
0x00000000
,
0x00000000
};
u32
tg3TsoFwRodata
[]
=
{
0x4d61696e
,
0x43707542
,
0x00000000
,
0x00000000
,
0x74637073
,
0x6567496e
,
0x00000000
,
0x53774576
,
0x656e7430
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
};
#if 0 /* All zeros, dont eat up space with it. */
u32 tg3TsoFwData[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000
};
#endif
/* tp->lock is held. */
static
int
tg3_load_tso_firmware
(
struct
tg3
*
tp
)
{
struct
fw_info
info
;
int
err
,
i
;
info
.
text_base
=
TG3_TSO_FW_TEXT_ADDR
;
info
.
text_len
=
TG3_TSO_FW_TEXT_LEN
;
info
.
text_data
=
&
tg3TsoFwText
[
0
];
info
.
rodata_base
=
TG3_TSO_FW_RODATA_ADDR
;
info
.
rodata_len
=
TG3_TSO_FW_RODATA_LEN
;
info
.
rodata_data
=
&
tg3TsoFwRodata
[
0
];
info
.
data_base
=
TG3_TSO_FW_DATA_ADDR
;
info
.
data_len
=
TG3_TSO_FW_DATA_LEN
;
info
.
data_data
=
NULL
;
err
=
tg3_load_firmware_cpu
(
tp
,
TX_CPU_BASE
,
TX_CPU_SCRATCH_BASE
,
TX_CPU_SCRATCH_SIZE
,
&
info
);
if
(
err
)
return
err
;
/* Now startup only the TX cpu. */
tw32
(
TX_CPU_BASE
+
CPU_STATE
,
0xffffffff
);
tw32
(
TX_CPU_BASE
+
CPU_PC
,
TG3_TSO_FW_TEXT_ADDR
);
/* Flush posted writes. */
tr32
(
TX_CPU_BASE
+
CPU_PC
);
for
(
i
=
0
;
i
<
5
;
i
++
)
{
if
(
tr32
(
TX_CPU_BASE
+
CPU_PC
)
==
TG3_TSO_FW_TEXT_ADDR
)
break
;
tw32
(
TX_CPU_BASE
+
CPU_STATE
,
0xffffffff
);
tw32
(
TX_CPU_BASE
+
CPU_MODE
,
CPU_MODE_HALT
);
tw32
(
TX_CPU_BASE
+
CPU_PC
,
TG3_TSO_FW_TEXT_ADDR
);
/* Flush posted writes. */
tr32
(
TX_CPU_BASE
+
CPU_PC
);
udelay
(
1000
);
}
if
(
i
>=
5
)
{
printk
(
KERN_ERR
PFX
"tg3_load_tso_firmware fails for %s "
"to set TX CPU PC, is %08x should be %08x
\n
"
,
tp
->
dev
->
name
,
tr32
(
TX_CPU_BASE
+
CPU_PC
),
TG3_TSO_FW_TEXT_ADDR
);
return
-
ENODEV
;
}
tw32
(
TX_CPU_BASE
+
CPU_STATE
,
0xffffffff
);
tw32
(
TX_CPU_BASE
+
CPU_MODE
,
0x00000000
);
/* Flush posted writes. */
tr32
(
TX_CPU_BASE
+
CPU_MODE
);
return
0
;
}
#endif
/* NETIF_F_TSO */
/* tp->lock is held. */
static
void
__tg3_set_mac_addr
(
struct
tg3
*
tp
)
{
...
...
@@ -3826,6 +4193,12 @@ static int tg3_reset_hw(struct tg3 *tp)
return
err
;
}
#ifdef NETIF_F_TSO
err
=
tg3_load_tso_firmware
(
tp
);
if
(
err
)
return
err
;
#endif
tp
->
tx_mode
=
TX_MODE_ENABLE
;
tw32
(
MAC_TX_MODE
,
tp
->
tx_mode
);
tr32
(
MAC_TX_MODE
);
...
...
@@ -6180,6 +6553,9 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
dev
->
vlan_rx_register
=
tg3_vlan_rx_register
;
dev
->
vlan_rx_kill_vid
=
tg3_vlan_rx_kill_vid
;
#endif
#ifdef NETIF_F_TSO
dev
->
features
|=
NETIF_F_TSO
#endif
tp
=
dev
->
priv
;
tp
->
pdev
=
pdev
;
...
...
drivers/net/tg3.h
View file @
5ff107df
...
...
@@ -1415,6 +1415,7 @@ struct tg3_tx_buffer_desc {
u32
vlan_tag
;
#define TXD_VLAN_TAG_SHIFT 0
#define TXD_MSS_SHIFT 16
};
#define TXD_ADDR 0x00UL
/* 64-bit */
...
...
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