Commit 678eb675 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven

dt-bindings: clock: renesas: Document RZ/V2L SoC

Document the device tree binding for the Renesas RZ/V2L SoC.
Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220110134659.30424-5-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 9b621b6a
...@@ -4,13 +4,13 @@ ...@@ -4,13 +4,13 @@
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#" $id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode
maintainers: maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be> - Geert Uytterhoeven <geert+renesas@glider.be>
description: | description: |
On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module
Standby Mode share the same register block. Standby Mode share the same register block.
They provide the following functionalities: They provide the following functionalities:
...@@ -22,7 +22,9 @@ description: | ...@@ -22,7 +22,9 @@ description: |
properties: properties:
compatible: compatible:
const: renesas,r9a07g044-cpg # RZ/G2{L,LC} enum:
- renesas,r9a07g044-cpg # RZ/G2{L,LC}
- renesas,r9a07g054-cpg # RZ/V2L
reg: reg:
maxItems: 1 maxItems: 1
...@@ -40,9 +42,9 @@ properties: ...@@ -40,9 +42,9 @@ properties:
description: | description: |
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE" - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
and a core clock reference, as defined in and a core clock reference, as defined in
<dt-bindings/clock/r9a07g044-cpg.h> <dt-bindings/clock/r9a07g*-cpg.h>
- For module clocks, the two clock specifier cells must be "CPG_MOD" and - For module clocks, the two clock specifier cells must be "CPG_MOD" and
a module number, as defined in the <dt-bindings/clock/r9a07g044-cpg.h>. a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>.
const: 2 const: 2
'#power-domain-cells': '#power-domain-cells':
...@@ -56,7 +58,7 @@ properties: ...@@ -56,7 +58,7 @@ properties:
'#reset-cells': '#reset-cells':
description: description:
The single reset specifier cell must be the module number, as defined in The single reset specifier cell must be the module number, as defined in
the <dt-bindings/clock/r9a07g044-cpg.h>. the <dt-bindings/clock/r9a07g0*-cpg.h>.
const: 1 const: 1
required: required:
......
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