Commit 6ab9f69e authored by Rajendra Nayak's avatar Rajendra Nayak Committed by Paul Walmsley

ARM: OMAP2: clock: Add 24xx data using common struct clk

The patch is the output from a python script which converts
from the old OMAP clk format to COMMON clk format using a
JSON parser in between which was developed by Paul Walmsley.
Signed-off-by: default avatarRajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: replace omap2_init_clksel_parent() with
 omap2_clksel_find_parent_index(); reflowed macros; dropped 243x clkdev
 aliases in 242x file; added recalc_rate fn ptrs to APLL clocks;
 fixed some checkpatch warnings]
[mturquette@ti.com: removed deprecated variables from omap24x0_clk_init]
Signed-off-by: default avatarMike Turquette <mturquette@ti.com>
[paul@pwsan.com: fixed boot crash due to missing clock init code; added twl.fck
 alias; fix DPLL rate initialization; fix APLL clocks and virt_prcm_set
 initialization]
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent 99e7938d
This diff is collapsed.
This diff is collapsed.
...@@ -59,6 +59,7 @@ ...@@ -59,6 +59,7 @@
/* CM_CLKSEL_MPU */ /* CM_CLKSEL_MPU */
#define OMAP24XX_CLKSEL_MPU_SHIFT 0 #define OMAP24XX_CLKSEL_MPU_SHIFT 0
#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0) #define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0)
#define OMAP24XX_CLKSEL_MPU_WIDTH 5
/* CM_CLKSTCTRL_MPU */ /* CM_CLKSTCTRL_MPU */
#define OMAP24XX_AUTOSTATE_MPU_SHIFT 0 #define OMAP24XX_AUTOSTATE_MPU_SHIFT 0
...@@ -237,8 +238,10 @@ ...@@ -237,8 +238,10 @@
#define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8) #define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8)
#define OMAP24XX_CLKSEL_L4_SHIFT 5 #define OMAP24XX_CLKSEL_L4_SHIFT 5
#define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5) #define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5)
#define OMAP24XX_CLKSEL_L4_WIDTH 2
#define OMAP24XX_CLKSEL_L3_SHIFT 0 #define OMAP24XX_CLKSEL_L3_SHIFT 0
#define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0) #define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0)
#define OMAP24XX_CLKSEL_L3_WIDTH 5
/* CM_CLKSEL2_CORE */ /* CM_CLKSEL2_CORE */
#define OMAP24XX_CLKSEL_GPT12_SHIFT 22 #define OMAP24XX_CLKSEL_GPT12_SHIFT 22
...@@ -363,8 +366,10 @@ ...@@ -363,8 +366,10 @@
#define OMAP24XX_DPLL_DIV_MASK (0xf << 8) #define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
#define OMAP24XX_54M_SOURCE_SHIFT 5 #define OMAP24XX_54M_SOURCE_SHIFT 5
#define OMAP24XX_54M_SOURCE_MASK (1 << 5) #define OMAP24XX_54M_SOURCE_MASK (1 << 5)
#define OMAP24XX_54M_SOURCE_WIDTH 1
#define OMAP2430_96M_SOURCE_SHIFT 4 #define OMAP2430_96M_SOURCE_SHIFT 4
#define OMAP2430_96M_SOURCE_MASK (1 << 4) #define OMAP2430_96M_SOURCE_MASK (1 << 4)
#define OMAP2430_96M_SOURCE_WIDTH 1
#define OMAP24XX_48M_SOURCE_SHIFT 3 #define OMAP24XX_48M_SOURCE_SHIFT 3
#define OMAP24XX_48M_SOURCE_MASK (1 << 3) #define OMAP24XX_48M_SOURCE_MASK (1 << 3)
#define OMAP2430_ALTCLK_SOURCE_SHIFT 0 #define OMAP2430_ALTCLK_SOURCE_SHIFT 0
......
...@@ -107,12 +107,14 @@ ...@@ -107,12 +107,14 @@
#define OMAP2420_CLKOUT2_EN_MASK (1 << 15) #define OMAP2420_CLKOUT2_EN_MASK (1 << 15)
#define OMAP2420_CLKOUT2_DIV_SHIFT 11 #define OMAP2420_CLKOUT2_DIV_SHIFT 11
#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11) #define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11)
#define OMAP2420_CLKOUT2_DIV_WIDTH 3
#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8 #define OMAP2420_CLKOUT2_SOURCE_SHIFT 8
#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8) #define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8)
#define OMAP24XX_CLKOUT_EN_SHIFT 7 #define OMAP24XX_CLKOUT_EN_SHIFT 7
#define OMAP24XX_CLKOUT_EN_MASK (1 << 7) #define OMAP24XX_CLKOUT_EN_MASK (1 << 7)
#define OMAP24XX_CLKOUT_DIV_SHIFT 3 #define OMAP24XX_CLKOUT_DIV_SHIFT 3
#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3) #define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3)
#define OMAP24XX_CLKOUT_DIV_WIDTH 3
#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0 #define OMAP24XX_CLKOUT_SOURCE_SHIFT 0
#define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0) #define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0)
......
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