Commit 6f80fcdf authored by Jakub Kicinski's avatar Jakub Kicinski

Merge branch 'mlxsw-use-page-pool-for-rx-buffers-allocation'

Petr Machata says:

====================
mlxsw: Use page pool for Rx buffers allocation

Amit Cohen  writes:

After using NAPI to process events from hardware, the next step is to
use page pool for Rx buffers allocation, which is also enhances
performance.

To simplify this change, first use page pool to allocate one continuous
buffer for each packet, later memory consumption can be improved by using
fragmented buffers.

This set significantly enhances mlxsw driver performance, CPU can handle
about 370% of the packets per second it previously handled.

The next planned improvement is using XDP to optimize telemetry.

Patch set overview:
Patches #1-#2 are small preparations for page pool usage
Patch #3 initializes page pool, but do not use it
Patch #4 converts the driver to use page pool for buffers allocations
Patch #5 is an optimization for buffer access
Patch #6 cleans up an unused structure
Patch #7 uses napi_consume_skb() as part of Tx completion
====================

Link: https://lore.kernel.org/r/cover.1718709196.git.petrm@nvidia.comSigned-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 89f5e607 d94ae641
...@@ -33,6 +33,7 @@ config MLXSW_CORE_THERMAL ...@@ -33,6 +33,7 @@ config MLXSW_CORE_THERMAL
config MLXSW_PCI config MLXSW_PCI
tristate "PCI bus implementation for Mellanox Technologies Switch ASICs" tristate "PCI bus implementation for Mellanox Technologies Switch ASICs"
depends on PCI && HAS_IOMEM && MLXSW_CORE depends on PCI && HAS_IOMEM && MLXSW_CORE
select PAGE_POOL
default m default m
help help
This is PCI bus implementation for Mellanox Technologies Switch ASICs. This is PCI bus implementation for Mellanox Technologies Switch ASICs.
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