Commit 7c3b54a5 authored by Olof Johansson's avatar Olof Johansson

Merge tag 'davinci-for-v4.13/soc' of...

Merge tag 'davinci-for-v4.13/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc

DaVinci SoC support updates enhancing DSP remoteproc
support for DA850 SoC. This lays the foundation for
DT conversion of da8xx remoteproc driver.

* tag 'davinci-for-v4.13/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
  ARM: davinci: da8xx: Add DSP internal RAM memories as IOMEM resources
  ARM: davinci: da8xx: Add names to DSP IOMEM resources
  ARM: davinci: da8xx: Create DSP device only when assigned memory
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 5ed02dbb 14ff86bc
...@@ -789,15 +789,35 @@ int __init da850_register_mmcsd1(struct davinci_mmc_config *config) ...@@ -789,15 +789,35 @@ int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
static struct resource da8xx_rproc_resources[] = { static struct resource da8xx_rproc_resources[] = {
{ /* DSP boot address */ { /* DSP boot address */
.name = "host1cfg",
.start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG, .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
.end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3, .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
{ /* DSP interrupt registers */ { /* DSP interrupt registers */
.name = "chipsig",
.start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG, .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
.end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7, .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
{ /* DSP L2 RAM */
.name = "l2sram",
.start = DA8XX_DSP_L2_RAM_BASE,
.end = DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1,
.flags = IORESOURCE_MEM,
},
{ /* DSP L1P RAM */
.name = "l1pram",
.start = DA8XX_DSP_L1P_RAM_BASE,
.end = DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1,
.flags = IORESOURCE_MEM,
},
{ /* DSP L1D RAM */
.name = "l1dram",
.start = DA8XX_DSP_L1D_RAM_BASE,
.end = DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1,
.flags = IORESOURCE_MEM,
},
{ /* dsp irq */ { /* dsp irq */
.start = IRQ_DA8XX_CHIPINT0, .start = IRQ_DA8XX_CHIPINT0,
.end = IRQ_DA8XX_CHIPINT0, .end = IRQ_DA8XX_CHIPINT0,
...@@ -814,6 +834,8 @@ static struct platform_device da8xx_dsp = { ...@@ -814,6 +834,8 @@ static struct platform_device da8xx_dsp = {
.resource = da8xx_rproc_resources, .resource = da8xx_rproc_resources,
}; };
static bool rproc_mem_inited __initdata;
#if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC) #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
static phys_addr_t rproc_base __initdata; static phys_addr_t rproc_base __initdata;
...@@ -852,6 +874,8 @@ void __init da8xx_rproc_reserve_cma(void) ...@@ -852,6 +874,8 @@ void __init da8xx_rproc_reserve_cma(void)
ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0); ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0);
if (ret) if (ret)
pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret); pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret);
else
rproc_mem_inited = true;
} }
#else #else
...@@ -866,6 +890,12 @@ int __init da8xx_register_rproc(void) ...@@ -866,6 +890,12 @@ int __init da8xx_register_rproc(void)
{ {
int ret; int ret;
if (!rproc_mem_inited) {
pr_warn("%s: memory not reserved for DSP, not registering DSP device\n",
__func__);
return -ENOMEM;
}
ret = platform_device_register(&da8xx_dsp); ret = platform_device_register(&da8xx_dsp);
if (ret) if (ret)
pr_err("%s: can't register DSP device: %d\n", __func__, ret); pr_err("%s: can't register DSP device: %d\n", __func__, ret);
......
...@@ -75,6 +75,11 @@ extern unsigned int da850_max_speed; ...@@ -75,6 +75,11 @@ extern unsigned int da850_max_speed;
#define DA8XX_VPIF_BASE 0x01e17000 #define DA8XX_VPIF_BASE 0x01e17000
#define DA8XX_GPIO_BASE 0x01e26000 #define DA8XX_GPIO_BASE 0x01e26000
#define DA8XX_PSC1_BASE 0x01e27000 #define DA8XX_PSC1_BASE 0x01e27000
#define DA8XX_DSP_L2_RAM_BASE 0x11800000
#define DA8XX_DSP_L1P_RAM_BASE (DA8XX_DSP_L2_RAM_BASE + 0x600000)
#define DA8XX_DSP_L1D_RAM_BASE (DA8XX_DSP_L2_RAM_BASE + 0x700000)
#define DA8XX_AEMIF_CS2_BASE 0x60000000 #define DA8XX_AEMIF_CS2_BASE 0x60000000
#define DA8XX_AEMIF_CS3_BASE 0x62000000 #define DA8XX_AEMIF_CS3_BASE 0x62000000
#define DA8XX_AEMIF_CTL_BASE 0x68000000 #define DA8XX_AEMIF_CTL_BASE 0x68000000
......
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