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Commit 7c856522 authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/clk: implement power state and engine clock control in core 

User control of this has been hard-coded as disabled for now.
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent c9c0ccae
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Showing with 2590 additions and 65 deletions
drivers/gpu/drm/nouveau/Makefile
View file @ 7c856522
......@@ -47,16 +47,20 @@ nouveau-y += core/subdev/bios/therm.o
nouveau-y += core/subdev/bios/vmap.o
nouveau-y += core/subdev/bios/volt.o
nouveau-y += core/subdev/bios/xpio.o
nouveau-y += core/subdev/bus/hwsq.o
nouveau-y += core/subdev/bus/nv04.o
nouveau-y += core/subdev/bus/nv31.o
nouveau-y += core/subdev/bus/nv50.o
nouveau-y += core/subdev/bus/nv94.o
nouveau-y += core/subdev/bus/nvc0.o
nouveau-y += core/subdev/clock/base.o
nouveau-y += core/subdev/clock/nv04.o
nouveau-y += core/subdev/clock/nv40.o
nouveau-y += core/subdev/clock/nv50.o
nouveau-y += core/subdev/clock/nv84.o
nouveau-y += core/subdev/clock/nva3.o
nouveau-y += core/subdev/clock/nvc0.o
nouveau-y += core/subdev/clock/nve0.o
nouveau-y += core/subdev/clock/pllnv04.o
nouveau-y += core/subdev/clock/pllnva3.o
nouveau-y += core/subdev/devinit/base.o
......
drivers/gpu/drm/nouveau/core/core/option.c
View file @ 7c856522
......@@ -25,15 +25,6 @@
#include <core/option.h>
#include <core/debug.h>
/* compares unterminated string 'str' with zero-terminated string 'cmp' */
static inline int
strncasecmpz(const char *str, const char *cmp, size_t len)
{
if (strlen(cmp) != len)
return len;
return strncasecmp(str, cmp, len);
}
const char *
nouveau_stropt(const char *optstr, const char *opt, int *arglen)
{
......
drivers/gpu/drm/nouveau/core/engine/device/nv50.c
View file @ 7c856522
......@@ -62,7 +62,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
......@@ -87,7 +87,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
......@@ -115,7 +115,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
......@@ -143,7 +143,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
......@@ -171,7 +171,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
......@@ -199,7 +199,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
......@@ -227,7 +227,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
......@@ -255,7 +255,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
......@@ -283,7 +283,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
......@@ -311,7 +311,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
......
drivers/gpu/drm/nouveau/core/engine/device/nve0.c
View file @ 7c856522
......@@ -62,7 +62,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
......@@ -95,7 +95,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
......@@ -128,7 +128,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
......@@ -161,7 +161,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
......@@ -196,7 +196,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
......
drivers/gpu/drm/nouveau/core/include/core/option.h
View file @ 7c856522
......@@ -8,4 +8,13 @@ bool nouveau_boolopt(const char *optstr, const char *opt, bool value);
int nouveau_dbgopt(const char *optstr, const char *sub);
/* compares unterminated string 'str' with zero-terminated string 'cmp' */
static inline int
strncasecmpz(const char *str, const char *cmp, size_t len)
{
if (strlen(cmp) != len)
return len;
return strncasecmp(str, cmp, len);
}
#endif
drivers/gpu/drm/nouveau/core/include/subdev/clock.h
View file @ 7c856522
......@@ -7,9 +7,78 @@
struct nouveau_pll_vals;
struct nvbios_pll;
enum nv_clk_src {
nv_clk_src_crystal,
nv_clk_src_href,
nv_clk_src_hclk,
nv_clk_src_hclkm3,
nv_clk_src_hclkm3d2,
nv_clk_src_host,
nv_clk_src_sppll0,
nv_clk_src_sppll1,
nv_clk_src_mpllsrcref,
nv_clk_src_mpllsrc,
nv_clk_src_mpll,
nv_clk_src_mdiv,
nv_clk_src_core,
nv_clk_src_shader,
nv_clk_src_mem,
nv_clk_src_gpc,
nv_clk_src_rop,
nv_clk_src_hubk01,
nv_clk_src_hubk06,
nv_clk_src_hubk07,
nv_clk_src_copy,
nv_clk_src_daemon,
nv_clk_src_disp,
nv_clk_src_vdec,
nv_clk_src_dom6,
nv_clk_src_max,
};
struct nouveau_cstate {
struct list_head head;
u8 voltage;
u32 domain[nv_clk_src_max];
};
struct nouveau_pstate {
struct list_head head;
struct list_head list; /* c-states */
struct nouveau_cstate base;
u8 pstate;
u8 fanspeed;
};
struct nouveau_clock {
struct nouveau_subdev base;
struct nouveau_clocks *domains;
struct nouveau_pstate bstate;
struct list_head states;
int state_nr;
int pstate; /* current */
int ustate; /* user-requested (-1 disabled, -2 perfmon) */
int astate; /* perfmon adjustment (base) */
int tstate; /* thermal adjustment (max-) */
int dstate; /* display adjustment (min+) */
int (*read)(struct nouveau_clock *, enum nv_clk_src);
int (*calc)(struct nouveau_clock *, struct nouveau_cstate *);
int (*prog)(struct nouveau_clock *);
void (*tidy)(struct nouveau_clock *);
/*XXX: die, these are here *only* to support the completely
* bat-shit insane what-was-nouveau_hw.c code
*/
......@@ -25,27 +94,42 @@ nouveau_clock(void *obj)
return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_CLOCK];
}
#define nouveau_clock_create(p,e,o,d) \
nouveau_subdev_create((p), (e), (o), 0, "CLOCK", "clock", d)
#define nouveau_clock_destroy(p) \
nouveau_subdev_destroy(&(p)->base)
#define nouveau_clock_init(p) \
nouveau_subdev_init(&(p)->base)
struct nouveau_clocks {
enum nv_clk_src name;
u8 bios; /* 0xff for none */
#define NVKM_CLK_DOM_FLAG_CORE 0x01
u8 flags;
const char *mname;
int mdiv;
};
#define nouveau_clock_create(p,e,o,i,d) \
nouveau_clock_create_((p), (e), (o), (i), sizeof(**d), (void **)d)
#define nouveau_clock_destroy(p) ({ \
struct nouveau_clock *clk = (p); \
_nouveau_clock_dtor(nv_object(clk)); \
})
#define nouveau_clock_init(p) ({ \
struct nouveau_clock *clk = (p); \
_nouveau_clock_init(nv_object(clk)); \
})
#define nouveau_clock_fini(p,s) \
nouveau_subdev_fini(&(p)->base, (s))
int nouveau_clock_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32, int, void **);
#define _nouveau_clock_dtor _nouveau_subdev_dtor
#define _nouveau_clock_init _nouveau_subdev_init
struct nouveau_oclass *,
struct nouveau_clocks *, int, void **);
void _nouveau_clock_dtor(struct nouveau_object *);
int _nouveau_clock_init(struct nouveau_object *);
#define _nouveau_clock_fini _nouveau_subdev_fini
extern struct nouveau_oclass nv04_clock_oclass;
extern struct nouveau_oclass nv40_clock_oclass;
extern struct nouveau_oclass nv50_clock_oclass;
extern struct nouveau_oclass *nv50_clock_oclass;
extern struct nouveau_oclass *nv84_clock_oclass;
extern struct nouveau_oclass nva3_clock_oclass;
extern struct nouveau_oclass nvc0_clock_oclass;
extern struct nouveau_oclass nve0_clock_oclass;
int nv04_clock_pll_set(struct nouveau_clock *, u32 type, u32 freq);
int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
......@@ -55,4 +139,9 @@ int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1,
int nva3_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
int clk, struct nouveau_pll_vals *);
int nouveau_clock_ustate(struct nouveau_clock *, int req);
int nouveau_clock_astate(struct nouveau_clock *, int req, int rel);
int nouveau_clock_dstate(struct nouveau_clock *, int req, int rel);
int nouveau_clock_tstate(struct nouveau_clock *, int req, int rel);
#endif
drivers/gpu/drm/nouveau/core/include/subdev/fb.h
View file @ 7c856522
......@@ -125,6 +125,9 @@ struct nouveau_ram {
int (*get)(struct nouveau_fb *, u64 size, u32 align,
u32 size_nc, u32 type, struct nouveau_mem **);
void (*put)(struct nouveau_fb *, struct nouveau_mem **);
int (*calc)(struct nouveau_fb *, u32 freq);
int (*prog)(struct nouveau_fb *);
void (*tidy)(struct nouveau_fb *);
};
#endif
drivers/gpu/drm/nouveau/core/subdev/clock/base.c 0 → 100644
View file @ 7c856522
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <core/option.h>
#include <subdev/clock.h>
#include <subdev/therm.h>
#include <subdev/volt.h>
#include <subdev/fb.h>
#include <subdev/bios.h>
#include <subdev/bios/boost.h>
#include <subdev/bios/cstep.h>
#include <subdev/bios/perf.h>
/******************************************************************************
* misc
*****************************************************************************/
static u32
nouveau_clock_adjust(struct nouveau_clock *clk, bool adjust,
u8 pstate, u8 domain, u32 input)
{
struct nouveau_bios *bios = nouveau_bios(clk);
struct nvbios_boostE boostE;
u8 ver, hdr, cnt, len;
u16 data;
data = nvbios_boostEm(bios, pstate, &ver, &hdr, &cnt, &len, &boostE);
if (data) {
struct nvbios_boostS boostS;
u8 idx = 0, sver, shdr;
u16 subd;
input = max(boostE.min, input);
input = min(boostE.max, input);
do {
sver = ver;
shdr = hdr;
subd = nvbios_boostSp(bios, idx++, data, &sver, &shdr,
cnt, len, &boostS);
if (subd && boostS.domain == domain) {
if (adjust)
input = input * boostS.percent / 100;
input = max(boostS.min, input);
input = min(boostS.max, input);
break;
}
} while (subd);
}
return input;
}
/******************************************************************************
* C-States
*****************************************************************************/
static int
nouveau_cstate_prog(struct nouveau_clock *clk,
struct nouveau_pstate *pstate, int cstatei)
{
struct nouveau_therm *ptherm = nouveau_therm(clk);
struct nouveau_volt *volt = nouveau_volt(clk);
struct nouveau_cstate *cstate;
int ret;
if (!list_empty(&pstate->list)) {
cstate = list_entry(pstate->list.prev, typeof(*cstate), head);
} else {
cstate = &pstate->base;
}
ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, +1);
if (ret && ret != -ENODEV) {
nv_error(clk, "failed to raise fan speed: %d\n", ret);
return ret;
}
ret = volt->set_id(volt, cstate->voltage, +1);
if (ret && ret != -ENODEV) {
nv_error(clk, "failed to raise voltage: %d\n", ret);
return ret;
}
ret = clk->calc(clk, cstate);
if (ret == 0) {
ret = clk->prog(clk);
clk->tidy(clk);
}
ret = volt->set_id(volt, cstate->voltage, -1);
if (ret && ret != -ENODEV)
nv_error(clk, "failed to lower voltage: %d\n", ret);
ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, -1);
if (ret && ret != -ENODEV)
nv_error(clk, "failed to lower fan speed: %d\n", ret);
return 0;
}
static void
nouveau_cstate_del(struct nouveau_cstate *cstate)
{
list_del(&cstate->head);
kfree(cstate);
}
static int
nouveau_cstate_new(struct nouveau_clock *clk, int idx,
struct nouveau_pstate *pstate)
{
struct nouveau_bios *bios = nouveau_bios(clk);
struct nouveau_clocks *domain = clk->domains;
struct nouveau_cstate *cstate = NULL;
struct nvbios_cstepX cstepX;
u8 ver, hdr;
u16 data;
data = nvbios_cstepXp(bios, idx, &ver, &hdr, &cstepX);
if (!data)
return -ENOENT;
cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
if (!cstate)
return -ENOMEM;
*cstate = pstate->base;
cstate->voltage = cstepX.voltage;
while (domain && domain->name != nv_clk_src_max) {
if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
u32 freq = nouveau_clock_adjust(clk, true,
pstate->pstate,
domain->bios,
cstepX.freq);
cstate->domain[domain->name] = freq;
}
domain++;
}
list_add(&cstate->head, &pstate->list);
return 0;
}
/******************************************************************************
* P-States
*****************************************************************************/
static int
nouveau_pstate_prog(struct nouveau_clock *clk, int pstatei)
{
struct nouveau_fb *pfb = nouveau_fb(clk);
struct nouveau_pstate *pstate;
int ret, idx = 0;
list_for_each_entry(pstate, &clk->states, head) {
if (idx++ == pstatei)
break;
}
nv_debug(clk, "setting performance state %d\n", pstatei);
clk->pstate = pstatei;
if (pfb->ram->calc) {
ret = pfb->ram->calc(pfb, pstate->base.domain[nv_clk_src_mem]);
if (ret == 0)
ret = pfb->ram->prog(pfb);
pfb->ram->tidy(pfb);
}
return nouveau_cstate_prog(clk, pstate, 0);
}
static int
nouveau_pstate_calc(struct nouveau_clock *clk)
{
int pstate, ret = 0;
nv_trace(clk, "P %d U %d A %d T %d D %d\n", clk->pstate,
clk->ustate, clk->astate, clk->tstate, clk->dstate);
if (clk->state_nr && clk->ustate != -1) {
pstate = (clk->ustate < 0) ? clk->astate : clk->ustate;
pstate = min(pstate, clk->state_nr - 1 - clk->tstate);
pstate = max(pstate, clk->dstate);
} else {
pstate = clk->pstate = -1;
}
nv_trace(clk, "-> %d\n", pstate);
if (pstate != clk->pstate)
ret = nouveau_pstate_prog(clk, pstate);
return ret;
}
static void
nouveau_pstate_info(struct nouveau_clock *clk, struct nouveau_pstate *pstate)
{
struct nouveau_clocks *clock = clk->domains - 1;
struct nouveau_cstate *cstate;
char info[3][32] = { "", "", "" };
char name[4] = "--";
int i = -1;
if (pstate->pstate != 0xff)
snprintf(name, sizeof(name), "%02x", pstate->pstate);
while ((++clock)->name != nv_clk_src_max) {
u32 lo = pstate->base.domain[clock->name];
u32 hi = lo;
if (hi == 0)
continue;
nv_debug(clk, "%02x: %10d KHz\n", clock->name, lo);
list_for_each_entry(cstate, &pstate->list, head) {
u32 freq = cstate->domain[clock->name];
lo = min(lo, freq);
hi = max(hi, freq);
nv_debug(clk, "%10d KHz\n", freq);
}
if (clock->mname && ++i < ARRAY_SIZE(info)) {
lo /= clock->mdiv;
hi /= clock->mdiv;
if (lo == hi) {
snprintf(info[i], sizeof(info[i]), "%s %d MHz",
clock->mname, lo);
} else {
snprintf(info[i], sizeof(info[i]),
"%s %d-%d MHz", clock->mname, lo, hi);
}
}
}
nv_info(clk, "%s: %s %s %s\n", name, info[0], info[1], info[2]);
}
static void
nouveau_pstate_del(struct nouveau_pstate *pstate)
{
struct nouveau_cstate *cstate, *temp;
list_for_each_entry_safe(cstate, temp, &pstate->list, head) {
nouveau_cstate_del(cstate);
}
list_del(&pstate->head);
kfree(pstate);
}
static int
nouveau_pstate_new(struct nouveau_clock *clk, int idx)
{
struct nouveau_bios *bios = nouveau_bios(clk);
struct nouveau_clocks *domain = clk->domains - 1;
struct nouveau_pstate *pstate;
struct nouveau_cstate *cstate;
struct nvbios_cstepE cstepE;
struct nvbios_perfE perfE;
u8 ver, hdr, cnt, len;
u16 data;
data = nvbios_perfEp(bios, idx, &ver, &hdr, &cnt, &len, &perfE);
if (!data)
return -EINVAL;
if (perfE.pstate == 0xff)
return 0;
pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
cstate = &pstate->base;
if (!pstate)
return -ENOMEM;
INIT_LIST_HEAD(&pstate->list);
pstate->pstate = perfE.pstate;
pstate->fanspeed = perfE.fanspeed;
cstate->voltage = perfE.voltage;
cstate->domain[nv_clk_src_core] = perfE.core;
cstate->domain[nv_clk_src_shader] = perfE.shader;
cstate->domain[nv_clk_src_mem] = perfE.memory;
cstate->domain[nv_clk_src_vdec] = perfE.vdec;
cstate->domain[nv_clk_src_dom6] = perfE.disp;
while (ver >= 0x40 && (++domain)->name != nv_clk_src_max) {
struct nvbios_perfS perfS;
u8 sver = ver, shdr = hdr;
u32 perfSe = nvbios_perfSp(bios, data, domain->bios,
&sver, &shdr, cnt, len, &perfS);
if (perfSe == 0 || sver != 0x40)
continue;
if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
perfS.v40.freq = nouveau_clock_adjust(clk, false,
pstate->pstate,
domain->bios,
perfS.v40.freq);
}
cstate->domain[domain->name] = perfS.v40.freq;
}
data = nvbios_cstepEm(bios, pstate->pstate, &ver, &hdr, &cstepE);
if (data) {
int idx = cstepE.index;
do {
nouveau_cstate_new(clk, idx, pstate);
} while(idx--);
}
nouveau_pstate_info(clk, pstate);
list_add_tail(&pstate->head, &clk->states);
clk->state_nr++;
return 0;
}
/******************************************************************************
* Adjustment triggers
*****************************************************************************/
static int
nouveau_clock_ustate_update(struct nouveau_clock *clk, int req)
{
struct nouveau_pstate *pstate;
int i = 0;
/* YKW repellant */
return -ENOSYS;
if (req != -1 && req != -2) {
list_for_each_entry(pstate, &clk->states, head) {
if (pstate->pstate == req)
break;
i++;
}
if (pstate->pstate != req)
return -EINVAL;
req = i;
}
clk->ustate = req;
return 0;
}
int
nouveau_clock_ustate(struct nouveau_clock *clk, int req)
{
int ret = nouveau_clock_ustate_update(clk, req);
if (ret)
return ret;
return nouveau_pstate_calc(clk);
}
int
nouveau_clock_astate(struct nouveau_clock *clk, int req, int rel)
{
if (!rel) clk->astate = req;
if ( rel) clk->astate += rel;
clk->astate = min(clk->astate, clk->state_nr - 1);
clk->astate = max(clk->astate, 0);
return nouveau_pstate_calc(clk);
}
int
nouveau_clock_tstate(struct nouveau_clock *clk, int req, int rel)
{
if (!rel) clk->tstate = req;
if ( rel) clk->tstate += rel;
clk->tstate = min(clk->tstate, 0);
clk->tstate = max(clk->tstate, -(clk->state_nr - 1));
return nouveau_pstate_calc(clk);
}
int
nouveau_clock_dstate(struct nouveau_clock *clk, int req, int rel)
{
if (!rel) clk->dstate = req;
if ( rel) clk->dstate += rel;
clk->dstate = min(clk->dstate, clk->state_nr - 1);
clk->dstate = max(clk->dstate, 0);
return nouveau_pstate_calc(clk);
}
/******************************************************************************
* subdev base class implementation
*****************************************************************************/
int
_nouveau_clock_init(struct nouveau_object *object)
{
struct nouveau_clock *clk = (void *)object;
struct nouveau_clocks *clock = clk->domains;
int ret;
memset(&clk->bstate, 0x00, sizeof(clk->bstate));
INIT_LIST_HEAD(&clk->bstate.list);
clk->bstate.pstate = 0xff;
while (clock->name != nv_clk_src_max) {
ret = clk->read(clk, clock->name);
if (ret < 0) {
nv_error(clk, "%02x freq unknown\n", clock->name);
return ret;
}
clk->bstate.base.domain[clock->name] = ret;
clock++;
}
nouveau_pstate_info(clk, &clk->bstate);
clk->astate = clk->state_nr - 1;
clk->tstate = 0;
clk->dstate = 0;
clk->pstate = -1;
nouveau_pstate_calc(clk);
return 0;
}
void
_nouveau_clock_dtor(struct nouveau_object *object)
{
struct nouveau_clock *clk = (void *)object;
struct nouveau_pstate *pstate, *temp;
list_for_each_entry_safe(pstate, temp, &clk->states, head) {
nouveau_pstate_del(pstate);
}
nouveau_subdev_destroy(&clk->base);
}
int
nouveau_clock_create_(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass,
struct nouveau_clocks *clocks,
int length, void **object)
{
struct nouveau_device *device = nv_device(parent);
struct nouveau_clock *clk;
int ret, idx, arglen;
const char *mode;
ret = nouveau_subdev_create_(parent, engine, oclass, 0, "CLK",
"clock", length, object);
clk = *object;
if (ret)
return ret;
INIT_LIST_HEAD(&clk->states);
clk->domains = clocks;
clk->ustate = -1;
idx = 0;
do {
ret = nouveau_pstate_new(clk, idx++);
} while (ret == 0);
mode = nouveau_stropt(device->cfgopt, "NvClkMode", &arglen);
if (mode) {
if (!strncasecmpz(mode, "disabled", arglen)) {
clk->ustate = -1;
} else {
char save = mode[arglen];
long v;
((char *)mode)[arglen] = '\0';
if (!kstrtol(mode, 0, &v))
nouveau_clock_ustate_update(clk, v);
((char *)mode)[arglen] = save;
}
}
return 0;
}
drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c
View file @ 7c856522
......@@ -77,7 +77,7 @@ nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nv04_clock_priv *priv;
int ret;
ret = nouveau_clock_create(parent, engine, oclass, &priv);
ret = nouveau_clock_create(parent, engine, oclass, NULL, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
......
drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c
View file @ 7c856522
......@@ -23,11 +23,188 @@
*/
#include <subdev/clock.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include "pll.h"
struct nv40_clock_priv {
struct nouveau_clock base;
u32 ctrl;
u32 npll_ctrl;
u32 npll_coef;
u32 spll;
};
static struct nouveau_clocks
nv40_domain[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
{ nv_clk_src_core , 0xff, 0, "core", 1000 },
{ nv_clk_src_shader , 0xff, 0, "shader", 1000 },
{ nv_clk_src_mem , 0xff, 0, "memory", 1000 },
{ nv_clk_src_max }
};
static u32
read_pll_1(struct nv40_clock_priv *priv, u32 reg)
{
u32 ctrl = nv_rd32(priv, reg + 0x00);
int P = (ctrl & 0x00070000) >> 16;
int N = (ctrl & 0x0000ff00) >> 8;
int M = (ctrl & 0x000000ff) >> 0;
u32 ref = 27000, clk = 0;
if (ctrl & 0x80000000)
clk = ref * N / M;
return clk >> P;
}
static u32
read_pll_2(struct nv40_clock_priv *priv, u32 reg)
{
u32 ctrl = nv_rd32(priv, reg + 0x00);
u32 coef = nv_rd32(priv, reg + 0x04);
int N2 = (coef & 0xff000000) >> 24;
int M2 = (coef & 0x00ff0000) >> 16;
int N1 = (coef & 0x0000ff00) >> 8;
int M1 = (coef & 0x000000ff) >> 0;
int P = (ctrl & 0x00070000) >> 16;
u32 ref = 27000, clk = 0;
if ((ctrl & 0x80000000) && M1) {
clk = ref * N1 / M1;
if ((ctrl & 0x40000100) == 0x40000000) {
if (M2)
clk = clk * N2 / M2;
else
clk = 0;
}
}
return clk >> P;
}
static u32
read_clk(struct nv40_clock_priv *priv, u32 src)
{
switch (src) {
case 3:
return read_pll_2(priv, 0x004000);
case 2:
return read_pll_1(priv, 0x004008);
default:
break;
}
return 0;
}
static int
nv40_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
{
struct nv40_clock_priv *priv = (void *)clk;
u32 mast = nv_rd32(priv, 0x00c040);
switch (src) {
case nv_clk_src_crystal:
return nv_device(priv)->crystal;
case nv_clk_src_href:
return 100000; /*XXX: PCIE/AGP differ*/
case nv_clk_src_core:
return read_clk(priv, (mast & 0x00000003) >> 0);
case nv_clk_src_shader:
return read_clk(priv, (mast & 0x00000030) >> 4);
case nv_clk_src_mem:
return read_pll_2(priv, 0x4020);
default:
break;
}
nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast);
return -EINVAL;
}
static int
nv40_clock_calc_pll(struct nv40_clock_priv *priv, u32 reg, u32 clk,
int *N1, int *M1, int *N2, int *M2, int *log2P)
{
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvbios_pll pll;
int ret;
ret = nvbios_pll_parse(bios, reg, &pll);
if (ret)
return ret;
if (clk < pll.vco1.max_freq)
pll.vco2.max_freq = 0;
ret = nv04_pll_calc(nv_subdev(priv), &pll, clk, N1, M1, N2, M2, log2P);
if (ret == 0)
return -ERANGE;
return ret;
}
static int
nv40_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
{
struct nv40_clock_priv *priv = (void *)clk;
int gclk = cstate->domain[nv_clk_src_core];
int sclk = cstate->domain[nv_clk_src_shader];
int N1, M1, N2, M2, log2P;
int ret;
/* core/geometric clock */
ret = nv40_clock_calc_pll(priv, 0x004000, gclk,
&N1, &M1, &N2, &M2, &log2P);
if (ret < 0)
return ret;
if (N2 == M2) {
priv->npll_ctrl = 0x80000100 | (log2P << 16);
priv->npll_coef = (N1 << 8) | M1;
} else {
priv->npll_ctrl = 0xc0000000 | (log2P << 16);
priv->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
}
/* use the second pll for shader/rop clock, if it differs from core */
if (sclk && sclk != gclk) {
ret = nv40_clock_calc_pll(priv, 0x004008, sclk,
&N1, &M1, NULL, NULL, &log2P);
if (ret < 0)
return ret;
priv->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1;
priv->ctrl = 0x00000223;
} else {
priv->spll = 0x00000000;
priv->ctrl = 0x00000333;
}
return 0;
}
static int
nv40_clock_prog(struct nouveau_clock *clk)
{
struct nv40_clock_priv *priv = (void *)clk;
nv_mask(priv, 0x00c040, 0x00000333, 0x00000000);
nv_wr32(priv, 0x004004, priv->npll_coef);
nv_mask(priv, 0x004000, 0xc0070100, priv->npll_ctrl);
nv_mask(priv, 0x004008, 0xc007ffff, priv->spll);
mdelay(5);
nv_mask(priv, 0x00c040, 0x00000333, priv->ctrl);
return 0;
}
static void
nv40_clock_tidy(struct nouveau_clock *clk)
{
}
static int
nv40_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
......@@ -36,13 +213,17 @@ nv40_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nv40_clock_priv *priv;
int ret;
ret = nouveau_clock_create(parent, engine, oclass, &priv);
ret = nouveau_clock_create(parent, engine, oclass, nv40_domain, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->base.pll_calc = nv04_clock_pll_calc;
priv->base.pll_prog = nv04_clock_pll_prog;
priv->base.read = nv40_clock_read;
priv->base.calc = nv40_clock_calc;
priv->base.prog = nv40_clock_prog;
priv->base.tidy = nv40_clock_tidy;
return 0;
}
......
drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c
View file @ 7c856522
......@@ -22,40 +22,538 @@
* Authors: Ben Skeggs
*/
#include <subdev/clock.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include "nv50.h"
#include "pll.h"
#include "seq.h"
struct nv50_clock_priv {
struct nouveau_clock base;
};
static u32
read_div(struct nv50_clock_priv *priv)
{
switch (nv_device(priv)->chipset) {
case 0x50: /* it exists, but only has bit 31, not the dividers.. */
case 0x84:
case 0x86:
case 0x98:
case 0xa0:
return nv_rd32(priv, 0x004700);
case 0x92:
case 0x94:
case 0x96:
return nv_rd32(priv, 0x004800);
default:
return 0x00000000;
}
}
static u32
read_pll_src(struct nv50_clock_priv *priv, u32 base)
{
struct nouveau_clock *clk = &priv->base;
u32 coef, ref = clk->read(clk, nv_clk_src_crystal);
u32 rsel = nv_rd32(priv, 0x00e18c);
int P, N, M, id;
switch (nv_device(priv)->chipset) {
case 0x50:
case 0xa0:
switch (base) {
case 0x4020:
case 0x4028: id = !!(rsel & 0x00000004); break;
case 0x4008: id = !!(rsel & 0x00000008); break;
case 0x4030: id = 0; break;
default:
nv_error(priv, "ref: bad pll 0x%06x\n", base);
return 0;
}
coef = nv_rd32(priv, 0x00e81c + (id * 0x0c));
ref *= (coef & 0x01000000) ? 2 : 4;
P = (coef & 0x00070000) >> 16;
N = ((coef & 0x0000ff00) >> 8) + 1;
M = ((coef & 0x000000ff) >> 0) + 1;
break;
case 0x84:
case 0x86:
case 0x92:
coef = nv_rd32(priv, 0x00e81c);
P = (coef & 0x00070000) >> 16;
N = (coef & 0x0000ff00) >> 8;
M = (coef & 0x000000ff) >> 0;
break;
case 0x94:
case 0x96:
case 0x98:
rsel = nv_rd32(priv, 0x00c050);
switch (base) {
case 0x4020: rsel = (rsel & 0x00000003) >> 0; break;
case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break;
case 0x4028: rsel = (rsel & 0x00001800) >> 11; break;
case 0x4030: rsel = 3; break;
default:
nv_error(priv, "ref: bad pll 0x%06x\n", base);
return 0;
}
switch (rsel) {
case 0: id = 1; break;
case 1: return clk->read(clk, nv_clk_src_crystal);
case 2: return clk->read(clk, nv_clk_src_href);
case 3: id = 0; break;
}
coef = nv_rd32(priv, 0x00e81c + (id * 0x28));
P = (nv_rd32(priv, 0x00e824 + (id * 0x28)) >> 16) & 7;
P += (coef & 0x00070000) >> 16;
N = (coef & 0x0000ff00) >> 8;
M = (coef & 0x000000ff) >> 0;
break;
default:
BUG_ON(1);
}
if (M)
return (ref * N / M) >> P;
return 0;
}
static u32
read_pll_ref(struct nv50_clock_priv *priv, u32 base)
{
struct nouveau_clock *clk = &priv->base;
u32 src, mast = nv_rd32(priv, 0x00c040);
switch (base) {
case 0x004028:
src = !!(mast & 0x00200000);
break;
case 0x004020:
src = !!(mast & 0x00400000);
break;
case 0x004008:
src = !!(mast & 0x00010000);
break;
case 0x004030:
src = !!(mast & 0x02000000);
break;
case 0x00e810:
return clk->read(clk, nv_clk_src_crystal);
default:
nv_error(priv, "bad pll 0x%06x\n", base);
return 0;
}
if (src)
return clk->read(clk, nv_clk_src_href);
return read_pll_src(priv, base);
}
static u32
read_pll(struct nv50_clock_priv *priv, u32 base)
{
struct nouveau_clock *clk = &priv->base;
u32 mast = nv_rd32(priv, 0x00c040);
u32 ctrl = nv_rd32(priv, base + 0);
u32 coef = nv_rd32(priv, base + 4);
u32 ref = read_pll_ref(priv, base);
u32 freq = 0;
int N1, N2, M1, M2;
if (base == 0x004028 && (mast & 0x00100000)) {
/* wtf, appears to only disable post-divider on nva0 */
if (nv_device(priv)->chipset != 0xa0)
return clk->read(clk, nv_clk_src_dom6);
}
N2 = (coef & 0xff000000) >> 24;
M2 = (coef & 0x00ff0000) >> 16;
N1 = (coef & 0x0000ff00) >> 8;
M1 = (coef & 0x000000ff);
if ((ctrl & 0x80000000) && M1) {
freq = ref * N1 / M1;
if ((ctrl & 0x40000100) == 0x40000000) {
if (M2)
freq = freq * N2 / M2;
else
freq = 0;
}
}
return freq;
}
static int
nv50_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
{
struct nv50_clock_priv *priv = (void *)clk;
u32 mast = nv_rd32(priv, 0x00c040);
u32 P = 0;
switch (src) {
case nv_clk_src_crystal:
return nv_device(priv)->crystal;
case nv_clk_src_href:
return 100000; /* PCIE reference clock */
case nv_clk_src_hclk:
return (u64)clk->read(clk, nv_clk_src_href) * 27778 / 10000;
case nv_clk_src_hclkm3:
return clk->read(clk, nv_clk_src_hclk) * 3;
case nv_clk_src_hclkm3d2:
return clk->read(clk, nv_clk_src_hclk) * 3 / 2;
case nv_clk_src_host:
switch (mast & 0x30000000) {
case 0x00000000: return clk->read(clk, nv_clk_src_href);
case 0x10000000: break;
case 0x20000000: /* !0x50 */
case 0x30000000: return clk->read(clk, nv_clk_src_hclk);
}
break;
case nv_clk_src_core:
if (!(mast & 0x00100000))
P = (nv_rd32(priv, 0x004028) & 0x00070000) >> 16;
switch (mast & 0x00000003) {
case 0x00000000: return clk->read(clk, nv_clk_src_crystal) >> P;
case 0x00000001: return clk->read(clk, nv_clk_src_dom6);
case 0x00000002: return read_pll(priv, 0x004020) >> P;
case 0x00000003: return read_pll(priv, 0x004028) >> P;
}
break;
case nv_clk_src_shader:
P = (nv_rd32(priv, 0x004020) & 0x00070000) >> 16;
switch (mast & 0x00000030) {
case 0x00000000:
if (mast & 0x00000080)
return clk->read(clk, nv_clk_src_host) >> P;
return clk->read(clk, nv_clk_src_crystal) >> P;
case 0x00000010: break;
case 0x00000020: return read_pll(priv, 0x004028) >> P;
case 0x00000030: return read_pll(priv, 0x004020) >> P;
}
break;
case nv_clk_src_mem:
P = (nv_rd32(priv, 0x004008) & 0x00070000) >> 16;
if (nv_rd32(priv, 0x004008) & 0x00000200) {
switch (mast & 0x0000c000) {
case 0x00000000:
return clk->read(clk, nv_clk_src_crystal) >> P;
case 0x00008000:
case 0x0000c000:
return clk->read(clk, nv_clk_src_href) >> P;
}
} else {
return read_pll(priv, 0x004008) >> P;
}
break;
case nv_clk_src_vdec:
P = (read_div(priv) & 0x00000700) >> 8;
switch (nv_device(priv)->chipset) {
case 0x84:
case 0x86:
case 0x92:
case 0x94:
case 0x96:
case 0xa0:
switch (mast & 0x00000c00) {
case 0x00000000:
if (nv_device(priv)->chipset == 0xa0) /* wtf?? */
return clk->read(clk, nv_clk_src_core) >> P;
return clk->read(clk, nv_clk_src_crystal) >> P;
case 0x00000400:
return 0;
case 0x00000800:
if (mast & 0x01000000)
return read_pll(priv, 0x004028) >> P;
return read_pll(priv, 0x004030) >> P;
case 0x00000c00:
return clk->read(clk, nv_clk_src_core) >> P;
}
break;
case 0x98:
switch (mast & 0x00000c00) {
case 0x00000000:
return clk->read(clk, nv_clk_src_core) >> P;
case 0x00000400:
return 0;
case 0x00000800:
return clk->read(clk, nv_clk_src_hclkm3d2) >> P;
case 0x00000c00:
return clk->read(clk, nv_clk_src_mem) >> P;
}
break;
}
break;
case nv_clk_src_dom6:
switch (nv_device(priv)->chipset) {
case 0x50:
case 0xa0:
return read_pll(priv, 0x00e810) >> 2;
case 0x84:
case 0x86:
case 0x92:
case 0x94:
case 0x96:
case 0x98:
P = (read_div(priv) & 0x00000007) >> 0;
switch (mast & 0x0c000000) {
case 0x00000000: return clk->read(clk, nv_clk_src_href);
case 0x04000000: break;
case 0x08000000: return clk->read(clk, nv_clk_src_hclk);
case 0x0c000000:
return clk->read(clk, nv_clk_src_hclkm3) >> P;
}
break;
default:
break;
}
default:
break;
}
nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast);
return -EINVAL;
}
static u32
calc_pll(struct nv50_clock_priv *priv, u32 reg, u32 clk, int *N, int *M, int *P)
{
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvbios_pll pll;
int ret;
ret = nvbios_pll_parse(bios, reg, &pll);
if (ret)
return 0;
pll.vco2.max_freq = 0;
pll.refclk = read_pll_ref(priv, reg);
if (!pll.refclk)
return 0;
return nv04_pll_calc(nv_subdev(priv), &pll, clk, N, M, NULL, NULL, P);
}
static inline u32
calc_div(u32 src, u32 target, int *div)
{
u32 clk0 = src, clk1 = src;
for (*div = 0; *div <= 7; (*div)++) {
if (clk0 <= target) {
clk1 = clk0 << (*div ? 1 : 0);
break;
}
clk0 >>= 1;
}
if (target - clk0 <= clk1 - target)
return clk0;
(*div)--;
return clk1;
}
static inline u32
clk_same(u32 a, u32 b)
{
return ((a / 1000) == (b / 1000));
}
static int
nv50_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
{
struct nv50_clock_priv *priv = (void *)clk;
struct nv50_clock_hwsq *hwsq = &priv->hwsq;
const int shader = cstate->domain[nv_clk_src_shader];
const int core = cstate->domain[nv_clk_src_core];
const int vdec = cstate->domain[nv_clk_src_vdec];
const int dom6 = cstate->domain[nv_clk_src_dom6];
u32 mastm = 0, mastv = 0;
u32 divsm = 0, divsv = 0;
int N, M, P1, P2;
int freq, out;
/* prepare a hwsq script from which we'll perform the reclock */
out = clk_init(hwsq, nv_subdev(clk));
if (out)
return out;
clk_wr32(hwsq, fifo, 0x00000001); /* block fifo */
clk_nsec(hwsq, 8000);
clk_setf(hwsq, 0x10, 0x00); /* disable fb */
clk_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */
/* vdec: avoid modifying xpll until we know exactly how the other
* clock domains work, i suspect at least some of them can also be
* tied to xpll...
*/
if (vdec) {
/* see how close we can get using nvclk as a source */
freq = calc_div(core, vdec, &P1);
/* see how close we can get using xpll/hclk as a source */
if (nv_device(priv)->chipset != 0x98)
out = read_pll(priv, 0x004030);
else
out = clk->read(clk, nv_clk_src_hclkm3d2);
out = calc_div(out, vdec, &P2);
/* select whichever gets us closest */
if (abs(vdec - freq) <= abs(vdec - out)) {
if (nv_device(priv)->chipset != 0x98)
mastv |= 0x00000c00;
divsv |= P1 << 8;
} else {
mastv |= 0x00000800;
divsv |= P2 << 8;
}
mastm |= 0x00000c00;
divsm |= 0x00000700;
}
/* dom6: nfi what this is, but we're limited to various combinations
* of the host clock frequency
*/
if (dom6) {
if (clk_same(dom6, clk->read(clk, nv_clk_src_href))) {
mastv |= 0x00000000;
} else
if (clk_same(dom6, clk->read(clk, nv_clk_src_hclk))) {
mastv |= 0x08000000;
} else {
freq = clk->read(clk, nv_clk_src_hclk) * 3;
freq = calc_div(freq, dom6, &P1);
mastv |= 0x0c000000;
divsv |= P1;
}
mastm |= 0x0c000000;
divsm |= 0x00000007;
}
/* vdec/dom6: switch to "safe" clocks temporarily, update dividers
* and then switch to target clocks
*/
clk_mask(hwsq, mast, mastm, 0x00000000);
clk_mask(hwsq, divs, divsm, divsv);
clk_mask(hwsq, mast, mastm, mastv);
/* core/shader: disconnect nvclk/sclk from their PLLs (nvclk to dom6,
* sclk to hclk) before reprogramming
*/
if (nv_device(priv)->chipset < 0x92)
clk_mask(hwsq, mast, 0x001000b0, 0x00100080);
else
clk_mask(hwsq, mast, 0x000000b3, 0x00000081);
/* core: for the moment at least, always use nvpll */
freq = calc_pll(priv, 0x4028, core, &N, &M, &P1);
if (freq == 0)
return -ERANGE;
clk_mask(hwsq, nvpll[0], 0xc03f0100,
0x80000000 | (P1 << 19) | (P1 << 16));
clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M);
/* shader: tie to nvclk if possible, otherwise use spll. have to be
* very careful that the shader clock is at least twice the core, or
* some chipsets will be very unhappy. i expect most or all of these
* cases will be handled by tying to nvclk, but it's possible there's
* corners
*/
if (P1-- && shader == (core << 1)) {
clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16));
clk_mask(hwsq, mast, 0x00100033, 0x00000023);
} else {
freq = calc_pll(priv, 0x4020, shader, &N, &M, &P1);
if (freq == 0)
return -ERANGE;
clk_mask(hwsq, spll[0], 0xc03f0100,
0x80000000 | (P1 << 19) | (P1 << 16));
clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M);
clk_mask(hwsq, mast, 0x00100033, 0x00000033);
}
/* restore normal operation */
clk_setf(hwsq, 0x10, 0x01); /* enable fb */
clk_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */
clk_wr32(hwsq, fifo, 0x00000000); /* un-block fifo */
return 0;
}
static int
nv50_clock_prog(struct nouveau_clock *clk)
{
struct nv50_clock_priv *priv = (void *)clk;
return clk_exec(&priv->hwsq, true);
}
static void
nv50_clock_tidy(struct nouveau_clock *clk)
{
struct nv50_clock_priv *priv = (void *)clk;
clk_exec(&priv->hwsq, false);
}
int
nv50_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv50_clock_oclass *pclass = (void *)oclass;
struct nv50_clock_priv *priv;
int ret;
ret = nouveau_clock_create(parent, engine, oclass, &priv);
ret = nouveau_clock_create(parent, engine, oclass, pclass->domains,
&priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->base.pll_calc = nv04_clock_pll_calc;
priv->hwsq.r_fifo = hwsq_reg(0x002504);
priv->hwsq.r_spll[0] = hwsq_reg(0x004020);
priv->hwsq.r_spll[1] = hwsq_reg(0x004024);
priv->hwsq.r_nvpll[0] = hwsq_reg(0x004028);
priv->hwsq.r_nvpll[1] = hwsq_reg(0x00402c);
switch (nv_device(priv)->chipset) {
case 0x92:
case 0x94:
case 0x96:
priv->hwsq.r_divs = hwsq_reg(0x004800);
break;
default:
priv->hwsq.r_divs = hwsq_reg(0x004700);
break;
}
priv->hwsq.r_mast = hwsq_reg(0x00c040);
priv->base.read = nv50_clock_read;
priv->base.calc = nv50_clock_calc;
priv->base.prog = nv50_clock_prog;
priv->base.tidy = nv50_clock_tidy;
return 0;
}
struct nouveau_oclass
nv50_clock_oclass = {
.handle = NV_SUBDEV(CLOCK, 0x50),
.ofuncs = &(struct nouveau_ofuncs) {
static struct nouveau_clocks
nv50_domains[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
{ nv_clk_src_core , 0xff, 0, "core", 1000 },
{ nv_clk_src_shader , 0xff, 0, "shader", 1000 },
{ nv_clk_src_mem , 0xff, 0, "memory", 1000 },
{ nv_clk_src_max }
};
struct nouveau_oclass *
nv50_clock_oclass = &(struct nv50_clock_oclass) {
.base.handle = NV_SUBDEV(CLOCK, 0x50),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_clock_ctor,
.dtor = _nouveau_clock_dtor,
.init = _nouveau_clock_init,
.fini = _nouveau_clock_fini,
},
};
.domains = nv50_domains,
}.base;
drivers/gpu/drm/nouveau/core/subdev/clock/nv50.h 0 → 100644
View file @ 7c856522
#ifndef __NVKM_CLK_NV50_H__
#define __NVKM_CLK_NV50_H__
#include <subdev/bus.h>
#include <subdev/bus/hwsq.h>
#include <subdev/clock.h>
struct nv50_clock_hwsq {
struct hwsq base;
struct hwsq_reg r_fifo;
struct hwsq_reg r_spll[2];
struct hwsq_reg r_nvpll[2];
struct hwsq_reg r_divs;
struct hwsq_reg r_mast;
};
struct nv50_clock_priv {
struct nouveau_clock base;
struct nv50_clock_hwsq hwsq;
};
int nv50_clock_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32,
struct nouveau_object **);
struct nv50_clock_oclass {
struct nouveau_oclass base;
struct nouveau_clocks *domains;
};
#endif
drivers/gpu/drm/nouveau/core/subdev/clock/nv84.c 0 → 100644
View file @ 7c856522
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "nv50.h"
static struct nouveau_clocks
nv84_domains[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
{ nv_clk_src_core , 0xff, 0, "core", 1000 },
{ nv_clk_src_shader , 0xff, 0, "shader", 1000 },
{ nv_clk_src_mem , 0xff, 0, "memory", 1000 },
{ nv_clk_src_vdec , 0xff },
{ nv_clk_src_max }
};
struct nouveau_oclass *
nv84_clock_oclass = &(struct nv50_clock_oclass) {
.base.handle = NV_SUBDEV(CLOCK, 0x84),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_clock_ctor,
.dtor = _nouveau_clock_dtor,
.init = _nouveau_clock_init,
.fini = _nouveau_clock_fini,
},
.domains = nv84_domains,
}.base;
drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c
View file @ 7c856522
......@@ -22,33 +22,277 @@
* Authors: Ben Skeggs
*/
#include <subdev/clock.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>
#include "pll.h"
#include "nva3.h"
struct nva3_clock_priv {
struct nouveau_clock base;
struct nva3_clock_info eng[nv_clk_src_max];
};
static u32 read_clk(struct nva3_clock_priv *, int, bool);
static u32 read_pll(struct nva3_clock_priv *, int, u32);
static u32
read_vco(struct nva3_clock_priv *priv, int clk)
{
u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4));
if ((sctl & 0x00000030) != 0x00000030)
return read_pll(priv, 0x41, 0x00e820);
return read_pll(priv, 0x42, 0x00e8a0);
}
static u32
read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en)
{
u32 sctl, sdiv, sclk;
/* refclk for the 0xe8xx plls is a fixed frequency */
if (clk >= 0x40) {
if (nv_device(priv)->chipset == 0xaf) {
/* no joke.. seriously.. sigh.. */
return nv_rd32(priv, 0x00471c) * 1000;
}
return nv_device(priv)->crystal;
}
sctl = nv_rd32(priv, 0x4120 + (clk * 4));
if (!ignore_en && !(sctl & 0x00000100))
return 0;
switch (sctl & 0x00003000) {
case 0x00000000:
return nv_device(priv)->crystal;
case 0x00002000:
if (sctl & 0x00000040)
return 108000;
return 100000;
case 0x00003000:
sclk = read_vco(priv, clk);
sdiv = ((sctl & 0x003f0000) >> 16) + 2;
return (sclk * 2) / sdiv;
default:
return 0;
}
}
static u32
read_pll(struct nva3_clock_priv *priv, int clk, u32 pll)
{
u32 ctrl = nv_rd32(priv, pll + 0);
u32 sclk = 0, P = 1, N = 1, M = 1;
if (!(ctrl & 0x00000008)) {
if (ctrl & 0x00000001) {
u32 coef = nv_rd32(priv, pll + 4);
M = (coef & 0x000000ff) >> 0;
N = (coef & 0x0000ff00) >> 8;
P = (coef & 0x003f0000) >> 16;
/* no post-divider on these.. */
if ((pll & 0x00ff00) == 0x00e800)
P = 1;
sclk = read_clk(priv, 0x00 + clk, false);
}
} else {
sclk = read_clk(priv, 0x10 + clk, false);
}
if (M * P)
return sclk * N / (M * P);
return 0;
}
static int
nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
{
struct nva3_clock_priv *priv = (void *)clk;
switch (src) {
case nv_clk_src_crystal:
return nv_device(priv)->crystal;
case nv_clk_src_href:
return 100000;
case nv_clk_src_core:
return read_pll(priv, 0x00, 0x4200);
case nv_clk_src_shader:
return read_pll(priv, 0x01, 0x4220);
case nv_clk_src_mem:
return read_pll(priv, 0x02, 0x4000);
case nv_clk_src_disp:
return read_clk(priv, 0x20, false);
case nv_clk_src_vdec:
return read_clk(priv, 0x21, false);
case nv_clk_src_daemon:
return read_clk(priv, 0x25, false);
default:
nv_error(clk, "invalid clock source %d\n", src);
return -EINVAL;
}
}
int
nva3_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info,
int clk, struct nouveau_pll_vals *pv)
nva3_clock_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
struct nva3_clock_info *info)
{
int ret, N, M, P;
struct nouveau_bios *bios = nouveau_bios(clock);
struct nva3_clock_priv *priv = (void *)clock;
struct nvbios_pll limits;
u32 oclk, sclk, sdiv;
int P, N, M, diff;
int ret;
info->pll = 0;
info->clk = 0;
ret = nva3_pll_calc(nv_subdev(clock), info, clk, &N, NULL, &M, &P);
switch (khz) {
case 27000:
info->clk = 0x00000100;
return khz;
case 100000:
info->clk = 0x00002100;
return khz;
case 108000:
info->clk = 0x00002140;
return khz;
default:
sclk = read_vco(priv, clk);
sdiv = min((sclk * 2) / (khz - 2999), (u32)65);
/* if the clock has a PLL attached, and we can get a within
* [-2, 3) MHz of a divider, we'll disable the PLL and use
* the divider instead.
*
* divider can go as low as 2, limited here because NVIDIA
* and the VBIOS on my NVA8 seem to prefer using the PLL
* for 810MHz - is there a good reason?
*/
if (sdiv > 4) {
oclk = (sclk * 2) / sdiv;
diff = khz - oclk;
if (!pll || (diff >= -2000 && diff < 3000)) {
info->clk = (((sdiv - 2) << 16) | 0x00003100);
return oclk;
}
}
if (ret > 0) {
pv->refclk = info->refclk;
pv->N1 = N;
pv->M1 = M;
pv->log2P = P;
if (!pll)
return -ERANGE;
break;
}
ret = nvbios_pll_parse(bios, pll, &limits);
if (ret)
return ret;
limits.refclk = read_clk(priv, clk - 0x10, true);
if (!limits.refclk)
return -EINVAL;
ret = nva3_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P);
if (ret >= 0) {
info->clk = nv_rd32(priv, 0x4120 + (clk * 4));
info->pll = (P << 16) | (N << 8) | M;
}
return ret ? ret : -ERANGE;
}
static int
calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate,
int clk, u32 pll, int idx)
{
int ret = nva3_clock_info(&priv->base, clk, pll, cstate->domain[idx],
&priv->eng[idx]);
if (ret >= 0)
return 0;
return ret;
}
static void
prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx)
{
struct nva3_clock_info *info = &priv->eng[idx];
const u32 src0 = 0x004120 + (clk * 4);
const u32 src1 = 0x004160 + (clk * 4);
const u32 ctrl = pll + 0;
const u32 coef = pll + 4;
if (info->pll) {
nv_mask(priv, src0, 0x00000101, 0x00000101);
nv_wr32(priv, coef, info->pll);
nv_mask(priv, ctrl, 0x00000015, 0x00000015);
nv_mask(priv, ctrl, 0x00000010, 0x00000000);
nv_wait(priv, ctrl, 0x00020000, 0x00020000);
nv_mask(priv, ctrl, 0x00000010, 0x00000010);
nv_mask(priv, ctrl, 0x00000008, 0x00000000);
nv_mask(priv, src1, 0x00000100, 0x00000000);
nv_mask(priv, src1, 0x00000001, 0x00000000);
} else {
nv_mask(priv, src1, 0x003f3141, 0x00000101 | info->clk);
nv_mask(priv, ctrl, 0x00000018, 0x00000018);
udelay(20);
nv_mask(priv, ctrl, 0x00000001, 0x00000000);
nv_mask(priv, src0, 0x00000100, 0x00000000);
nv_mask(priv, src0, 0x00000001, 0x00000000);
}
}
static void
prog_clk(struct nva3_clock_priv *priv, int clk, int idx)
{
struct nva3_clock_info *info = &priv->eng[idx];
nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk);
}
static int
nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
{
struct nva3_clock_priv *priv = (void *)clk;
int ret;
if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) ||
(ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) ||
(ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) ||
(ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)))
return ret;
return 0;
}
static int
nva3_clock_prog(struct nouveau_clock *clk)
{
struct nva3_clock_priv *priv = (void *)clk;
prog_pll(priv, 0x00, 0x004200, nv_clk_src_core);
prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader);
prog_clk(priv, 0x20, nv_clk_src_disp);
prog_clk(priv, 0x21, nv_clk_src_vdec);
return 0;
}
static void
nva3_clock_tidy(struct nouveau_clock *clk)
{
}
static struct nouveau_clocks
nva3_domain[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
{ nv_clk_src_core , 0x00, 0, "core", 1000 },
{ nv_clk_src_shader , 0x01, 0, "shader", 1000 },
{ nv_clk_src_mem , 0x02, 0, "memory", 1000 },
{ nv_clk_src_vdec , 0x03 },
{ nv_clk_src_disp , 0x04 },
{ nv_clk_src_max }
};
static int
nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
......@@ -58,12 +302,15 @@ nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nva3_clock_priv *priv;
int ret;
ret = nouveau_clock_create(parent, engine, oclass, &priv);
ret = nouveau_clock_create(parent, engine, oclass, nva3_domain, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->base.pll_calc = nva3_clock_pll_calc;
priv->base.read = nva3_clock_read;
priv->base.calc = nva3_clock_calc;
priv->base.prog = nva3_clock_prog;
priv->base.tidy = nva3_clock_tidy;
return 0;
}
......
drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h 0 → 100644
View file @ 7c856522
#ifndef __NVKM_CLK_NVA3_H__
#define __NVKM_CLK_NVA3_H__
#include <subdev/clock.h>
struct nva3_clock_info {
u32 clk;
u32 pll;
};
int nva3_clock_info(struct nouveau_clock *, int, u32, u32,
struct nva3_clock_info *);
#endif
drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c
View file @ 7c856522
......@@ -25,11 +25,408 @@
#include <subdev/clock.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>
#include "pll.h"
struct nvc0_clock_info {
u32 freq;
u32 ssel;
u32 mdiv;
u32 dsrc;
u32 ddiv;
u32 coef;
};
struct nvc0_clock_priv {
struct nouveau_clock base;
struct nvc0_clock_info eng[16];
};
static u32 read_div(struct nvc0_clock_priv *, int, u32, u32);
static u32
read_vco(struct nvc0_clock_priv *priv, u32 dsrc)
{
struct nouveau_clock *clk = &priv->base;
u32 ssrc = nv_rd32(priv, dsrc);
if (!(ssrc & 0x00000100))
return clk->read(clk, nv_clk_src_sppll0);
return clk->read(clk, nv_clk_src_sppll1);
}
static u32
read_pll(struct nvc0_clock_priv *priv, u32 pll)
{
struct nouveau_clock *clk = &priv->base;
u32 ctrl = nv_rd32(priv, pll + 0x00);
u32 coef = nv_rd32(priv, pll + 0x04);
u32 P = (coef & 0x003f0000) >> 16;
u32 N = (coef & 0x0000ff00) >> 8;
u32 M = (coef & 0x000000ff) >> 0;
u32 sclk;
if (!(ctrl & 0x00000001))
return 0;
switch (pll) {
case 0x00e800:
case 0x00e820:
sclk = nv_device(priv)->crystal;
P = 1;
break;
case 0x132000:
sclk = clk->read(clk, nv_clk_src_mpllsrc);
break;
case 0x132020:
sclk = clk->read(clk, nv_clk_src_mpllsrcref);
break;
case 0x137000:
case 0x137020:
case 0x137040:
case 0x1370e0:
sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140);
break;
default:
return 0;
}
return sclk * N / M / P;
}
static u32
read_div(struct nvc0_clock_priv *priv, int doff, u32 dsrc, u32 dctl)
{
u32 ssrc = nv_rd32(priv, dsrc + (doff * 4));
u32 sctl = nv_rd32(priv, dctl + (doff * 4));
switch (ssrc & 0x00000003) {
case 0:
if ((ssrc & 0x00030000) != 0x00030000)
return nv_device(priv)->crystal;
return 108000;
case 2:
return 100000;
case 3:
if (sctl & 0x80000000) {
u32 sclk = read_vco(priv, dsrc + (doff * 4));
u32 sdiv = (sctl & 0x0000003f) + 2;
return (sclk * 2) / sdiv;
}
return read_vco(priv, dsrc + (doff * 4));
default:
return 0;
}
}
static u32
read_clk(struct nvc0_clock_priv *priv, int clk)
{
u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4));
u32 ssel = nv_rd32(priv, 0x137100);
u32 sclk, sdiv;
if (ssel & (1 << clk)) {
if (clk < 7)
sclk = read_pll(priv, 0x137000 + (clk * 0x20));
else
sclk = read_pll(priv, 0x1370e0);
sdiv = ((sctl & 0x00003f00) >> 8) + 2;
} else {
sclk = read_div(priv, clk, 0x137160, 0x1371d0);
sdiv = ((sctl & 0x0000003f) >> 0) + 2;
}
if (sctl & 0x80000000)
return (sclk * 2) / sdiv;
return sclk;
}
static int
nvc0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
{
struct nouveau_device *device = nv_device(clk);
struct nvc0_clock_priv *priv = (void *)clk;
switch (src) {
case nv_clk_src_crystal:
return device->crystal;
case nv_clk_src_href:
return 100000;
case nv_clk_src_sppll0:
return read_pll(priv, 0x00e800);
case nv_clk_src_sppll1:
return read_pll(priv, 0x00e820);
case nv_clk_src_mpllsrcref:
return read_div(priv, 0, 0x137320, 0x137330);
case nv_clk_src_mpllsrc:
return read_pll(priv, 0x132020);
case nv_clk_src_mpll:
return read_pll(priv, 0x132000);
case nv_clk_src_mdiv:
return read_div(priv, 0, 0x137300, 0x137310);
case nv_clk_src_mem:
if (nv_rd32(priv, 0x1373f0) & 0x00000002)
return clk->read(clk, nv_clk_src_mpll);
return clk->read(clk, nv_clk_src_mdiv);
case nv_clk_src_gpc:
return read_clk(priv, 0x00);
case nv_clk_src_rop:
return read_clk(priv, 0x01);
case nv_clk_src_hubk07:
return read_clk(priv, 0x02);
case nv_clk_src_hubk06:
return read_clk(priv, 0x07);
case nv_clk_src_hubk01:
return read_clk(priv, 0x08);
case nv_clk_src_copy:
return read_clk(priv, 0x09);
case nv_clk_src_daemon:
return read_clk(priv, 0x0c);
case nv_clk_src_vdec:
return read_clk(priv, 0x0e);
default:
nv_error(clk, "invalid clock source %d\n", src);
return -EINVAL;
}
}
static u32
calc_div(struct nvc0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
{
u32 div = min((ref * 2) / freq, (u32)65);
if (div < 2)
div = 2;
*ddiv = div - 2;
return (ref * 2) / div;
}
static u32
calc_src(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
{
u32 sclk;
/* use one of the fixed frequencies if possible */
*ddiv = 0x00000000;
switch (freq) {
case 27000:
case 108000:
*dsrc = 0x00000000;
if (freq == 108000)
*dsrc |= 0x00030000;
return freq;
case 100000:
*dsrc = 0x00000002;
return freq;
default:
*dsrc = 0x00000003;
break;
}
/* otherwise, calculate the closest divider */
sclk = read_vco(priv, 0x137160 + (clk * 4));
if (clk < 7)
sclk = calc_div(priv, clk, sclk, freq, ddiv);
return sclk;
}
static u32
calc_pll(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *coef)
{
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvbios_pll limits;
int N, M, P, ret;
ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits);
if (ret)
return 0;
limits.refclk = read_div(priv, clk, 0x137120, 0x137140);
if (!limits.refclk)
return 0;
ret = nva3_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P);
if (ret <= 0)
return 0;
*coef = (P << 16) | (N << 8) | M;
return ret;
}
static int
calc_clk(struct nvc0_clock_priv *priv,
struct nouveau_cstate *cstate, int clk, int dom)
{
struct nvc0_clock_info *info = &priv->eng[clk];
u32 freq = cstate->domain[dom];
u32 src0, div0, div1D, div1P = 0;
u32 clk0, clk1 = 0;
/* invalid clock domain */
if (!freq)
return 0;
/* first possible path, using only dividers */
clk0 = calc_src(priv, clk, freq, &src0, &div0);
clk0 = calc_div(priv, clk, clk0, freq, &div1D);
/* see if we can get any closer using PLLs */
if (clk0 != freq && (0x00004387 & (1 << clk))) {
if (clk <= 7)
clk1 = calc_pll(priv, clk, freq, &info->coef);
else
clk1 = cstate->domain[nv_clk_src_hubk06];
clk1 = calc_div(priv, clk, clk1, freq, &div1P);
}
/* select the method which gets closest to target freq */
if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
info->dsrc = src0;
if (div0) {
info->ddiv |= 0x80000000;
info->ddiv |= div0 << 8;
info->ddiv |= div0;
}
if (div1D) {
info->mdiv |= 0x80000000;
info->mdiv |= div1D;
}
info->ssel = info->coef = 0;
info->freq = clk0;
} else {
if (div1P) {
info->mdiv |= 0x80000000;
info->mdiv |= div1P << 8;
}
info->ssel = (1 << clk);
info->freq = clk1;
}
return 0;
}
static int
nvc0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
{
struct nvc0_clock_priv *priv = (void *)clk;
int ret;
if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) ||
(ret = calc_clk(priv, cstate, 0x01, nv_clk_src_rop)) ||
(ret = calc_clk(priv, cstate, 0x02, nv_clk_src_hubk07)) ||
(ret = calc_clk(priv, cstate, 0x07, nv_clk_src_hubk06)) ||
(ret = calc_clk(priv, cstate, 0x08, nv_clk_src_hubk01)) ||
(ret = calc_clk(priv, cstate, 0x09, nv_clk_src_copy)) ||
(ret = calc_clk(priv, cstate, 0x0c, nv_clk_src_daemon)) ||
(ret = calc_clk(priv, cstate, 0x0e, nv_clk_src_vdec)))
return ret;
return 0;
}
static void
nvc0_clock_prog_0(struct nvc0_clock_priv *priv, int clk)
{
struct nvc0_clock_info *info = &priv->eng[clk];
if (clk < 7 && !info->ssel) {
nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv);
nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc);
}
}
static void
nvc0_clock_prog_1(struct nvc0_clock_priv *priv, int clk)
{
nv_mask(priv, 0x137100, (1 << clk), 0x00000000);
nv_wait(priv, 0x137100, (1 << clk), 0x00000000);
}
static void
nvc0_clock_prog_2(struct nvc0_clock_priv *priv, int clk)
{
struct nvc0_clock_info *info = &priv->eng[clk];
const u32 addr = 0x137000 + (clk * 0x20);
if (clk <= 7) {
nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000);
nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000);
if (info->coef) {
nv_wr32(priv, addr + 0x04, info->coef);
nv_mask(priv, addr + 0x00, 0x00000001, 0x00000001);
nv_wait(priv, addr + 0x00, 0x00020000, 0x00020000);
nv_mask(priv, addr + 0x00, 0x00020004, 0x00000004);
}
}
}
static void
nvc0_clock_prog_3(struct nvc0_clock_priv *priv, int clk)
{
struct nvc0_clock_info *info = &priv->eng[clk];
if (info->ssel) {
nv_mask(priv, 0x137100, (1 << clk), info->ssel);
nv_wait(priv, 0x137100, (1 << clk), info->ssel);
}
}
static void
nvc0_clock_prog_4(struct nvc0_clock_priv *priv, int clk)
{
struct nvc0_clock_info *info = &priv->eng[clk];
nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv);
}
static int
nvc0_clock_prog(struct nouveau_clock *clk)
{
struct nvc0_clock_priv *priv = (void *)clk;
struct {
void (*exec)(struct nvc0_clock_priv *, int);
} stage[] = {
{ nvc0_clock_prog_0 }, /* div programming */
{ nvc0_clock_prog_1 }, /* select div mode */
{ nvc0_clock_prog_2 }, /* (maybe) program pll */
{ nvc0_clock_prog_3 }, /* (maybe) select pll mode */
{ nvc0_clock_prog_4 }, /* final divider */
};
int i, j;
for (i = 0; i < ARRAY_SIZE(stage); i++) {
for (j = 0; j < ARRAY_SIZE(priv->eng); j++) {
if (!priv->eng[j].freq)
continue;
stage[i].exec(priv, j);
}
}
return 0;
}
static void
nvc0_clock_tidy(struct nouveau_clock *clk)
{
struct nvc0_clock_priv *priv = (void *)clk;
memset(priv->eng, 0x00, sizeof(priv->eng));
}
static struct nouveau_clocks
nvc0_domain[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
{ nv_clk_src_hubk06 , 0x00 },
{ nv_clk_src_hubk01 , 0x01 },
{ nv_clk_src_copy , 0x02 },
{ nv_clk_src_gpc , 0x03, 0, "core", 2000 },
{ nv_clk_src_rop , 0x04 },
{ nv_clk_src_mem , 0x05, 0, "memory", 1000 },
{ nv_clk_src_vdec , 0x06 },
{ nv_clk_src_daemon , 0x0a },
{ nv_clk_src_hubk07 , 0x0b },
{ nv_clk_src_max }
};
static int
......@@ -40,12 +437,15 @@ nvc0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nvc0_clock_priv *priv;
int ret;
ret = nouveau_clock_create(parent, engine, oclass, &priv);
ret = nouveau_clock_create(parent, engine, oclass, nvc0_domain, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->base.pll_calc = nva3_clock_pll_calc;
priv->base.read = nvc0_clock_read;
priv->base.calc = nvc0_clock_calc;
priv->base.prog = nvc0_clock_prog;
priv->base.tidy = nvc0_clock_tidy;
return 0;
}
......
drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c 0 → 100644
View file @ 7c856522
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/clock.h>
#include <subdev/timer.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include "pll.h"
struct nve0_clock_info {
u32 freq;
u32 ssel;
u32 mdiv;
u32 dsrc;
u32 ddiv;
u32 coef;
};
struct nve0_clock_priv {
struct nouveau_clock base;
struct nve0_clock_info eng[16];
};
static u32 read_div(struct nve0_clock_priv *, int, u32, u32);
static u32 read_pll(struct nve0_clock_priv *, u32);
static u32
read_vco(struct nve0_clock_priv *priv, u32 dsrc)
{
u32 ssrc = nv_rd32(priv, dsrc);
if (!(ssrc & 0x00000100))
return read_pll(priv, 0x00e800);
return read_pll(priv, 0x00e820);
}
static u32
read_pll(struct nve0_clock_priv *priv, u32 pll)
{
u32 ctrl = nv_rd32(priv, pll + 0x00);
u32 coef = nv_rd32(priv, pll + 0x04);
u32 P = (coef & 0x003f0000) >> 16;
u32 N = (coef & 0x0000ff00) >> 8;
u32 M = (coef & 0x000000ff) >> 0;
u32 sclk;
u16 fN = 0xf000;
if (!(ctrl & 0x00000001))
return 0;
switch (pll) {
case 0x00e800:
case 0x00e820:
sclk = nv_device(priv)->crystal;
P = 1;
break;
case 0x132000:
sclk = read_pll(priv, 0x132020);
P = (coef & 0x10000000) ? 2 : 1;
break;
case 0x132020:
sclk = read_div(priv, 0, 0x137320, 0x137330);
fN = nv_rd32(priv, pll + 0x10) >> 16;
break;
case 0x137000:
case 0x137020:
case 0x137040:
case 0x1370e0:
sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140);
break;
default:
return 0;
}
if (P == 0)
P = 1;
sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13);
return sclk / (M * P);
}
static u32
read_div(struct nve0_clock_priv *priv, int doff, u32 dsrc, u32 dctl)
{
u32 ssrc = nv_rd32(priv, dsrc + (doff * 4));
u32 sctl = nv_rd32(priv, dctl + (doff * 4));
switch (ssrc & 0x00000003) {
case 0:
if ((ssrc & 0x00030000) != 0x00030000)
return nv_device(priv)->crystal;
return 108000;
case 2:
return 100000;
case 3:
if (sctl & 0x80000000) {
u32 sclk = read_vco(priv, dsrc + (doff * 4));
u32 sdiv = (sctl & 0x0000003f) + 2;
return (sclk * 2) / sdiv;
}
return read_vco(priv, dsrc + (doff * 4));
default:
return 0;
}
}
static u32
read_mem(struct nve0_clock_priv *priv)
{
switch (nv_rd32(priv, 0x1373f4) & 0x0000000f) {
case 1: return read_pll(priv, 0x132020);
case 2: return read_pll(priv, 0x132000);
default:
return 0;
}
}
static u32
read_clk(struct nve0_clock_priv *priv, int clk)
{
u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4));
u32 sclk, sdiv;
if (clk < 7) {
u32 ssel = nv_rd32(priv, 0x137100);
if (ssel & (1 << clk)) {
sclk = read_pll(priv, 0x137000 + (clk * 0x20));
sdiv = 1;
} else {
sclk = read_div(priv, clk, 0x137160, 0x1371d0);
sdiv = 0;
}
} else {
u32 ssrc = nv_rd32(priv, 0x137160 + (clk * 0x04));
if ((ssrc & 0x00000003) == 0x00000003) {
sclk = read_div(priv, clk, 0x137160, 0x1371d0);
if (ssrc & 0x00000100) {
if (ssrc & 0x40000000)
sclk = read_pll(priv, 0x1370e0);
sdiv = 1;
} else {
sdiv = 0;
}
} else {
sclk = read_div(priv, clk, 0x137160, 0x1371d0);
sdiv = 0;
}
}
if (sctl & 0x80000000) {
if (sdiv)
sdiv = ((sctl & 0x00003f00) >> 8) + 2;
else
sdiv = ((sctl & 0x0000003f) >> 0) + 2;
return (sclk * 2) / sdiv;
}
return sclk;
}
static int
nve0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
{
struct nouveau_device *device = nv_device(clk);
struct nve0_clock_priv *priv = (void *)clk;
switch (src) {
case nv_clk_src_crystal:
return device->crystal;
case nv_clk_src_href:
return 100000;
case nv_clk_src_mem:
return read_mem(priv);
case nv_clk_src_gpc:
return read_clk(priv, 0x00);
case nv_clk_src_rop:
return read_clk(priv, 0x01);
case nv_clk_src_hubk07:
return read_clk(priv, 0x02);
case nv_clk_src_hubk06:
return read_clk(priv, 0x07);
case nv_clk_src_hubk01:
return read_clk(priv, 0x08);
case nv_clk_src_daemon:
return read_clk(priv, 0x0c);
case nv_clk_src_vdec:
return read_clk(priv, 0x0e);
default:
nv_error(clk, "invalid clock source %d\n", src);
return -EINVAL;
}
}
static u32
calc_div(struct nve0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
{
u32 div = min((ref * 2) / freq, (u32)65);
if (div < 2)
div = 2;
*ddiv = div - 2;
return (ref * 2) / div;
}
static u32
calc_src(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
{
u32 sclk;
/* use one of the fixed frequencies if possible */
*ddiv = 0x00000000;
switch (freq) {
case 27000:
case 108000:
*dsrc = 0x00000000;
if (freq == 108000)
*dsrc |= 0x00030000;
return freq;
case 100000:
*dsrc = 0x00000002;
return freq;
default:
*dsrc = 0x00000003;
break;
}
/* otherwise, calculate the closest divider */
sclk = read_vco(priv, 0x137160 + (clk * 4));
if (clk < 7)
sclk = calc_div(priv, clk, sclk, freq, ddiv);
return sclk;
}
static u32
calc_pll(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *coef)
{
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvbios_pll limits;
int N, M, P, ret;
ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits);
if (ret)
return 0;
limits.refclk = read_div(priv, clk, 0x137120, 0x137140);
if (!limits.refclk)
return 0;
ret = nva3_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P);
if (ret <= 0)
return 0;
*coef = (P << 16) | (N << 8) | M;
return ret;
}
static int
calc_clk(struct nve0_clock_priv *priv,
struct nouveau_cstate *cstate, int clk, int dom)
{
struct nve0_clock_info *info = &priv->eng[clk];
u32 freq = cstate->domain[dom];
u32 src0, div0, div1D, div1P = 0;
u32 clk0, clk1 = 0;
/* invalid clock domain */
if (!freq)
return 0;
/* first possible path, using only dividers */
clk0 = calc_src(priv, clk, freq, &src0, &div0);
clk0 = calc_div(priv, clk, clk0, freq, &div1D);
/* see if we can get any closer using PLLs */
if (clk0 != freq && (0x0000ff87 & (1 << clk))) {
if (clk <= 7)
clk1 = calc_pll(priv, clk, freq, &info->coef);
else
clk1 = cstate->domain[nv_clk_src_hubk06];
clk1 = calc_div(priv, clk, clk1, freq, &div1P);
}
/* select the method which gets closest to target freq */
if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
info->dsrc = src0;
if (div0) {
info->ddiv |= 0x80000000;
info->ddiv |= div0 << 8;
info->ddiv |= div0;
}
if (div1D) {
info->mdiv |= 0x80000000;
info->mdiv |= div1D;
}
info->ssel = 0;
info->freq = clk0;
} else {
if (div1P) {
info->mdiv |= 0x80000000;
info->mdiv |= div1P << 8;
}
info->ssel = (1 << clk);
info->dsrc = 0x40000100;
info->freq = clk1;
}
return 0;
}
static int
nve0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
{
struct nve0_clock_priv *priv = (void *)clk;
int ret;
if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) ||
(ret = calc_clk(priv, cstate, 0x01, nv_clk_src_rop)) ||
(ret = calc_clk(priv, cstate, 0x02, nv_clk_src_hubk07)) ||
(ret = calc_clk(priv, cstate, 0x07, nv_clk_src_hubk06)) ||
(ret = calc_clk(priv, cstate, 0x08, nv_clk_src_hubk01)) ||
(ret = calc_clk(priv, cstate, 0x0c, nv_clk_src_daemon)) ||
(ret = calc_clk(priv, cstate, 0x0e, nv_clk_src_vdec)))
return ret;
return 0;
}
static void
nve0_clock_prog_0(struct nve0_clock_priv *priv, int clk)
{
struct nve0_clock_info *info = &priv->eng[clk];
if (!info->ssel) {
nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv);
nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc);
}
}
static void
nve0_clock_prog_1_0(struct nve0_clock_priv *priv, int clk)
{
nv_mask(priv, 0x137100, (1 << clk), 0x00000000);
nv_wait(priv, 0x137100, (1 << clk), 0x00000000);
}
static void
nve0_clock_prog_1_1(struct nve0_clock_priv *priv, int clk)
{
nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000000);
}
static void
nve0_clock_prog_2(struct nve0_clock_priv *priv, int clk)
{
struct nve0_clock_info *info = &priv->eng[clk];
const u32 addr = 0x137000 + (clk * 0x20);
nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000);
nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000);
if (info->coef) {
nv_wr32(priv, addr + 0x04, info->coef);
nv_mask(priv, addr + 0x00, 0x00000001, 0x00000001);
nv_wait(priv, addr + 0x00, 0x00020000, 0x00020000);
nv_mask(priv, addr + 0x00, 0x00020004, 0x00000004);
}
}
static void
nve0_clock_prog_3(struct nve0_clock_priv *priv, int clk)
{
struct nve0_clock_info *info = &priv->eng[clk];
nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv);
}
static void
nve0_clock_prog_4_0(struct nve0_clock_priv *priv, int clk)
{
struct nve0_clock_info *info = &priv->eng[clk];
if (info->ssel) {
nv_mask(priv, 0x137100, (1 << clk), info->ssel);
nv_wait(priv, 0x137100, (1 << clk), info->ssel);
}
}
static void
nve0_clock_prog_4_1(struct nve0_clock_priv *priv, int clk)
{
struct nve0_clock_info *info = &priv->eng[clk];
if (info->ssel) {
nv_mask(priv, 0x137160 + (clk * 0x04), 0x40000000, 0x40000000);
nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000100);
}
}
static int
nve0_clock_prog(struct nouveau_clock *clk)
{
struct nve0_clock_priv *priv = (void *)clk;
struct {
u32 mask;
void (*exec)(struct nve0_clock_priv *, int);
} stage[] = {
{ 0x007f, nve0_clock_prog_0 }, /* div programming */
{ 0x007f, nve0_clock_prog_1_0 }, /* select div mode */
{ 0xff80, nve0_clock_prog_1_1 },
{ 0x00ff, nve0_clock_prog_2 }, /* (maybe) program pll */
{ 0xff80, nve0_clock_prog_3 }, /* final divider */
{ 0x007f, nve0_clock_prog_4_0 }, /* (maybe) select pll mode */
{ 0xff80, nve0_clock_prog_4_1 },
};
int i, j;
for (i = 0; i < ARRAY_SIZE(stage); i++) {
for (j = 0; j < ARRAY_SIZE(priv->eng); j++) {
if (!(stage[i].mask & (1 << j)))
continue;
if (!priv->eng[j].freq)
continue;
stage[i].exec(priv, j);
}
}
return 0;
}
static void
nve0_clock_tidy(struct nouveau_clock *clk)
{
struct nve0_clock_priv *priv = (void *)clk;
memset(priv->eng, 0x00, sizeof(priv->eng));
}
static struct nouveau_clocks
nve0_domain[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
{ nv_clk_src_gpc , 0x00, NVKM_CLK_DOM_FLAG_CORE, "core", 2000 },
{ nv_clk_src_hubk07 , 0x01, NVKM_CLK_DOM_FLAG_CORE },
{ nv_clk_src_rop , 0x02, NVKM_CLK_DOM_FLAG_CORE },
{ nv_clk_src_mem , 0x03, 0, "memory", 1000 },
{ nv_clk_src_hubk06 , 0x04, NVKM_CLK_DOM_FLAG_CORE },
{ nv_clk_src_hubk01 , 0x05 },
{ nv_clk_src_vdec , 0x06 },
{ nv_clk_src_daemon , 0x07 },
{ nv_clk_src_max }
};
static int
nve0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nve0_clock_priv *priv;
int ret;
ret = nouveau_clock_create(parent, engine, oclass, nve0_domain, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->base.read = nve0_clock_read;
priv->base.calc = nve0_clock_calc;
priv->base.prog = nve0_clock_prog;
priv->base.tidy = nve0_clock_tidy;
return 0;
}
struct nouveau_oclass
nve0_clock_oclass = {
.handle = NV_SUBDEV(CLOCK, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nve0_clock_ctor,
.dtor = _nouveau_clock_dtor,
.init = _nouveau_clock_init,
.fini = _nouveau_clock_fini,
},
};
drivers/gpu/drm/nouveau/core/subdev/clock/pllnv04.c
View file @ 7c856522
......@@ -230,10 +230,12 @@ nv04_pll_calc(struct nouveau_subdev *subdev, struct nvbios_pll *info, u32 freq,
{
int ret;
if (!info->vco2.max_freq) {
if (!info->vco2.max_freq || !N2) {
ret = getMNP_single(subdev, info, freq, N1, M1, P);
if (N2) {
*N2 = 1;
*M2 = 1;
}
} else {
ret = getMNP_double(subdev, info, freq, N1, M1, N2, M2, P);
}
......
drivers/gpu/drm/nouveau/core/subdev/clock/seq.h 0 → 100644
View file @ 7c856522
#ifndef __NVKM_CLK_SEQ_H__
#define __NVKM_CLK_SEQ_H__
#include <subdev/bus.h>
#include <subdev/bus/hwsq.h>
#define clk_init(s,p) hwsq_init(&(s)->base, (p))
#define clk_exec(s,e) hwsq_exec(&(s)->base, (e))
#define clk_have(s,r) ((s)->r_##r.addr != 0x000000)
#define clk_rd32(s,r) hwsq_rd32(&(s)->base, &(s)->r_##r)
#define clk_wr32(s,r,d) hwsq_wr32(&(s)->base, &(s)->r_##r, (d))
#define clk_mask(s,r,m,d) hwsq_mask(&(s)->base, &(s)->r_##r, (m), (d))
#define clk_setf(s,f,d) hwsq_setf(&(s)->base, (f), (d))
#define clk_wait(s,f,d) hwsq_wait(&(s)->base, (f), (d))
#define clk_nsec(s,n) hwsq_nsec(&(s)->base, (n))
#endif
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