Commit 89d1f725 authored by Fabrice Gasnier's avatar Fabrice Gasnier Committed by Jonathan Cameron

iio: adc: stm32-adc: adapt clock duty cycle for proper operation

For proper operation, STM32 ADC should be used with a clock duty cycle
of 50%, in the range of 49% to 51%. Depending on the clock tree, divider
can be used in case clock duty cycle is out of this range.
In case clk_get_scaled_duty_cycle() returns an error, kindly apply a
divider by default (don't make the probe fail).
Signed-off-by: default avatarFabrice Gasnier <fabrice.gasnier@st.com>
Link: https://lore.kernel.org/r/1604681846-31234-1-git-send-email-fabrice.gasnier@st.comSigned-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
parent 8dedcc3e
...@@ -202,7 +202,7 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev, ...@@ -202,7 +202,7 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev,
{ {
u32 ckmode, presc, val; u32 ckmode, presc, val;
unsigned long rate; unsigned long rate;
int i, div; int i, div, duty;
/* stm32h7 bus clock is common for all ADC instances (mandatory) */ /* stm32h7 bus clock is common for all ADC instances (mandatory) */
if (!priv->bclk) { if (!priv->bclk) {
...@@ -226,6 +226,11 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev, ...@@ -226,6 +226,11 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev,
return -EINVAL; return -EINVAL;
} }
/* If duty is an error, kindly use at least /2 divider */
duty = clk_get_scaled_duty_cycle(priv->aclk, 100);
if (duty < 0)
dev_warn(&pdev->dev, "adc clock duty: %d\n", duty);
for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
presc = stm32h7_adc_ckmodes_spec[i].presc; presc = stm32h7_adc_ckmodes_spec[i].presc;
...@@ -234,6 +239,13 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev, ...@@ -234,6 +239,13 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev,
if (ckmode) if (ckmode)
continue; continue;
/*
* For proper operation, clock duty cycle range is 49%
* to 51%. Apply at least /2 prescaler otherwise.
*/
if (div == 1 && (duty < 49 || duty > 51))
continue;
if ((rate / div) <= priv->max_clk_rate) if ((rate / div) <= priv->max_clk_rate)
goto out; goto out;
} }
...@@ -246,6 +258,10 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev, ...@@ -246,6 +258,10 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev,
return -EINVAL; return -EINVAL;
} }
duty = clk_get_scaled_duty_cycle(priv->bclk, 100);
if (duty < 0)
dev_warn(&pdev->dev, "bus clock duty: %d\n", duty);
for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
presc = stm32h7_adc_ckmodes_spec[i].presc; presc = stm32h7_adc_ckmodes_spec[i].presc;
...@@ -254,6 +270,9 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev, ...@@ -254,6 +270,9 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev,
if (!ckmode) if (!ckmode)
continue; continue;
if (div == 1 && (duty < 49 || duty > 51))
continue;
if ((rate / div) <= priv->max_clk_rate) if ((rate / div) <= priv->max_clk_rate)
goto out; goto out;
} }
......
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