Commit 9024fb08 authored by Lang Yu's avatar Lang Yu Committed by Alex Deucher

drm/amd/display: fix 64-bit division issue on 32-bit OS

Replace "/" with div_u64 for 32-bit OS. On 32-bit OS,
the use of "/" for 64-bit division will cause build error,
i.e. "__udivdi3/__divdi3 undefined!".

Fixes: ea7154d8 ("drm/amd/display: Update dcn30_apply_idle_power_optimizations() code")
Signed-off-by: default avatarLang Yu <Lang.Yu@amd.com>
Acked-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d80d3da9
...@@ -772,8 +772,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) ...@@ -772,8 +772,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
cursor_cache_enable ? &cursor_attr : NULL)) { cursor_cache_enable ? &cursor_attr : NULL)) {
unsigned int v_total = stream->adjust.v_total_max ? unsigned int v_total = stream->adjust.v_total_max ?
stream->adjust.v_total_max : stream->timing.v_total; stream->adjust.v_total_max : stream->timing.v_total;
unsigned int refresh_hz = (unsigned long long) stream->timing.pix_clk_100hz * unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz *
100LL / (v_total * stream->timing.h_total); 100LL, (v_total * stream->timing.h_total));
/* /*
* one frame time in microsec: * one frame time in microsec:
...@@ -800,8 +800,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) ...@@ -800,8 +800,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
unsigned int denom = refresh_hz * 6528; unsigned int denom = refresh_hz * 6528;
unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us; unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us;
tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) * tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
(100LL + dc->debug.mall_additional_timer_percent) + denom - 1) / (100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
denom) - 64LL; denom) - 64LL;
/* scale should be increased until it fits into 6 bits */ /* scale should be increased until it fits into 6 bits */
...@@ -815,8 +815,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) ...@@ -815,8 +815,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
} }
denom *= 2; denom *= 2;
tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) * tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
(100LL + dc->debug.mall_additional_timer_percent) + denom - 1) / (100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
denom) - 64LL; denom) - 64LL;
} }
......
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