Commit a8ffeac9 authored by Christian König's avatar Christian König Committed by Alex Deucher

drm/amdgpu: use 2MB fragment size for GFX6,7 and 8

Use 2MB fragment size by default for older hardware generations as well.
Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Acked-by: default avatarJohn Bridgman <john.bridgman@amd.com>
Reviewed-by: default avatarRoger He <Hongbo.He@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fd4495e5
...@@ -831,7 +831,7 @@ static int gmc_v6_0_sw_init(void *handle) ...@@ -831,7 +831,7 @@ static int gmc_v6_0_sw_init(void *handle)
if (r) if (r)
return r; return r;
amdgpu_vm_adjust_size(adev, 64, 4); amdgpu_vm_adjust_size(adev, 64, 9);
adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
adev->mc.mc_mask = 0xffffffffffULL; adev->mc.mc_mask = 0xffffffffffULL;
......
...@@ -970,7 +970,7 @@ static int gmc_v7_0_sw_init(void *handle) ...@@ -970,7 +970,7 @@ static int gmc_v7_0_sw_init(void *handle)
* Currently set to 4GB ((1 << 20) 4k pages). * Currently set to 4GB ((1 << 20) 4k pages).
* Max GPUVM size for cayman and SI is 40 bits. * Max GPUVM size for cayman and SI is 40 bits.
*/ */
amdgpu_vm_adjust_size(adev, 64, 4); amdgpu_vm_adjust_size(adev, 64, 9);
adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
/* Set the internal MC address mask /* Set the internal MC address mask
......
...@@ -1067,7 +1067,7 @@ static int gmc_v8_0_sw_init(void *handle) ...@@ -1067,7 +1067,7 @@ static int gmc_v8_0_sw_init(void *handle)
* Currently set to 4GB ((1 << 20) 4k pages). * Currently set to 4GB ((1 << 20) 4k pages).
* Max GPUVM size for cayman and SI is 40 bits. * Max GPUVM size for cayman and SI is 40 bits.
*/ */
amdgpu_vm_adjust_size(adev, 64, 4); amdgpu_vm_adjust_size(adev, 64, 9);
adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
/* Set the internal MC address mask /* Set the internal MC address mask
......
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