Commit aa44beb5 authored by Jane Jian's avatar Jane Jian Committed by Alex Deucher

drm/amdgpu/vcn: Add sriov VCN v4_0 unified queue support

Enable unified queue support for sriov, abandon all previous
multi-queue settings
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarJane Jian <Jane.Jian@amd.com>
Reviewed-by: default avatarRuijing Dong <ruijing.dong@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 60e9c7ee
...@@ -1908,10 +1908,9 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) ...@@ -1908,10 +1908,9 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(4, 0, 0): case IP_VERSION(4, 0, 0):
case IP_VERSION(4, 0, 2): case IP_VERSION(4, 0, 2):
case IP_VERSION(4, 0, 4): case IP_VERSION(4, 0, 4):
if (!amdgpu_sriov_vf(adev)) { amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block);
amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); if (!amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block);
}
break; break;
default: default:
dev_err(adev->dev, dev_err(adev->dev,
......
...@@ -161,6 +161,7 @@ ...@@ -161,6 +161,7 @@
#define AMDGPU_VCN_SW_RING_FLAG (1 << 9) #define AMDGPU_VCN_SW_RING_FLAG (1 << 9)
#define AMDGPU_VCN_FW_LOGGING_FLAG (1 << 10) #define AMDGPU_VCN_FW_LOGGING_FLAG (1 << 10)
#define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11) #define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11)
#define AMDGPU_VCN_VF_RB_SETUP_FLAG (1 << 12)
#define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER 0x00000001 #define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER 0x00000001
#define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER 0x00000001 #define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER 0x00000001
...@@ -317,12 +318,24 @@ struct amdgpu_fw_shared { ...@@ -317,12 +318,24 @@ struct amdgpu_fw_shared {
struct amdgpu_fw_shared_smu_interface_info smu_interface_info; struct amdgpu_fw_shared_smu_interface_info smu_interface_info;
}; };
struct amdgpu_fw_shared_rb_setup {
uint32_t is_rb_enabled_flags;
uint32_t rb_addr_lo;
uint32_t rb_addr_hi;
uint32_t rb_size;
uint32_t rb4_addr_lo;
uint32_t rb4_addr_hi;
uint32_t rb4_size;
uint32_t reserved[6];
};
struct amdgpu_vcn4_fw_shared { struct amdgpu_vcn4_fw_shared {
uint32_t present_flag_0; uint32_t present_flag_0;
uint8_t pad[12]; uint8_t pad[12];
struct amdgpu_fw_shared_unified_queue_struct sq; struct amdgpu_fw_shared_unified_queue_struct sq;
uint8_t pad1[8]; uint8_t pad1[8];
struct amdgpu_fw_shared_fw_logging fw_log; struct amdgpu_fw_shared_fw_logging fw_log;
struct amdgpu_fw_shared_rb_setup rb_setup;
}; };
struct amdgpu_vcn_fwlog { struct amdgpu_vcn_fwlog {
......
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