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Commit b2e0059b authored by Jani Nikula's avatar Jani Nikula
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drm/i915/de: register wait function renames 

Do some renames on the register wait functions for clarity and brevity:

intel_de_wait_for_register	-> intel_de_wait
intel_de_wait_for_register_fw	-> intel_de_wait_fw
__intel_de_wait_for_register	-> intel_de_wait_custom

In particular, it seemed odd to have a double-underscored function be
called in a number of places.
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240320160123.2904609-1-jani.nikula@intel.com
parent 1bfc03b1
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Showing with 58 additions and 64 deletions
drivers/gpu/drm/i915/display/intel_cx0_phy.c
View file @ b2e0059b
...@@ -151,7 +151,7 @@ static int intel_cx0_wait_for_ack(struct intel_encoder *encoder, ...@@ -151,7 +151,7 @@ static int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
enum port port = encoder->port; enum port port = encoder->port;
enum phy phy = intel_encoder_to_phy(encoder); enum phy phy = intel_encoder_to_phy(encoder);
if (__intel_de_wait_for_register(i915, if (intel_de_wait_custom(i915,
XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane), XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane),
XELPDP_PORT_P2M_RESPONSE_READY, XELPDP_PORT_P2M_RESPONSE_READY,
XELPDP_PORT_P2M_RESPONSE_READY, XELPDP_PORT_P2M_RESPONSE_READY,
...@@ -2545,7 +2545,7 @@ static void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder, ...@@ -2545,7 +2545,7 @@ static void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
intel_cx0_get_powerdown_update(lane_mask)); intel_cx0_get_powerdown_update(lane_mask));
/* Update Timeout Value */ /* Update Timeout Value */
if (__intel_de_wait_for_register(i915, buf_ctl2_reg, if (intel_de_wait_custom(i915, buf_ctl2_reg,
intel_cx0_get_powerdown_update(lane_mask), 0, intel_cx0_get_powerdown_update(lane_mask), 0,
XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL)) XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n", drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
...@@ -2605,7 +2605,7 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder, ...@@ -2605,7 +2605,7 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
XELPDP_LANE_PHY_CURRENT_STATUS(1)) XELPDP_LANE_PHY_CURRENT_STATUS(1))
: XELPDP_LANE_PHY_CURRENT_STATUS(0); : XELPDP_LANE_PHY_CURRENT_STATUS(0);
if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(i915, port), if (intel_de_wait_custom(i915, XELPDP_PORT_BUF_CTL1(i915, port),
XELPDP_PORT_BUF_SOC_PHY_READY, XELPDP_PORT_BUF_SOC_PHY_READY,
XELPDP_PORT_BUF_SOC_PHY_READY, XELPDP_PORT_BUF_SOC_PHY_READY,
XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL)) XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
...@@ -2615,7 +2615,7 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder, ...@@ -2615,7 +2615,7 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port), lane_pipe_reset, intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port), lane_pipe_reset,
lane_pipe_reset); lane_pipe_reset);
if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(i915, port), if (intel_de_wait_custom(i915, XELPDP_PORT_BUF_CTL2(i915, port),
lane_phy_current_status, lane_phy_current_status, lane_phy_current_status, lane_phy_current_status,
XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL)) XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))
drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n", drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
...@@ -2625,7 +2625,7 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder, ...@@ -2625,7 +2625,7 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
intel_cx0_get_pclk_refclk_request(owned_lane_mask), intel_cx0_get_pclk_refclk_request(owned_lane_mask),
intel_cx0_get_pclk_refclk_request(lane_mask)); intel_cx0_get_pclk_refclk_request(lane_mask));
if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, port), if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, port),
intel_cx0_get_pclk_refclk_ack(owned_lane_mask), intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
intel_cx0_get_pclk_refclk_ack(lane_mask), intel_cx0_get_pclk_refclk_ack(lane_mask),
XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL)) XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
...@@ -2778,7 +2778,7 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder, ...@@ -2778,7 +2778,7 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
intel_cx0_get_pclk_pll_request(maxpclk_lane)); intel_cx0_get_pclk_pll_request(maxpclk_lane));
/* 10. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */ /* 10. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES), intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
intel_cx0_get_pclk_pll_ack(maxpclk_lane), intel_cx0_get_pclk_pll_ack(maxpclk_lane),
XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL)) XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL))
...@@ -2869,7 +2869,7 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder, ...@@ -2869,7 +2869,7 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), val); intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), val);
/* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */ /* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
XELPDP_TBT_CLOCK_ACK, XELPDP_TBT_CLOCK_ACK,
XELPDP_TBT_CLOCK_ACK, XELPDP_TBT_CLOCK_ACK,
100, 0, NULL)) 100, 0, NULL))
...@@ -2931,7 +2931,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder) ...@@ -2931,7 +2931,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
/* /*
* 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0". * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".
*/ */
if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) | intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0, intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL)) XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL))
...@@ -2969,7 +2969,7 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder) ...@@ -2969,7 +2969,7 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
XELPDP_TBT_CLOCK_REQUEST, 0); XELPDP_TBT_CLOCK_REQUEST, 0);
/* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */ /* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL)) XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL))
drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n", drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",
encoder->base.base.id, encoder->base.name, phy_name(phy)); encoder->base.base.id, encoder->base.name, phy_name(phy));
......
drivers/gpu/drm/i915/display/intel_de.h
View file @ b2e0059b
...@@ -48,21 +48,21 @@ intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set) ...@@ -48,21 +48,21 @@ intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
} }
static inline int static inline int
intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg, intel_de_wait(struct drm_i915_private *i915, i915_reg_t reg,
u32 mask, u32 value, unsigned int timeout) u32 mask, u32 value, unsigned int timeout)
{ {
return intel_wait_for_register(&i915->uncore, reg, mask, value, timeout); return intel_wait_for_register(&i915->uncore, reg, mask, value, timeout);
} }
static inline int static inline int
intel_de_wait_for_register_fw(struct drm_i915_private *i915, i915_reg_t reg, intel_de_wait_fw(struct drm_i915_private *i915, i915_reg_t reg,
u32 mask, u32 value, unsigned int timeout) u32 mask, u32 value, unsigned int timeout)
{ {
return intel_wait_for_register_fw(&i915->uncore, reg, mask, value, timeout); return intel_wait_for_register_fw(&i915->uncore, reg, mask, value, timeout);
} }
static inline int static inline int
__intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg, intel_de_wait_custom(struct drm_i915_private *i915, i915_reg_t reg,
u32 mask, u32 value, u32 mask, u32 value,
unsigned int fast_timeout_us, unsigned int fast_timeout_us,
unsigned int slow_timeout_ms, u32 *out_value) unsigned int slow_timeout_ms, u32 *out_value)
...@@ -75,14 +75,14 @@ static inline int ...@@ -75,14 +75,14 @@ static inline int
intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg, intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg,
u32 mask, unsigned int timeout) u32 mask, unsigned int timeout)
{ {
return intel_de_wait_for_register(i915, reg, mask, mask, timeout); return intel_de_wait(i915, reg, mask, mask, timeout);
} }
static inline int static inline int
intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg, intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
u32 mask, unsigned int timeout) u32 mask, unsigned int timeout)
{ {
return intel_de_wait_for_register(i915, reg, mask, 0, timeout); return intel_de_wait(i915, reg, mask, 0, timeout);
} }
/* /*
......
drivers/gpu/drm/i915/display/intel_display.c
View file @ b2e0059b
...@@ -383,8 +383,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, ...@@ -383,8 +383,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
break; break;
} }
if (intel_de_wait_for_register(dev_priv, dpll_reg, if (intel_de_wait(dev_priv, dpll_reg, port_mask, expected_mask, 1000))
port_mask, expected_mask, 1000))
drm_WARN(&dev_priv->drm, 1, drm_WARN(&dev_priv->drm, 1,
"timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
dig_port->base.base.base.id, dig_port->base.base.name, dig_port->base.base.base.id, dig_port->base.base.name,
......
drivers/gpu/drm/i915/display/intel_display_power_well.c
View file @ b2e0059b
...@@ -1390,7 +1390,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv) ...@@ -1390,7 +1390,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
* The PHY may be busy with some initial calibration and whatnot, * The PHY may be busy with some initial calibration and whatnot,
* so the power state can take a while to actually change. * so the power state can take a while to actually change.
*/ */
if (intel_de_wait_for_register(dev_priv, DISPLAY_PHY_STATUS, if (intel_de_wait(dev_priv, DISPLAY_PHY_STATUS,
phy_status_mask, phy_status, 10)) phy_status_mask, phy_status, 10))
drm_err(&dev_priv->drm, drm_err(&dev_priv->drm,
"Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
......
drivers/gpu/drm/i915/display/intel_dp_aux.c
View file @ b2e0059b
...@@ -61,8 +61,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp) ...@@ -61,8 +61,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
u32 status; u32 status;
int ret; int ret;
ret = __intel_de_wait_for_register(i915, ch_ctl, ret = intel_de_wait_custom(i915, ch_ctl, DP_AUX_CH_CTL_SEND_BUSY, 0,
DP_AUX_CH_CTL_SEND_BUSY, 0,
2, timeout_ms, &status); 2, timeout_ms, &status);
if (ret == -ETIMEDOUT) if (ret == -ETIMEDOUT)
......
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
View file @ b2e0059b
...@@ -766,10 +766,8 @@ intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector, ...@@ -766,10 +766,8 @@ intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector,
return -EINVAL; return -EINVAL;
/* Wait for encryption confirmation */ /* Wait for encryption confirmation */
if (intel_de_wait_for_register(i915, if (intel_de_wait(i915, HDCP_STATUS(i915, cpu_transcoder, port),
HDCP_STATUS(i915, cpu_transcoder, port), stream_enc_status, enable ? stream_enc_status : 0,
stream_enc_status,
enable ? stream_enc_status : 0,
HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n", drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled"); transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled");
...@@ -801,8 +799,7 @@ intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector, ...@@ -801,8 +799,7 @@ intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
return ret; return ret;
/* Wait for encryption confirmation */ /* Wait for encryption confirmation */
if (intel_de_wait_for_register(i915, if (intel_de_wait(i915, HDCP2_STREAM_STATUS(i915, cpu_transcoder, pipe),
HDCP2_STREAM_STATUS(i915, cpu_transcoder, pipe),
STREAM_ENCRYPTION_STATUS, STREAM_ENCRYPTION_STATUS,
enable ? STREAM_ENCRYPTION_STATUS : 0, enable ? STREAM_ENCRYPTION_STATUS : 0,
HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
......
drivers/gpu/drm/i915/display/intel_gmbus.c
View file @ b2e0059b
...@@ -411,7 +411,7 @@ gmbus_wait_idle(struct drm_i915_private *i915) ...@@ -411,7 +411,7 @@ gmbus_wait_idle(struct drm_i915_private *i915)
add_wait_queue(&i915->display.gmbus.wait_queue, &wait); add_wait_queue(&i915->display.gmbus.wait_queue, &wait);
intel_de_write_fw(i915, GMBUS4(i915), irq_enable); intel_de_write_fw(i915, GMBUS4(i915), irq_enable);
ret = intel_de_wait_for_register_fw(i915, GMBUS2(i915), GMBUS_ACTIVE, 0, 10); ret = intel_de_wait_fw(i915, GMBUS2(i915), GMBUS_ACTIVE, 0, 10);
intel_de_write_fw(i915, GMBUS4(i915), 0); intel_de_write_fw(i915, GMBUS4(i915), 0);
remove_wait_queue(&i915->display.gmbus.wait_queue, &wait); remove_wait_queue(&i915->display.gmbus.wait_queue, &wait);
......
drivers/gpu/drm/i915/display/intel_pps.c
View file @ b2e0059b
...@@ -605,8 +605,7 @@ static void wait_panel_status(struct intel_dp *intel_dp, ...@@ -605,8 +605,7 @@ static void wait_panel_status(struct intel_dp *intel_dp,
intel_de_read(dev_priv, pp_stat_reg), intel_de_read(dev_priv, pp_stat_reg),
intel_de_read(dev_priv, pp_ctrl_reg)); intel_de_read(dev_priv, pp_ctrl_reg));
if (intel_de_wait_for_register(dev_priv, pp_stat_reg, if (intel_de_wait(dev_priv, pp_stat_reg, mask, value, 5000))
mask, value, 5000))
drm_err(&dev_priv->drm, drm_err(&dev_priv->drm,
"[ENCODER:%d:%s] %s panel status timeout: PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", "[ENCODER:%d:%s] %s panel status timeout: PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
dig_port->base.base.base.id, dig_port->base.base.name, dig_port->base.base.base.id, dig_port->base.base.name,
......
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