Commit b4e7b0e8 authored by Kenneth Feng's avatar Kenneth Feng Committed by Alex Deucher

drm/amd/pm: enable gfxoff control on smu_v13_0_7

enable gfxoff control interface on smu_v13_0_7
Signed-off-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f5f79e32
...@@ -5193,6 +5193,7 @@ static int gfx_v11_0_set_powergating_state(void *handle, ...@@ -5193,6 +5193,7 @@ static int gfx_v11_0_set_powergating_state(void *handle,
switch (adev->ip_versions[GC_HWIP][0]) { switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(11, 0, 0): case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 2):
amdgpu_gfx_off_ctrl(adev, enable); amdgpu_gfx_off_ctrl(adev, enable);
break; break;
default: default:
......
...@@ -834,6 +834,7 @@ int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable) ...@@ -834,6 +834,7 @@ int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
case IP_VERSION(13, 0, 1): case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 3): case IP_VERSION(13, 0, 3):
case IP_VERSION(13, 0, 5): case IP_VERSION(13, 0, 5):
case IP_VERSION(13, 0, 7):
case IP_VERSION(13, 0, 8): case IP_VERSION(13, 0, 8):
if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
return 0; return 0;
......
...@@ -113,6 +113,8 @@ static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] = ...@@ -113,6 +113,8 @@ static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] =
MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
}; };
static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = { static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {
...@@ -1486,6 +1488,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { ...@@ -1486,6 +1488,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
.get_gpu_metrics = smu_v13_0_7_get_gpu_metrics, .get_gpu_metrics = smu_v13_0_7_get_gpu_metrics,
.set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range, .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range,
.set_performance_level = smu_v13_0_set_performance_level, .set_performance_level = smu_v13_0_set_performance_level,
.gfx_off_control = smu_v13_0_gfx_off_control,
.get_fan_speed_pwm = smu_v13_0_7_get_fan_speed_pwm, .get_fan_speed_pwm = smu_v13_0_7_get_fan_speed_pwm,
.get_fan_speed_rpm = smu_v13_0_7_get_fan_speed_rpm, .get_fan_speed_rpm = smu_v13_0_7_get_fan_speed_rpm,
.set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm, .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm,
......
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