Commit b720aaa3 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding

firmware: tf: Different way of L2 cache enabling after LP2 suspend

ASUS TF300T device may not work properly if firmware is asked to fully
re-initialize L2 cache after resume from LP2 suspend. The downstream
kernel of TF300T uses different opcode to enable cache after resuming
from LP2, this opcode also works fine on Nexus 7 and Ouya devices.
Supposedly, this may be needed by an older firmware versions.
Reported-by: default avatarMichał Mirosław <mirq-linux@rere.qmqm.pl>
Tested-by: default avatarMichał Mirosław <mirq-linux@rere.qmqm.pl>
Tested-by: default avatarJasper Korten <jja2000@gmail.com>
Tested-by: default avatarDavid Heidelberg <david@ixit.cz>
Tested-by: default avatarPeter Geis <pgwipeout@gmail.com>
Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent d70f5e54
...@@ -19,6 +19,7 @@ ...@@ -19,6 +19,7 @@
#define TF_CACHE_ENABLE 1 #define TF_CACHE_ENABLE 1
#define TF_CACHE_DISABLE 2 #define TF_CACHE_DISABLE 2
#define TF_CACHE_REENABLE 4
#define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200 #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200
...@@ -29,6 +30,7 @@ ...@@ -29,6 +30,7 @@
#define TF_CPU_PM_S1 0xffffffe4 #define TF_CPU_PM_S1 0xffffffe4
#define TF_CPU_PM_S1_NOFLUSH_L2 0xffffffe7 #define TF_CPU_PM_S1_NOFLUSH_L2 0xffffffe7
static unsigned long tf_idle_mode = TF_PM_MODE_NONE;
static unsigned long cpu_boot_addr; static unsigned long cpu_boot_addr;
static void tf_generic_smc(u32 type, u32 arg1, u32 arg2) static void tf_generic_smc(u32 type, u32 arg1, u32 arg2)
...@@ -85,25 +87,40 @@ static int tf_prepare_idle(unsigned long mode) ...@@ -85,25 +87,40 @@ static int tf_prepare_idle(unsigned long mode)
cpu_boot_addr); cpu_boot_addr);
break; break;
case TF_PM_MODE_NONE:
break;
default: default:
return -EINVAL; return -EINVAL;
} }
tf_idle_mode = mode;
return 0; return 0;
} }
#ifdef CONFIG_CACHE_L2X0 #ifdef CONFIG_CACHE_L2X0
static void tf_cache_write_sec(unsigned long val, unsigned int reg) static void tf_cache_write_sec(unsigned long val, unsigned int reg)
{ {
u32 l2x0_way_mask = 0xff; u32 enable_op, l2x0_way_mask = 0xff;
switch (reg) { switch (reg) {
case L2X0_CTRL: case L2X0_CTRL:
if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_ASSOCIATIVITY_16) if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_ASSOCIATIVITY_16)
l2x0_way_mask = 0xffff; l2x0_way_mask = 0xffff;
switch (tf_idle_mode) {
case TF_PM_MODE_LP2:
enable_op = TF_CACHE_REENABLE;
break;
default:
enable_op = TF_CACHE_ENABLE;
break;
}
if (val == L2X0_CTRL_EN) if (val == L2X0_CTRL_EN)
tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_ENABLE, tf_generic_smc(TF_CACHE_MAINT, enable_op,
l2x0_saved_regs.aux_ctrl); l2x0_saved_regs.aux_ctrl);
else else
tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_DISABLE, tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_DISABLE,
......
...@@ -32,6 +32,7 @@ ...@@ -32,6 +32,7 @@
#define TF_PM_MODE_LP1_NO_MC_CLK 2 #define TF_PM_MODE_LP1_NO_MC_CLK 2
#define TF_PM_MODE_LP2 3 #define TF_PM_MODE_LP2 3
#define TF_PM_MODE_LP2_NOFLUSH_L2 4 #define TF_PM_MODE_LP2_NOFLUSH_L2 4
#define TF_PM_MODE_NONE 5
struct trusted_foundations_platform_data { struct trusted_foundations_platform_data {
unsigned int version_major; unsigned int version_major;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment