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Commit b9c1ea40 authored by Lijun Ou's avatar Lijun Ou Committed by Jason Gunthorpe
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RDMA/hns: Refactor the codes for setting transport opode 

Currently the transport opcodes which come from users configuration is set
by similar code. This patch simplifies it.
Signed-off-by: default avatarLijun Ou <oulijun@huawei.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@mellanox.com>
parent 6c854111
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Inline Side-by-side
Showing with 18 additions and 48 deletions
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
View file @ b9c1ea40
...@@ -191,6 +191,7 @@ static int hns_roce_v2_post_send(struct ib_qp *ibqp, ...@@ -191,6 +191,7 @@ static int hns_roce_v2_post_send(struct ib_qp *ibqp,
int attr_mask; int attr_mask;
u32 tmp_len; u32 tmp_len;
int ret = 0; int ret = 0;
u32 hr_op;
u8 *smac; u8 *smac;
int nreq; int nreq;
int i; int i;
...@@ -408,91 +409,60 @@ static int hns_roce_v2_post_send(struct ib_qp *ibqp, ...@@ -408,91 +409,60 @@ static int hns_roce_v2_post_send(struct ib_qp *ibqp,
switch (wr->opcode) { switch (wr->opcode) {
case IB_WR_RDMA_READ: case IB_WR_RDMA_READ:
roce_set_field(rc_sq_wqe->byte_4, hr_op = HNS_ROCE_V2_WQE_OP_RDMA_READ;
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
HNS_ROCE_V2_WQE_OP_RDMA_READ);
rc_sq_wqe->rkey = rc_sq_wqe->rkey =
cpu_to_le32(rdma_wr(wr)->rkey); cpu_to_le32(rdma_wr(wr)->rkey);
rc_sq_wqe->va = rc_sq_wqe->va =
cpu_to_le64(rdma_wr(wr)->remote_addr); cpu_to_le64(rdma_wr(wr)->remote_addr);
break; break;
case IB_WR_RDMA_WRITE: case IB_WR_RDMA_WRITE:
roce_set_field(rc_sq_wqe->byte_4, hr_op = HNS_ROCE_V2_WQE_OP_RDMA_WRITE;
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
HNS_ROCE_V2_WQE_OP_RDMA_WRITE);
rc_sq_wqe->rkey = rc_sq_wqe->rkey =
cpu_to_le32(rdma_wr(wr)->rkey); cpu_to_le32(rdma_wr(wr)->rkey);
rc_sq_wqe->va = rc_sq_wqe->va =
cpu_to_le64(rdma_wr(wr)->remote_addr); cpu_to_le64(rdma_wr(wr)->remote_addr);
break; break;
case IB_WR_RDMA_WRITE_WITH_IMM: case IB_WR_RDMA_WRITE_WITH_IMM:
roce_set_field(rc_sq_wqe->byte_4, hr_op = HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM;
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM);
rc_sq_wqe->rkey = rc_sq_wqe->rkey =
cpu_to_le32(rdma_wr(wr)->rkey); cpu_to_le32(rdma_wr(wr)->rkey);
rc_sq_wqe->va = rc_sq_wqe->va =
cpu_to_le64(rdma_wr(wr)->remote_addr); cpu_to_le64(rdma_wr(wr)->remote_addr);
break; break;
case IB_WR_SEND: case IB_WR_SEND:
roce_set_field(rc_sq_wqe->byte_4, hr_op = HNS_ROCE_V2_WQE_OP_SEND;
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
HNS_ROCE_V2_WQE_OP_SEND);
break; break;
case IB_WR_SEND_WITH_INV: case IB_WR_SEND_WITH_INV:
roce_set_field(rc_sq_wqe->byte_4, hr_op = HNS_ROCE_V2_WQE_OP_SEND_WITH_INV;
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
HNS_ROCE_V2_WQE_OP_SEND_WITH_INV);
break; break;
case IB_WR_SEND_WITH_IMM: case IB_WR_SEND_WITH_IMM:
roce_set_field(rc_sq_wqe->byte_4, hr_op = HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM;
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM);
break; break;
case IB_WR_LOCAL_INV: case IB_WR_LOCAL_INV:
roce_set_field(rc_sq_wqe->byte_4, hr_op = HNS_ROCE_V2_WQE_OP_LOCAL_INV;
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
HNS_ROCE_V2_WQE_OP_LOCAL_INV);
break; break;
case IB_WR_ATOMIC_CMP_AND_SWP: case IB_WR_ATOMIC_CMP_AND_SWP:
roce_set_field(rc_sq_wqe->byte_4, hr_op = HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP;
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP);
break; break;
case IB_WR_ATOMIC_FETCH_AND_ADD: case IB_WR_ATOMIC_FETCH_AND_ADD:
roce_set_field(rc_sq_wqe->byte_4, hr_op = HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD;
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD);
break; break;
case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
roce_set_field(rc_sq_wqe->byte_4, hr_op =
V2_RC_SEND_WQE_BYTE_4_OPCODE_M, HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP;
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP);
break; break;
case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD: case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
roce_set_field(rc_sq_wqe->byte_4, hr_op =
V2_RC_SEND_WQE_BYTE_4_OPCODE_M, HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD;
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD);
break; break;
default: default:
roce_set_field(rc_sq_wqe->byte_4, hr_op = HNS_ROCE_V2_WQE_OP_MASK;
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
HNS_ROCE_V2_WQE_OP_MASK);
break; break;
} }
roce_set_field(rc_sq_wqe->byte_4,
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
V2_RC_SEND_WQE_BYTE_4_OPCODE_S, hr_op);
wqe += sizeof(struct hns_roce_v2_rc_send_wqe); wqe += sizeof(struct hns_roce_v2_rc_send_wqe);
ret = set_rwqe_data_seg(ibqp, wr, rc_sq_wqe, wqe, ret = set_rwqe_data_seg(ibqp, wr, rc_sq_wqe, wqe,
......
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