Commit bc9bec3c authored by Tom Rini's avatar Tom Rini Committed by Linus Torvalds

[PATCH] ppc32: remove cli()/sti() in arch/ppc/syslib/qspan_pci.c

Replace save_flags()/resore_flags() with spin_lock_irqsave() /
spin_unlock_irqrestore() and document reasons for locking in the Qspan PCI
code.
Signed-off-by: default avatarJames Nelson <james4765@gmail.com>
Signed-off-by: default avatarTom Rini <trini@kernel.crashing.org>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 61b2b514
...@@ -94,6 +94,8 @@ ...@@ -94,6 +94,8 @@
#define mk_config_type1(bus, dev, offset) \ #define mk_config_type1(bus, dev, offset) \
mk_config_addr(bus, dev, offset) | 1; mk_config_addr(bus, dev, offset) | 1;
static spinlock_t pcibios_lock = SPIN_LOCK_UNLOCKED;
int qspan_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn, int qspan_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn,
unsigned char offset, unsigned char *val) unsigned char offset, unsigned char *val)
{ {
...@@ -109,8 +111,8 @@ int qspan_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn, ...@@ -109,8 +111,8 @@ int qspan_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn,
} }
#ifdef CONFIG_RPXCLASSIC #ifdef CONFIG_RPXCLASSIC
save_flags(flags); /* disable interrupts */
cli(); spin_lock_irqsave(&pcibios_lock, flags);
*((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL; *((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
eieio(); eieio();
#endif #endif
...@@ -124,7 +126,7 @@ int qspan_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn, ...@@ -124,7 +126,7 @@ int qspan_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn,
#ifdef CONFIG_RPXCLASSIC #ifdef CONFIG_RPXCLASSIC
*((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL; *((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
eieio(); eieio();
restore_flags(flags); spin_unlock_irqrestore(&pcibios_lock, flags);
#endif #endif
offset ^= 0x03; offset ^= 0x03;
...@@ -148,8 +150,8 @@ int qspan_pcibios_read_config_word(unsigned char bus, unsigned char dev_fn, ...@@ -148,8 +150,8 @@ int qspan_pcibios_read_config_word(unsigned char bus, unsigned char dev_fn,
} }
#ifdef CONFIG_RPXCLASSIC #ifdef CONFIG_RPXCLASSIC
save_flags(flags); /* disable interrupts */
cli(); spin_lock_irqsave(&pcibios_lock, flags);
*((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL; *((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
eieio(); eieio();
#endif #endif
...@@ -164,7 +166,7 @@ int qspan_pcibios_read_config_word(unsigned char bus, unsigned char dev_fn, ...@@ -164,7 +166,7 @@ int qspan_pcibios_read_config_word(unsigned char bus, unsigned char dev_fn,
#ifdef CONFIG_RPXCLASSIC #ifdef CONFIG_RPXCLASSIC
*((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL; *((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
eieio(); eieio();
restore_flags(flags); spin_unlock_irqrestore(&pcibios_lock, flags);
#endif #endif
sp = ((ushort *)&temp) + ((offset >> 1) & 1); sp = ((ushort *)&temp) + ((offset >> 1) & 1);
...@@ -185,8 +187,8 @@ int qspan_pcibios_read_config_dword(unsigned char bus, unsigned char dev_fn, ...@@ -185,8 +187,8 @@ int qspan_pcibios_read_config_dword(unsigned char bus, unsigned char dev_fn,
} }
#ifdef CONFIG_RPXCLASSIC #ifdef CONFIG_RPXCLASSIC
save_flags(flags); /* disable interrupts */
cli(); spin_lock_irqsave(&pcibios_lock, flags);
*((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL; *((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
eieio(); eieio();
#endif #endif
...@@ -200,7 +202,7 @@ int qspan_pcibios_read_config_dword(unsigned char bus, unsigned char dev_fn, ...@@ -200,7 +202,7 @@ int qspan_pcibios_read_config_dword(unsigned char bus, unsigned char dev_fn,
#ifdef CONFIG_RPXCLASSIC #ifdef CONFIG_RPXCLASSIC
*((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL; *((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
eieio(); eieio();
restore_flags(flags); spin_unlock_irqrestore(&pcibios_lock, flags);
#endif #endif
return PCIBIOS_SUCCESSFUL; return PCIBIOS_SUCCESSFUL;
...@@ -225,8 +227,8 @@ int qspan_pcibios_write_config_byte(unsigned char bus, unsigned char dev_fn, ...@@ -225,8 +227,8 @@ int qspan_pcibios_write_config_byte(unsigned char bus, unsigned char dev_fn,
*cp = val; *cp = val;
#ifdef CONFIG_RPXCLASSIC #ifdef CONFIG_RPXCLASSIC
save_flags(flags); /* disable interrupts */
cli(); spin_lock_irqsave(&pcibios_lock, flags);
*((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL; *((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
eieio(); eieio();
#endif #endif
...@@ -240,7 +242,7 @@ int qspan_pcibios_write_config_byte(unsigned char bus, unsigned char dev_fn, ...@@ -240,7 +242,7 @@ int qspan_pcibios_write_config_byte(unsigned char bus, unsigned char dev_fn,
#ifdef CONFIG_RPXCLASSIC #ifdef CONFIG_RPXCLASSIC
*((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL; *((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
eieio(); eieio();
restore_flags(flags); spin_unlock_irqrestore(&pcibios_lock, flags);
#endif #endif
return PCIBIOS_SUCCESSFUL; return PCIBIOS_SUCCESSFUL;
...@@ -265,8 +267,8 @@ int qspan_pcibios_write_config_word(unsigned char bus, unsigned char dev_fn, ...@@ -265,8 +267,8 @@ int qspan_pcibios_write_config_word(unsigned char bus, unsigned char dev_fn,
*sp = val; *sp = val;
#ifdef CONFIG_RPXCLASSIC #ifdef CONFIG_RPXCLASSIC
save_flags(flags); /* disable interrupts */
cli(); spin_lock_irqsave(&pcibios_lock, flags);
*((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL; *((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
eieio(); eieio();
#endif #endif
...@@ -280,7 +282,7 @@ int qspan_pcibios_write_config_word(unsigned char bus, unsigned char dev_fn, ...@@ -280,7 +282,7 @@ int qspan_pcibios_write_config_word(unsigned char bus, unsigned char dev_fn,
#ifdef CONFIG_RPXCLASSIC #ifdef CONFIG_RPXCLASSIC
*((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL; *((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
eieio(); eieio();
restore_flags(flags); spin_unlock_irqrestore(&pcibios_lock, flags);
#endif #endif
return PCIBIOS_SUCCESSFUL; return PCIBIOS_SUCCESSFUL;
...@@ -297,8 +299,8 @@ int qspan_pcibios_write_config_dword(unsigned char bus, unsigned char dev_fn, ...@@ -297,8 +299,8 @@ int qspan_pcibios_write_config_dword(unsigned char bus, unsigned char dev_fn,
return PCIBIOS_DEVICE_NOT_FOUND; return PCIBIOS_DEVICE_NOT_FOUND;
#ifdef CONFIG_RPXCLASSIC #ifdef CONFIG_RPXCLASSIC
save_flags(flags); /* disable interrupts */
cli(); spin_lock_irqsave(&pcibios_lock, flags);
*((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL; *((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
eieio(); eieio();
#endif #endif
...@@ -312,7 +314,7 @@ int qspan_pcibios_write_config_dword(unsigned char bus, unsigned char dev_fn, ...@@ -312,7 +314,7 @@ int qspan_pcibios_write_config_dword(unsigned char bus, unsigned char dev_fn,
#ifdef CONFIG_RPXCLASSIC #ifdef CONFIG_RPXCLASSIC
*((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL; *((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
eieio(); eieio();
restore_flags(flags); spin_unlock_irqrestore(&pcibios_lock, flags);
#endif #endif
return PCIBIOS_SUCCESSFUL; return PCIBIOS_SUCCESSFUL;
......
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