[ARM PATCH] 2297/1: SMC91x patch (#2) for LPD7a40x CardEngines

Patch from Marc Singer

Add support for the LPD7a40x implementation of the SMC91x ethernet
controller. This patch exists to work around a mismatch between the
way the LH7a40x CPUs handle chip selects and what the ethernet
controller expects.

This patch has been revised to eliminate masking of interrupts.  The
concessions are that 

  a) the ISR must perform an IOBARRIER before the first access to the
     chip, just in case the interrupt occurred while the driver was
     writing to the chip
  b) other drivers that use the same chip select region as the SMC
     chip must perform a similar IOBARRIER at the top of their ISRs.

Signed-off-by: Marc Singer
Signed-off-by: Russell King

Documentation/arm/Sharp-LH/IOBarrier

@@ -5,7 +5,7 @@ Due to an unfortunate oversight when the Card Engines were designed,
 the signals that control access to some peripherals, most notably the
 SMC91C9111 ethernet controller, are not properly handled.
 
-The symptom is that back to back IO with the peripheral returns
+The symptom is that some back to back IO with the peripheral returns
 unreliable data.  With the SMC chip, you'll see errors about the bank
 register being 'screwed'.
 
@@ -13,20 +13,33 @@ The cause is that the AEN signal to the SMC chip does not transition
 for every memory access.  It is driven through the CPLD from the CS7
 line of the CPU's static memory controller which is optimized to
 eliminate unnecessary transitions.  Yet, the SMC requires a transition
-for every access.  The Sharp website has more information on the
-effect of this power conservation feature on peripheral interfacing.
+for every write access.  The Sharp website has more information about
+the effect this power-conserving feature has on peripheral
+interfacing.
 
-The solution is to follow every access to the SMC chip with an access
-to another memory region that will force the CPU to release the chip
-select line.  Note that it is important to guarantee that the access
-will force the CPU off-chip.  We map a page of SDRAM as if it were an
-uncacheable IO device and read from it after every SMC IO operation.
+The solution is to follow every write access to the SMC chip with an
+access to another memory region that will force the CPU to release the
+chip select line.  It is important to guarantee that this access
+forces the CPU off-chip.  We map a page of SDRAM as if it were an
+uncacheable IO device and read from it after every SMC IO write
+operation.
 
   SMC IO
   BARRIER IO
 
-You might be tempted to believe that we must access another device
+Only this sequence is important.  It does not matter that there is no
+BARRIER IO before the access to the SMC chip because the AEN latch
+only needs occurs after the SMC IO write cycle.  The routines that
+implement this work-around make an additional concession which is to
+disable interrupts during the IO sequence.  Other hardware devices
+(the LogicPD CPLD) have registers in the same the physical memory
+region as the SMC chip.  An interrupt might allow an access to one of
+those registers while SMC IO is being performed.
+
+You might be tempted to think that we have to access another device
 attached to the static memory controller, but the empirical evidence
 indicates that this is not so.  Mapping 0x00000000 (flash) and
 0xc0000000 (SDRAM) appear to have the same effect.  Using SDRAM seems
-to be faster.
+to be faster.  Choosing to access an undecoded memory region is not
+desirable as there is no way to know how that chip select will be used
+in the future.

drivers/net/smc91x.c

@@ -1244,6 +1244,11 @@ static irqreturn_t smc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 
 	spin_lock(&lp->lock);
 
+	/* A preamble may be used when there is a potential race
+	 * between the interruptible transmit functions and this
+	 * ISR. */
+	SMC_INTERRUPT_PREAMBLE;
+
 	saved_pointer = SMC_GET_PTR();
 	mask = SMC_GET_INT_MASK();
 	SMC_SET_INT_MASK(0);

drivers/net/smc91x.h

@@ -193,6 +193,53 @@ SMC_outw(u16 val, unsigned long ioaddr, int reg)
 #define RPC_LSA_DEFAULT		RPC_LED_TX_RX
 #define RPC_LSB_DEFAULT		RPC_LED_100_10
 
+#elif	defined(CONFIG_MACH_LPD7A400) || defined(CONFIG_MACH_LPD7A404)
+
+/* The LPD7A40X_IOBARRIER is necessary to overcome a mismatch between
+ * the way that the CPU handles chip selects and the way that the SMC
+ * chip expects the chip select to operate.  Refer to
+ * Documentation/arm/Sharp-LH/IOBarrier for details.  The read from
+ * IOBARRIER is a byte as a least-common denominator of possible
+ * regions to use as the barrier.  It would be wasteful to read 32
+ * bits from a byte oriented region.
+ *
+ * There is no explicit protection against interrupts intervening
+ * between the writew and the IOBARRIER.  In SMC ISR there is a
+ * preamble that performs an IOBARRIER in the extremely unlikely event
+ * that the driver interrupts itself between a writew to the chip an
+ * the IOBARRIER that follows *and* the cache is large enough that the
+ * first off-chip access while handing the interrupt is to the SMC
+ * chip.  Other devices in the same address space as the SMC chip must
+ * be aware of the potential for trouble and perform a similar
+ * IOBARRIER on entry to their ISR.
+ */
+
+#include <asm/arch/constants.h>	/* IOBARRIER_VIRT */
+
+#define SMC_CAN_USE_8BIT	0
+#define SMC_CAN_USE_16BIT	1
+#define SMC_CAN_USE_32BIT	0
+#define SMC_NOWAIT		0
+#define LPD7A40X_IOBARRIER	readb (IOBARRIER_VIRT)
+
+#define SMC_inw(a,r)		readw ((void*) ((a) + (r)))
+#define SMC_insw(a,r,p,l)	readsw ((void*) ((a) + (r)), p, l)
+#define SMC_outw(v,a,r)	     ({ writew ((v), (a) + (r)); LPD7A40X_IOBARRIER; })
+
+static inline void SMC_outsw (unsigned long a, int r, unsigned char* p, int l)
+{
+	unsigned short* ps = (unsigned short*) p;
+	while (l-- > 0) {
+		writew (*ps++, a + r);
+		LPD7A40X_IOBARRIER;
+	}
+}
+
+#define SMC_INTERRUPT_PREAMBLE	LPD7A40X_IOBARRIER
+
+#define RPC_LSA_DEFAULT		RPC_LED_TX_RX
+#define RPC_LSB_DEFAULT		RPC_LED_100_10
+
 #else
 
 #define SMC_CAN_USE_8BIT	1
@@ -894,5 +941,8 @@ static const char * chip_ids[ 16 ] =  {
 	})
 #endif
 
+#if !defined (SMC_INTERRUPT_PREAMBLE)
+# define SMC_INTERRUPT_PREAMBLE
+#endif
 
 #endif  /* _SMC91X_H_ */