Commit c5a8e907 authored by Zong-Zhe Yang's avatar Zong-Zhe Yang Committed by Kalle Valo

rtw88: fix RX clock gate setting while fifo dump

When fw fifo dumps, RX clock gating should be disabled to avoid
something unexpected. However, the register operation ran into
a mistake. So, we fix it.
Signed-off-by: default avatarZong-Zhe Yang <kevin_yang@realtek.com>
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20210927111830.5354-1-pkshih@realtek.com
parent a8e5387f
...@@ -1582,12 +1582,10 @@ static void rtw_fw_read_fifo_page(struct rtw_dev *rtwdev, u32 offset, u32 size, ...@@ -1582,12 +1582,10 @@ static void rtw_fw_read_fifo_page(struct rtw_dev *rtwdev, u32 offset, u32 size,
u32 i; u32 i;
u16 idx = 0; u16 idx = 0;
u16 ctl; u16 ctl;
u8 rcr;
rcr = rtw_read8(rtwdev, REG_RCR + 2);
ctl = rtw_read16(rtwdev, REG_PKTBUF_DBG_CTRL) & 0xf000; ctl = rtw_read16(rtwdev, REG_PKTBUF_DBG_CTRL) & 0xf000;
/* disable rx clock gate */ /* disable rx clock gate */
rtw_write8(rtwdev, REG_RCR, rcr | BIT(3)); rtw_write32_set(rtwdev, REG_RCR, BIT_DISGCLK);
do { do {
rtw_write16(rtwdev, REG_PKTBUF_DBG_CTRL, start_pg | ctl); rtw_write16(rtwdev, REG_PKTBUF_DBG_CTRL, start_pg | ctl);
...@@ -1606,7 +1604,8 @@ static void rtw_fw_read_fifo_page(struct rtw_dev *rtwdev, u32 offset, u32 size, ...@@ -1606,7 +1604,8 @@ static void rtw_fw_read_fifo_page(struct rtw_dev *rtwdev, u32 offset, u32 size,
out: out:
rtw_write16(rtwdev, REG_PKTBUF_DBG_CTRL, ctl); rtw_write16(rtwdev, REG_PKTBUF_DBG_CTRL, ctl);
rtw_write8(rtwdev, REG_RCR + 2, rcr); /* restore rx clock gate */
rtw_write32_clr(rtwdev, REG_RCR, BIT_DISGCLK);
} }
static void rtw_fw_read_fifo(struct rtw_dev *rtwdev, enum rtw_fw_fifo_sel sel, static void rtw_fw_read_fifo(struct rtw_dev *rtwdev, enum rtw_fw_fifo_sel sel,
......
...@@ -408,6 +408,7 @@ ...@@ -408,6 +408,7 @@
#define BIT_MFBEN BIT(22) #define BIT_MFBEN BIT(22)
#define BIT_DISCHKPPDLLEN BIT(21) #define BIT_DISCHKPPDLLEN BIT(21)
#define BIT_PKTCTL_DLEN BIT(20) #define BIT_PKTCTL_DLEN BIT(20)
#define BIT_DISGCLK BIT(19)
#define BIT_TIM_PARSER_EN BIT(18) #define BIT_TIM_PARSER_EN BIT(18)
#define BIT_BC_MD_EN BIT(17) #define BIT_BC_MD_EN BIT(17)
#define BIT_UC_MD_EN BIT(16) #define BIT_UC_MD_EN BIT(16)
......
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