drm/nouveau/fifo/gk104-: fix parsing of mmu fault data

Pascal was particularly incorrect, as the register changed to be more in the
same format as the MMU fault buffers are.

Shouldn't have impacted much more than confusing MMU fault log messages.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c

@@ -646,31 +646,6 @@ gk104_fifo_intr_dropped_fault(struct gk104_fifo *fifo)
 	nvkm_error(subdev, "DROPPED_MMU_FAULT %08x\n", stat);
 }
 
-static void
-gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit)
-{
-	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
-	struct nvkm_device *device = subdev->device;
-	u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
-	u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
-	u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
-	u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10));
-	struct nvkm_fault_data info;
-
-	info.inst   =  (u64)inst << 12;
-	info.addr   = ((u64)vahi << 32) | valo;
-	info.time   = 0;
-	info.engine = unit;
-	info.valid  = 1;
-	info.gpc    = (type & 0x1f000000) >> 24;
-	info.client = (type & 0x00001f00) >> 8;
-	info.access = (type & 0x00000080) >> 7;
-	info.hub    = (type & 0x00000040) >> 6;
-	info.reason = (type & 0x0000001f);
-
-	nvkm_fifo_fault(&fifo->base, &info);
-}
-
 static const struct nvkm_bitfield gk104_fifo_pbdma_intr_0[] = {
 	{ 0x00000001, "MEMREQ" },
 	{ 0x00000002, "MEMACK_TIMEOUT" },
@@ -849,7 +824,7 @@ gk104_fifo_intr(struct nvkm_fifo *base)
 		u32 mask = nvkm_rd32(device, 0x00259c);
 		while (mask) {
 			u32 unit = __ffs(mask);
-			gk104_fifo_intr_fault(fifo, unit);
+			fifo->func->intr.fault(&fifo->base, unit);
 			nvkm_wr32(device, 0x00259c, (1 << unit));
 			mask &= ~(1 << unit);
 		}
@@ -1204,6 +1179,7 @@ gk104_fifo_fault_gpcclient[] = {
 
 static const struct gk104_fifo_func
 gk104_fifo = {
+	.intr.fault = gf100_fifo_intr_fault,
 	.pbdma = &gk104_fifo_pbdma,
 	.fault.access = gk104_fifo_fault_access,
 	.fault.engine = gk104_fifo_fault_engine,

drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h

@@ -45,6 +45,10 @@ struct gk104_fifo {
 };
 
 struct gk104_fifo_func {
+	struct {
+		void (*fault)(struct nvkm_fifo *, int unit);
+	} intr;
+
 	const struct gk104_fifo_pbdma_func {
 		int (*nr)(struct gk104_fifo *);
 		void (*init)(struct gk104_fifo *);
@@ -110,12 +114,14 @@ void gk110_fifo_runlist_cgrp(struct nvkm_fifo_cgrp *,
 extern const struct gk104_fifo_pbdma_func gk208_fifo_pbdma;
 void gk208_fifo_pbdma_init_timeout(struct gk104_fifo *);
 
+void gm107_fifo_intr_fault(struct nvkm_fifo *, int);
 extern const struct nvkm_enum gm107_fifo_fault_engine[];
 extern const struct gk104_fifo_runlist_func gm107_fifo_runlist;
 
 extern const struct gk104_fifo_pbdma_func gm200_fifo_pbdma;
 int gm200_fifo_pbdma_nr(struct gk104_fifo *);
 
+void gp100_fifo_intr_fault(struct nvkm_fifo *, int);
 extern const struct nvkm_enum gp100_fifo_fault_engine[];
 
 extern const struct nvkm_enum gv100_fifo_fault_access[];

drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c

@@ -48,6 +48,7 @@ gk110_fifo_runlist = {
 
 static const struct gk104_fifo_func
 gk110_fifo = {
+	.intr.fault = gf100_fifo_intr_fault,
 	.pbdma = &gk104_fifo_pbdma,
 	.fault.access = gk104_fifo_fault_access,
 	.fault.engine = gk104_fifo_fault_engine,

drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c

@@ -45,6 +45,7 @@ gk208_fifo_pbdma = {
 
 static const struct gk104_fifo_func
 gk208_fifo = {
+	.intr.fault = gf100_fifo_intr_fault,
 	.pbdma = &gk208_fifo_pbdma,
 	.fault.access = gk104_fifo_fault_access,
 	.fault.engine = gk104_fifo_fault_engine,

drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c

@@ -26,6 +26,7 @@
 
 static const struct gk104_fifo_func
 gk20a_fifo = {
+	.intr.fault = gf100_fifo_intr_fault,
 	.pbdma = &gk208_fifo_pbdma,
 	.fault.access = gk104_fifo_fault_access,
 	.fault.engine = gk104_fifo_fault_engine,

drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c

@@ -25,6 +25,7 @@
 #include "changk104.h"
 
 #include <core/gpuobj.h>
+#include <subdev/fault.h>
 
 #include <nvif/class.h>
 
@@ -67,8 +68,33 @@ gm107_fifo_fault_engine[] = {
 	{}
 };
 
+void
+gm107_fifo_intr_fault(struct nvkm_fifo *fifo, int unit)
+{
+	struct nvkm_device *device = fifo->engine.subdev.device;
+	u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
+	u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
+	u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
+	u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10));
+	struct nvkm_fault_data info;
+
+	info.inst   =  (u64)inst << 12;
+	info.addr   = ((u64)vahi << 32) | valo;
+	info.time   = 0;
+	info.engine = unit;
+	info.valid  = 1;
+	info.gpc    = (type & 0x1f000000) >> 24;
+	info.client = (type & 0x00003f00) >> 8;
+	info.access = (type & 0x00000080) >> 7;
+	info.hub    = (type & 0x00000040) >> 6;
+	info.reason = (type & 0x0000000f);
+
+	nvkm_fifo_fault(fifo, &info);
+}
+
 static const struct gk104_fifo_func
 gm107_fifo = {
+	.intr.fault = gm107_fifo_intr_fault,
 	.pbdma = &gk208_fifo_pbdma,
 	.fault.access = gk104_fifo_fault_access,
 	.fault.engine = gm107_fifo_fault_engine,

drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c

@@ -42,6 +42,7 @@ gm200_fifo_pbdma = {
 
 static const struct gk104_fifo_func
 gm200_fifo = {
+	.intr.fault = gm107_fifo_intr_fault,
 	.pbdma = &gm200_fifo_pbdma,
 	.fault.access = gk104_fifo_fault_access,
 	.fault.engine = gm107_fifo_fault_engine,

drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c

@@ -26,6 +26,7 @@
 
 static const struct gk104_fifo_func
 gm20b_fifo = {
+	.intr.fault = gm107_fifo_intr_fault,
 	.pbdma = &gm200_fifo_pbdma,
 	.fault.access = gk104_fifo_fault_access,
 	.fault.engine = gm107_fifo_fault_engine,

drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c

@@ -24,6 +24,8 @@
 #include "gk104.h"
 #include "changk104.h"
 
+#include <subdev/fault.h>
+
 #include <nvif/class.h>
 
 const struct nvkm_enum
@@ -50,8 +52,33 @@ gp100_fifo_fault_engine[] = {
 	{}
 };
 
+void
+gp100_fifo_intr_fault(struct nvkm_fifo *fifo, int unit)
+{
+	struct nvkm_device *device = fifo->engine.subdev.device;
+	u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
+	u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
+	u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
+	u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10));
+	struct nvkm_fault_data info;
+
+	info.inst   =  (u64)inst << 12;
+	info.addr   = ((u64)vahi << 32) | valo;
+	info.time   = 0;
+	info.engine = unit;
+	info.valid  = 1;
+	info.gpc    = (type & 0x1f000000) >> 24;
+	info.hub    = (type & 0x00100000) >> 20;
+	info.access = (type & 0x00070000) >> 16;
+	info.client = (type & 0x00007f00) >> 8;
+	info.reason = (type & 0x0000001f);
+
+	nvkm_fifo_fault(fifo, &info);
+}
+
 static const struct gk104_fifo_func
 gp100_fifo = {
+	.intr.fault = gp100_fifo_intr_fault,
 	.pbdma = &gm200_fifo_pbdma,
 	.fault.access = gk104_fifo_fault_access,
 	.fault.engine = gp100_fifo_fault_engine,

drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp10b.c

@@ -26,6 +26,7 @@
 
 static const struct gk104_fifo_func
 gp10b_fifo = {
+	.intr.fault = gp100_fifo_intr_fault,
 	.pbdma = &gm200_fifo_pbdma,
 	.fault.access = gk104_fifo_fault_access,
 	.fault.engine = gp100_fifo_fault_engine,